CN210016555U - High definition video acquisition system based on FPGA - Google Patents

Abstract

The utility model discloses a high definition video acquisition system based on FPGA contains video acquisition module, FPGA main control module, data cache module, HDMI interface circuit, FPGA main control module contains camera control module, logic control unit, HDMI interface chip the control unit, DDR3-SDRAM buffer control unit to and supply circuit, reset circuit, crystal oscillator circuit, download circuit and configuration SPI Flash circuit, the system uses OminiVision company's 500 ten thousand pixel level CMOS image sensor OV5640 to gather the camera as the front end, use Xilinx company Spartan6 series FPGA as main control chip, regard 4 Gbit capacity DDR3-SDRAM as the buffer chip, recombine MCB hardcore, MIG IP nuclear and ping-pong operation, realize the high-efficient buffer memory of video data; meanwhile, the SiI9134 of the Silion Image company is used as an HDMI chip, so that full high-definition video can be effectively supported.

Description

High definition video acquisition system based on FPGA

Technical Field

The utility model belongs to data acquisition control field especially relates to a synchronous real-time high-speed data acquisition system of multichannel based on FPGA.

Background

With the continuous development of scientific technology, digital image acquisition and transmission technology is increasingly widely applied in the fields of video monitoring, information processing, industrial control, scientific research and the like, and the application puts higher and higher requirements on the acquisition and transmission speed of a system. The development of a high-speed CMOS image acquisition system is greatly accelerated by the progress of a micro-nano electronic technology and the progress of an electronic design level, and particularly, the performance improvement in the aspects of high frame rate, high resolution and the like is very obvious, so that the data volume is inevitably increased. This requires the data acquisition system to have the ability to read data quickly, allowing the system to process large amounts of data in a minimum amount of time, while passing the data to the host for display or subsequent processing. Since the first USB interface technology concept proposed in 1994, USB bus interface technology has undergone USB 1.0, USB 1.x, USB2.0, and USB3.0 versions, and is now becoming the standard interface for devices such as mobile phones, tablet computers, and personal PCs. The USB3.0 serial universal bus is widely applied to various fields due to the characteristics of high transmission rate, convenience in use, plug and play, hot plug support and the like. The USB3.0 interface (theoretical transmission rate 5 Gbps) has partially replaced USB2.0 as the standard interface of the computer motherboard, and the USB interface bus also retains good backward compatibility in the new and old versions which are continuously developed, which is one of the reasons for its wide application

With the development of video display technology, video signals are developed from the former standard definition to high definition and then to full high definition, the resolution of the video signals is higher and higher, and the data volume is multiplied, so that the high-speed development of the display interface technology is promoted, and the display interface technology is developed through a development process from analog to digital, from parallel to serial, and from low speed to high speed. The HDMI interface is the newest high definition multimedia interface, and compared with the DVI interface, the HDMI interface has smaller size, larger bandwidth, longer transmission distance and higher supported resolution, can transmit video signals and audio signals, and has the copyright protection function. The HDMI interface has become one of the standard interfaces of devices such as liquid crystal displays, tablet personal computers, and notebook computers, and is widely used.

With the rapid development of scientific technology, data acquisition systems have been widely applied to various fields such as aerospace, military, industry, medical treatment and the like, and especially play a vital role in detection and monitoring projects of high-precision products. In practical engineering application, the acquisition system is required to have the characteristics of high speed, high precision, real-time processing, good system stability, large number of channels and the like. However, most of the conventional data acquisition schemes use an ARM processor (ARM) or a Digital Signal Processor (DSP) as a control core, and cannot effectively solve the technical problems of real-time performance and synchronization in high-speed data acquisition Processing.

Compared with DSP and ARM, FPGA has an extremely important position in the field of data acquisition. The FPGA has the advantages of high clock frequency, small internal delay, pure hardware parallel control, high operation speed, flexible programming configuration, short development period, strong anti-interference capability, rich internal resources and the like, and is very suitable for real-time high-speed data acquisition.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that the synchronism of data in transmission and storage process, real-time nature problem can not be realized effectively to traditional data acquisition processing system, the invention discloses a full high-definition video acquisition display system, the system uses 500 ten thousand pixel level CMOS image sensor OV5640 of OminiVision company as the front end and gathers the camera, use Xilinx company Spartan DDR 6 series FPGA as the main control chip, use 4 Gbit capacity 3-SDRAM as the buffer chip, recombine MCB hardcore, MIG IP nuclear and ping-pong operation, realize the high-efficient buffer memory of video data; meanwhile, the SiI9134 of the SilionImage company is used as an HDMI chip, so that full-high-definition video can be effectively supported.

The utility model adopts the following technical scheme to solve the technical problems

A high-definition video acquisition system based on FPGA comprises a video acquisition module, an FPGA main control module, a data cache module and an HDMI interface circuit, wherein the video acquisition module, the data cache module and the HDMI interface circuit are respectively and electrically connected with the FPGA main control module; the FPGA main control module comprises a camera control module, a logic control unit, an HDMI interface chip control unit, a DDR3-SDRAM cache control unit, a power supply circuit, a reset circuit, a crystal oscillator circuit, a download circuit and a configuration SPIFlash circuit, wherein the camera control module, the logic control unit, the HDMI interface chip control unit, the DDR3-SDRAM cache control unit, the power supply circuit, the reset circuit, the crystal oscillator circuit, the download circuit and the configuration SPI Flash circuit are respectively and electrically connected with the logic control unit.

As the utility model relates to a high definition video acquisition system's further preferred scheme based on FPGA, OmniVision company OV5640 camera is chooseed for use to the video acquisition module, and it is 500 ten thousand pixel rank CMOS image sensor, and support resolution ratio can reach the 2K rank, can export multiple image format data.

As a further preferred scheme of the high definition video acquisition system based on FPGA, the logic control unit adopts Xilinx company Spartan6 series chip XC6SLX 45.

As the utility model relates to a high definition video acquisition system's further preferred scheme based on FPGA, data cache module chooses for use 4 Gbit capacity DDR3-SDRAM memory chip MT41J256M16HA-125 of Micron company as the buffer medium.

As the utility model relates to a high definition video acquisition system's further preferred scheme based on FPGA, HDMI interface module chooses for use the SiI9134 as HDMI output interface chip.

As the utility model relates to a high definition video acquisition system's further preferred scheme based on FPGA still contains gating switch accuse module, video acquisition module passes through switch accuse module and connects FPGA host system, gating switch accuse module contains TTL level conversion unit, coaxial switch unit and analog signal switch unit for realize the input signal gating and the power on-off control of equipment under test, make equipment under test can enter into monitoring state safely fast.

The utility model adopts the above technical scheme to compare with prior art, have following technological effect:

1. the utility model discloses a full high-definition video acquisition display system, the system uses 500 ten thousand pixel level CMOS image sensor OV5640 of OminiVision company to gather the camera as the front end, uses Xilinx company Spartan6 series FPGA as the main control chip, uses 4 Gbit capacity DDR3-SDRAM as the buffer memory chip, and combines MCB hardcore, MIG IP core and ping-pong operation again, realizes the high-efficient buffer memory of video data; meanwhile, the SiI9134 of the Silion Image company is used as an HDMI chip, so that full high-definition video can be effectively supported. The system can stably acquire and display full-high-definition videos, has high display quality and no smear phenomenon, and can be applied to the fields of military monitoring systems, civil multimedia systems, medicine and the like.

Drawings

FIG. 1 is a schematic diagram of the overall system architecture of the present invention;

fig. 2 is a schematic diagram of the overall system architecture of the present invention.

Detailed Description

The technical scheme of the utility model is further explained in detail with the attached drawings as follows:

the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

A high-definition video acquisition system based on FPGA (field programmable gate array) is shown in figure 1 and comprises a video acquisition module, an FPGA main control module, a data cache module and an HDMI (high-definition multimedia interface) interface circuit, wherein the video acquisition module, the data cache module and the HDMI interface circuit are respectively and electrically connected with the FPGA main control module;

as shown in fig. 2, the FPGA main control module includes a camera control module, a logic control unit, an HDMI interface chip control unit, a DDR3-SDRAM cache control unit, a power supply circuit, a reset circuit, a crystal oscillator circuit, a download circuit, and a configuration SPI Flash circuit, and the camera control module, the logic control unit, the HDMI interface chip control unit, the DDR3-SDRAM cache control unit, the power supply circuit, the reset circuit, the crystal oscillator circuit, the download circuit, and the configuration SPI Flash circuit are electrically connected to the logic control unit, respectively.

The video acquisition module is connected with the FPGA main control module through the switch control module, and the gating switch control module comprises a TTL level conversion unit, a coaxial switch switching unit and an analog signal switching unit and is used for realizing input signal gating and power on-off control of the equipment to be detected, so that the equipment to be detected can safely and quickly enter a monitoring state.

The specific embodiment is as follows: the system mainly comprises a video acquisition module, an FPGA main control module, a data cache module and an HDMI interface circuit. The video acquisition module provides a full high-definition video data source, and before the acquisition of the full high-definition video data source, the FPGA main Control module is required to send Camera configuration information to a register in a Camera through an SCCB (Serial Camera Control bus); the FPGA main control module is a control core of the system and controls the camera, the DDR3-SDRAM, the HDMI interface chip and the video data stream; the data cache module takes a 4 Gbit DDR3-SDRAM as a cache medium, so that the cache problem of high-speed large-capacity data can be effectively solved; the HDMI interface circuit mainly comprises an HDMI interface chip which is used for realizing parallel-serial conversion of video data; and finally, the serial video data is transmitted to a display supporting the HDMI through an HDMI transmission line, so that full high-definition video images can be displayed in real time.

2.1 video acquisition Module

The video acquisition module adopts an OmniVision OV5640 camera which is a 500 ten thousand pixel level CMOS image sensor, supports the resolution up to 2K level, can output data in various image formats and supports various self-adaptive adjustment functions. The CMOS image sensor supports two data interfaces of DVP and MIPI, and the DVP interface is selected in the system. Sensor register information needs to be configured to the sensors through the SCCB bus before the master control module obtains the data. The CMOS image sensor image data output format in the system is configured to be RGB24, the video resolution is configured to be 1920 x 1080 (full high definition), the video frame rate is configured to be 30 f/s, and the module further comprises a digital and an analog power supply circuit.

2.2 FPGA Master control Module

The chip selected by the system control core is a Spartan6 series chip XC6SLX45 of Xilinx company, and a Spartan6 FPGA of the sixth generation Spartan series product provides a high-level power consumption management technology, 150000 logic units, a hardmac DRAM memory, various IPs and the like based on the accepted process technology of low power consumption 45 nm, 9-metallic copper layers and double gate oxide layers, and is an FPGA series with the most extensive application and mature technology of the Xilinx company. The FPGA main control module mainly completes the configuration of a camera, the acquisition of video data, the access of DDR3-SDRAM data, the configuration of an HDMI interface chip and the transmission of the video data, and a hardware circuit of the FPGA main control module also comprises a power supply circuit, a reset circuit, a crystal oscillator circuit, a download circuit and a configuration SPI Flash circuit.

2.3 data cache Module

In order to solve the problem of caching high-speed large-capacity video data, the system selects 4 Gbit capacity DDR3-SDRAM memory chip MT41J256M16HA-125 of Micron company as a caching medium. A0-A14 are address buses, B0-B3 are Bank addresses, and the storage position of data in the DDR3-SDRAM can be controlled by the FPGA by controlling the address buses and the Bank addresses; D0-D15 are data buses and are connected with the FPGA in parallel; CLK-N and CLK-P are differential clock input ports, and the clock frequency is set to be 312.5 MHz in the system; the FPGA performs read-write control on DDR3-SDRAM through a column address selection signal (CAS), a row address selection signal (RAS) and a write enable signal (WE), and prevents data line interruption reflection by controlling the optimization performance of on-chip resistance of the ODT enable; DQS is a synchronization signal between DDR3-SDRAM and the controller, which is a bidirectional signal that is issued by the controller when data is written and issued by the memory when data is read; DM is a data mask signal. Since the Spartan6 FPAG has MCB hardcores only in Bank1 and Bank3, in the system, the Bank3 is connected with DDR3-SDRAM, the port voltage standard is 1.5V, and in the FPAG UCF, the IO standard needs to be SSTL15_ II.

2.4 HDMI interface module

In the system, the SiI9134 is selected as an HDMI output interface chip, and the hardware connection relationship between the chip and the FPAG is shown in fig. 2. Before the chip works, register information needs to be configured into the chip through an I2C (SCL, SDA) bus, the frequency is 100 kHz in the configuration process, the data input format is configured to be RGB24, and the video output resolution is configured to be 1920 x 1080; CLK is a video data synchronous clock, the clock of the chip 1080p video format is 148.5 MHz, DE is a data effective signal, and high level is effective; HS and VS are line synchronous signal and field synchronous signal respectively; d [23:0] is RGB24 data input bus, R, G, B component data bus from top to bottom in turn, in order to support other video data formats, the bus width of SiI9134 is 36 bit, only 24 bit is used in the system, and the pins of the rest data bus are grounded; the SiI9134 supports a variety of digital audio signal input interfaces including S/PDIF, I2S, etc., and audio interfaces are not used in the present system. After being encoded by the SiI9134, the RGB24 format video data is converted into serial data, and then the serial data is transmitted to a display through a connector and a transmission line, and finally, full high-definition video is displayed.

3 control logic design

The design of the control logic of the system comprises OV5640 configuration and video data acquisition logic, DDR3-SDRAM data access control logic, SiI9134 configuration and video data sending logic. The system receives video data in an RGB24 format through a DVP port, stores the video data into DDR3-SDRAM in different areas, and reads out the video data from the DDR3-SDRAM and sends the video data to an HDMI interface chip for display of a display screen. After power-on, the system firstly performs reset operation and then enters an initialization state, the system sends configuration information to the OV5640 and the SiI9134, and the DDR3-SDRAM also starts to enter initialization and verification processes. After all initialization work is finished, the system judges whether OV5640 is configured or not, if the configuration is finished, the system acquires video data and stores the video data into DDR 3-SDRAM. When the buffer area has data and the configuration of the SiI9134 is finished, the system reads out the video data in the buffer area and sends the video data to the SiI 9134.

3.1 video acquisition control section

The OV5640 has certain requirements on the power-on time sequence, so a module meeting the power-on time sequence is necessary, after initialization is completed, the working mode of the OV5640 is determined firstly, and the initialization can be completed through an SCCB bus, and 303 registers are configured in the system; after OV5640 configuration and DDR3-SDRAM initialization and calibration are completed, video data can be obtained; control OV5640 requires a system clock XVCLK to be 192 MHz and then identifies the pixel output clock (PCLK), the field sync signal (VSYNC), and the row sync signal (HREF) to acquire data. The falling edge of the field synchronizing signal represents the beginning of one frame of data, the line synchronizing signal is effective data output when being at high level, and the line synchronizing signal can have high level for 1080 times between the low levels of the field synchronizing signal, which represents that one frame of data has 1080 lines of data; the column sync signal is high for 1920 pixel output clocks, which represents 1920 pixels per column.

3.2 DDR3-SDRAM buffer control part

DDR3-SDRAM data access uses a MIG IP core provided by a spark 6 series FPGA, and meanwhile, an MCB hard core is required to exchange data with an external SDRAM chip. After an SDRAM controller is generated in an Xilinx compiling environment ISE, a MIG IP core user interface can be used for data access, the MIG IP core in the system is configured into two bidirectional ports with 64-bit width, one port is used for writing data, and the other port is used for reading data. A write data FIFO and a read data FIFO are respectively added at the front end and the rear end of the MIG IP core, and the logic for calling the cache module is equivalent to a large-capacity FIFO. In the MIG IP core, a ping-pong operation mode is adopted to improve the caching efficiency, in the caching process, a storage area with the capacity of 4 Gbit is divided into N areas, the capacity of each area is the capacity of one frame of video data, in the writing process, data is written into a1 st area, after the 1 st area is fully written, the next area (a 2 nd area, the data of the area is ensured to be empty when the next area is written), at the moment, the data of the 1 st area can be read, after the 1 st area is completely read, the next area (a 2 nd area, the data of the area is ensured to be full when the next area is read) is read and written circularly according to the sequence, and the ping-pong operation is completed. The caching mode can greatly improve the caching efficiency of the video data, effectively solve the caching problem of high-speed large-capacity data, enable one frame of video data to be continuous, avoid the condition of data intersection (addresses cannot be intersected), and avoid the phenomenon of smear of video display.

3.3 HDMI interface control section

Before the HDMI works, data needs to be configured to the register through an I2C bus, the data format is configured to be RGB24, the resolution is 1920 × 1080, and the video frame rate is 30 f/s. After configuration is completed, when the buffer area is full of data, the video data can be read and sent to the SiI9134 according to a specific time sequence, the SiI9134 sends the data at the time sequence, the falling edge of the line synchronizing signal represents the beginning of one frame of video data, the rising edge represents the end of one frame of data, the next line of data is sent after one line of data is sent, and the first line of data of the next frame of picture is sent after the last line of data of one frame of data is sent. The data is sent in a repeated cycle, DE is a data effective signal, and high level is effective.

The points to be finally explained are: first, in the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounted," "connected," and "connected" should be understood broadly, and may be a mechanical connection or an electrical connection, or a communication between two elements, and may be a direct connection, and "upper," "lower," "left," and "right" are only used to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed;

secondly, the method comprises the following steps: in the drawings of the disclosed embodiments of the present invention, only the structures related to the disclosed embodiments are referred to, and other structures can refer to the common design, and under the condition of no conflict, the same embodiment and different embodiments of the present invention can be combined with each other;

and finally: the above description is only for the preferred embodiment of the present invention and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. The utility model provides a high definition video acquisition system based on FPGA which characterized in that: the system comprises a video acquisition module, an FPGA main control module, a data cache module and an HDMI interface circuit, wherein the video acquisition module, the data cache module and the HDMI interface circuit are respectively and electrically connected with the FPGA main control module; the FPGA main control module comprises a camera control module, a logic control unit, an HDMI interface chip control unit, a DDR3-SDRAM cache control unit, a power supply circuit, a reset circuit, a crystal oscillator circuit, a download circuit and a configuration SPI Flash circuit, wherein the camera control module, the logic control unit, the HDMI interface chip control unit, the DDR3-SDRAM cache control unit, the power supply circuit, the reset circuit, the crystal oscillator circuit, the download circuit and the configuration SPI Flash circuit are respectively and electrically connected with the logic control unit.

2. The FPGA-based high-definition video acquisition system of claim 1, characterized in that: the video acquisition module adopts an OmniVision OV5640 camera which is a 500 ten thousand pixel-level CMOS image sensor, supports the resolution up to 2K level and can output data in various image formats.

3. The FPGA-based high-definition video acquisition system of claim 1, characterized in that: the logic control unit adopts Xilinx Spartan6 series chip XC6SLX 45.

4. The FPGA-based high-definition video acquisition system of claim 1, characterized in that: the data cache module selects 4 Gbit capacity DDR3-SDRAM memory chip MT41J256M16HA-125 of Micron company as a cache medium.

5. The FPGA-based high-definition video acquisition system of claim 1, characterized in that: the HDMI interface module selects SiI9134 as an HDMI output interface chip.

6. The FPGA-based high-definition video acquisition system of claim 2, characterized in that: the video acquisition module is connected with the FPGA main control module through the switch control module, and the gating switch control module comprises a TTL level conversion unit, a coaxial switch switching unit and an analog signal switching unit and is used for realizing input signal gating and power on-off control of the equipment to be detected, so that the equipment to be detected can safely and quickly enter a monitoring state.

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