CN213025335U - Display control apparatus and display system - Google Patents
Display control apparatus and display system Download PDFInfo
- Publication number
- CN213025335U CN213025335U CN202021704535.4U CN202021704535U CN213025335U CN 213025335 U CN213025335 U CN 213025335U CN 202021704535 U CN202021704535 U CN 202021704535U CN 213025335 U CN213025335 U CN 213025335U
- Authority
- CN
- China
- Prior art keywords
- data
- main processing
- processing circuit
- display control
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the present application relates to a display control apparatus, including: the main processing circuit board card is provided with a main processing circuit; the data interface board card is detachably connected with the main processing circuit board card; wherein, the data interface integrated circuit board includes: the data conversion circuit is connected with the main processing circuit; and the data transmission interface is connected with the data conversion circuit. In this embodiment, the data interface board card is detachably connected to the main processing circuit board card to control the number change of the data transmission interfaces, so as to flexibly change the loading capacity of the data transmission interfaces.
Description
Technical Field
The present application relates to the field of video devices, and in particular, to a display control device and a display system.
Background
With the development of science and technology, display screens are also increasingly applied.
At present, the method for realizing video output mainly comprises the following steps: firstly, video source signals are input and then transmitted to the programmable logic device to generate video data, then the programmable logic device is sent to the PHY chip through the output interface, the PHY chip is sent to the network port, the network port outputs the video data to the display screen for display, and the programmable logic device, the PHY chip and the network port are integrated on one board card for realization.
However, in the modules of the programmable logic device, the PHY chip, and the network port, the number of the network ports with loads is determined, and when the number of the network ports with loads is more, the module function and the network port need to be redesigned, which results in an increase in design cost and an inability to flexibly change the number of the network ports with loads.
SUMMERY OF THE UTILITY MODEL
Therefore, to overcome the defects and shortcomings of the prior art, embodiments of the present application provide a display control apparatus and a display system.
In one aspect, an embodiment of the present application provides a display control apparatus, including: the main processing circuit board card is provided with a main processing circuit; the data interface board card is detachably connected with the main processing circuit board card; wherein, the data interface integrated circuit board includes: the data conversion circuit is connected with the main processing circuit; and the data transmission interface is connected with the data conversion circuit.
In the prior art, in modules such as a programmable logic device, a PHY chip, and a port, the number of load capacity of the port is determined, and when the number of load capacity of the port is more, the module function and the port need to be redesigned, which results in an increase in design cost and an inability to flexibly change the number of load capacity of the port. According to the data transmission interface card, the data interface card part is independent, when the carrying capacity of the data transmission interface is required to be changed, the number of the data transmission interfaces corresponding to the carrying capacity of the data transmission interface in the data interface card is only required to be detachably connected with the main processing circuit card, so that the purpose of flexibly changing the carrying capacity of the data transmission interface is achieved, and the design cost is reduced.
In one embodiment of the present application, the data conversion circuit includes: and the signal conversion chip is connected with the main processing circuit.
In one embodiment of the present application, the data transmission interface includes at least one network port, and the at least one network port is connected to the signal conversion chip.
In one embodiment of the present application, the data conversion circuit further includes: and the network transformer is connected between the signal conversion chip and the network port.
In one embodiment of the present application, the data conversion circuit includes: and the photoelectric conversion circuit is connected with the programmable logic device and the microprocessor.
In one embodiment of the present application, the data transmission interface includes at least one optical port, and the at least one optical port is connected to the photoelectric conversion circuit.
In one embodiment of the present application, the main processing circuit includes a microprocessor connected to the data conversion circuit; the microprocessor is provided with a configuration signal transmission channel and a reset signal transmission channel, and is connected with the data conversion circuit through the configuration signal transmission channel and the reset signal transmission channel.
In an embodiment of the present application, the main processing circuit board is further provided with a first connector, and the first connector connects the data interface board and the main processing circuit.
In an embodiment of the present application, the data interface board further includes: and a second connector connecting the data conversion circuit and the first connector.
On the other hand, an embodiment of the present application provides a display system, including: a display screen; and a display control apparatus as described above; the display control equipment is connected with the display screen through the data transmission interface of the data interface board card.
As can be seen from the above, the above technical features of the present application may have the following beneficial effects: according to the data transmission interface card, the data interface card part is independent, when the carrying capacity of the data transmission interface is required to be changed, the number of the data transmission interfaces corresponding to the carrying capacity of the data transmission interface in the data interface card is only required to be detachably connected with the main processing circuit card, so that the purpose of flexibly changing the carrying capacity of the data transmission interface is achieved, and the design cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a block diagram of a display control apparatus according to an embodiment of the present application.
Fig. 2 is a block diagram of another display control apparatus according to an embodiment of the present application.
Fig. 3 is a block diagram of a data interface board card according to an embodiment of the present application.
Fig. 4 is a block diagram of another data interface board card according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of an embodiment of a display control apparatus according to an embodiment of the present application.
Fig. 6 is a circuit diagram of a portion of pins and a socket of a 88E1680 signal conversion chip according to an embodiment of the present invention.
Fig. 7 is a circuit diagram of a portion of pins of the 88E1680 signal conversion chip and a main processing circuit according to an embodiment of the present invention.
Fig. 8 is a block diagram of a display system according to an embodiment of the present application.
[ brief description of the drawings ]
10: a display control device; 11: a main processing circuit board card; 12: a data interface board card; 111: a main processing circuit; 1111: a programmable logic device; 1112: a microprocessor; 11121: configuring a signal transmission channel; 11122: a reset signal transmission channel; 112: a first connector; 121: a data conversion circuit; 122: a data transmission interface; 123: a second connector; 1211: a signal conversion chip; 1212: a network transformer; 1213: a photoelectric conversion circuit; 1221: a network port; 1222: a light port;
20: a display system; 21: a display screen.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work according to the embodiments of the present application are within the scope of the present application.
[ first embodiment ] A method for manufacturing a semiconductor device
As shown in fig. 1-2, fig. 1 is a block diagram of a display control device according to an embodiment of the present disclosure. The display control apparatus 10 includes: a main processing circuit board card 11 and a data interface board card 12.
The main processing circuit board card 11 is provided with a main processing circuit 111;
the data interface board card 12 is detachably connected with the main processing circuit board card 11.
The data interface board 12 includes a data conversion circuit 121 and a data transmission interface 122; the data conversion circuit 121 is connected to the main processing circuit 111; the data transmission interface 122 is connected to the data conversion circuit 121.
The main processing circuit 11 in the main processing circuit board 11 sends a series of data to the data conversion circuit 121 in the data interface board 12, where the series of data includes: data transmission interface configuration data, data conversion circuit state change data, video data, picture data, and the like, where the data transmission interface configuration data may be set by the main processing circuit board card 11, and is not limited herein. In this application, the data transmission interface configuration data is obtained by setting the main processing circuit board 11, for example, the user needs 6 data transmission interfaces, and then the user directly selects the data interface board of the 6 data transmission interfaces to be detachably connected with the main processing circuit board 11, and then the main processing circuit board 11 sets 6 data transmission interfaces to generate data transmission interface configuration data correspondingly. The content in the configuration data of the data transmission interface may also be added according to actual requirements, and is not limited herein. After the data interface board 12 completes configuration of the data according to the data transmission interface configuration, the main processing circuit 111 in the main processing circuit board 11 outputs data through the data transmission interface 122 in the data interface board 12.
After receiving the data sent by the main processing circuit 111, the data conversion circuit 121 in the data interface board 12 converts the received data, and converts the received data into data that can be recognized by the data conversion circuit 121 or data that can be output by the data transmission interface 122.
The data transmission interface 122 in the data interface board 12 receives the data sent by the data conversion circuit 121, and then the data transmission interface 122 outputs the converted data. The data transmission interface 122 outputs the converted data to a display screen for displaying.
In the prior art, in modules of a programmable logic device, a PHY chip and a port, the number of load carrying capacity of the port is determined, and when the number of load carrying capacity of the port is more, the module function and the port need to be redesigned, thereby increasing the design cost and failing to achieve the purpose of flexible change of the number of load carrying capacity of the port. According to the data transmission interface card, the data interface card part is independent, when the carrying capacity of the data transmission interface is required to be changed, the number of the data transmission interfaces corresponding to the carrying capacity of the data transmission interface in the data interface card is only required to be detachably connected with the main processing circuit card, so that the purpose of flexibly changing the carrying capacity of the data transmission interface is achieved, and the design cost is reduced.
As shown in fig. 1 to 5, the main processing circuit 111 includes, for example: a programmable logic device 1111 and a microprocessor 1112.
Wherein, the Programmable logic device 1111 (for example, FPGA (Field-Programmable Gate Array) shown in fig. 5) is connected to the data conversion circuit 121 in the data interface board 12 and the microprocessor 1112 (for example, MCU (Microcontroller Unit) shown in fig. 5); the microprocessor 1112 is connected to the data conversion circuit 121 in the data interface board 12.
The programmable logic device 1111 sends the video data to the data conversion circuit 121, and then the data conversion circuit 121 outputs the video data that can be output by the video data conversion data transmission interface 122. The programmable logic device 1111 may further send picture data, and the data sent by the programmable logic device 1111 may be set according to an actual scene requirement, for example, a display screen needs to display a video or a picture, and the like, and then according to a requirement of the display screen, which is not limited herein. The programmable logic device 1111 is, for example, 7a 50T.
The microprocessor 1112 sets data to be configured first, then generates data transmission interface configuration data according to the set accompanying data, and sends the data transmission interface configuration data to the data conversion circuit 121, and then the data conversion circuit 121 controls the number of the data transmission interfaces 122 in the data interface board card 12 to output the data. The microprocessor 1112 is, for example, STM32F103 or GD32F 303. The microprocessor 1112 is provided with a configuration signal transmission channel 11121 and a reset signal transmission channel 11122, and the microprocessor 1112 is connected to the data conversion circuit 121 through the configuration signal transmission channel 11121 and the reset signal transmission channel 11122.
As shown in fig. 2, the main processing circuit board 11 is provided with a first connector 112; the data interface board card 12 is provided with a second connector 123.
Wherein the first connector 112 connects the data interface board 12, the programmable logic device 1111 and the microprocessor 1112.
The second connector 123 connects the data conversion circuit 121 and the first connector 112.
The first connector 112 and the second connector 123 are plug-in connectors. In this embodiment, the first connector 112 and the second connector 123 may be pin header connectors, that is, the first connector 112 is a pin header and the second connector 123 is a female header or a wire terminal, or the first connector 112 is a female header or a wire terminal and the second connector 123 is a pin header. In other embodiments, the first connector 112 and the second connector 123 may be other plug connectors, such as a press-fit connector. The details are not limited herein.
As shown in fig. 3, the data conversion circuit 121 includes, for example: a signal conversion chip 1211 and a network transformer 1212; the data transmission interface 122 includes, for example, at least one network port 1221.
The signal conversion chip 1211 is connected to the main processing circuit 111, and the network transformer 1212 is connected between the signal conversion chip 121 and the network port 1221.
The signal conversion chip 1211 performs conversion after receiving the relevant signal, converts the relevant signal into required data or a signal, and then the signal conversion chip 1211 controls the output of the network interface 1221 according to the data transmission interface configuration data, in this embodiment, after the signal conversion chip 1211 receives the data transmission interface configuration data sent by the main processing circuit 111, the signal conversion chip 1211 controls the output of the at least one network interface 1221. For example, the main processing circuit board 11 needs 6 network ports for output, first, the data transmission interface 122 on the data interface board 12 is provided with a data transmission interface 122 with 6 network ports, and then the data interface board 12 with 6 network ports is connected to the main processing circuit board 11. Then, the main processing circuit 111 generates data transmission interface configuration data according to the number of the network ports required to be output, and sends the data transmission interface configuration data to the signal conversion chip 1211. The signal conversion chip 1211 uses 6 net ports 1221 to output according to the data transmission interface configuration data. In this embodiment, the signal conversion chip 1211 employs an 88E1680 chip in the PHY chip, and a specific circuit connection relationship between the 88E1680 chip and the main processing circuit 11 is shown in fig. 7. In other embodiments, the signal conversion chip 1211 may adopt an RTL8218 chip or an AR8033 chip or an RTL8211 chip or a B50621 chip, etc. in a PHY chip, as long as the signal conversion function can be realized, and any chip that does not perform any processing function on the signal and then controls the network port to output the signal can be adopted.
The number of the signal conversion chips 1211 can be changed according to the number of the set network ports 1221, for example, the signal conversion chip 1211 employs 88E1680 chip, the 88E1680 chip has 8 network ports, when the main processing circuit 111 needs less than 8 network ports for output, only one 88E1680 chip needs to be set, when the main processing circuit 111 needs more than 8 network ports for output, a plurality of 88E1680 chips can be set, that is, at least one signal conversion chip 1211 can be set according to the selected signal conversion chip type and the actual requirement. When a plurality of signal conversion chips 1211 are provided, the data interface board 12 including the plurality of signal conversion chips 1211 directly performs balanced distribution on the power of the network port 1221, so as to prevent the power of one of the signal conversion chips 1211 from affecting the overall output state and speed. For example, there are 10 network ports 1221 for output, 2 signal conversion chips 1211 are needed, and then the 10 network ports are distributed in an equalizing manner, where one signal conversion chip controls 4 network ports for output, and the other signal conversion chip controls 6 network ports for output. The circuit connection diagram of the 88E1680 chip and at least one network port is shown in FIG. 6.
The at least one portal 1221 is at least one gigabit portal 1221, that is, in this embodiment, the at least one portal 1221 all uses the gigabit portal 1221 to output, and the at least one portal 1221 outputs video data or picture data. For example, a user needs 5 network ports to output, then the main processing circuit 111 generates corresponding data transmission interface configuration data, then the signal conversion chip 1211 performs conversion identification on the data transmission interface configuration data, and the signal conversion chip 1211 controls 5 network ports 1221 to output according to the converted data transmission interface configuration data. The number of the network ports 1221 can be set correspondingly according to the requirements of the user, for example, if the user needs 6 network ports, 6 network ports 1221 are set on the data interface board card.
The network transformer 1212 prevents external signals from interfering with the signal conversion chip 1211 and the network ports 1221, where the number of the network transformers 1212 is the same as the number of the network ports in the data interface board, that is, each of the network ports 1221 in the multiple network ports 1221 is connected to one network transformer 1212, that is, the network ports 1221 and the network transformers 1212 are in a one-to-one correspondence relationship, so as to prevent each of the network ports 1221 from interfering with the external signals, and the network transformer 1212 is, for example, SG 48001G. The network transformer 1212 is mainly used for signal level coupling, which can enhance the signal transmission distance, and moreover, when receiving the network ports of different levels (for example, some signal conversion chips are at a level of 2.5V, and some signal conversion chips are at a level of 3.3V), the network transformer will not affect the devices of each other.
In another embodiment of the present invention, as shown in fig. 4, the data transmission circuit 121 may further include: a photoelectric conversion circuit 1213; the data transmission interface includes, for example, at least one optical port 1222 (also called a fiber optic interface).
The photoelectric conversion circuit 1213 is connected to the programmable logic device 1111 and the microprocessor 1112; the at least one optical port 1222 is connected to the photoelectric conversion circuit 1213.
The photoelectric conversion circuit 1213 receives data transmitted from the programmable logic device 1111 of the main processing circuit 111 and the microprocessor 1112, and converts the data into data that can be recognized by the photoelectric conversion circuit 1213 and data that can be output from the optical port 1222. For example, after the photoelectric conversion circuit 1213 converts the data sent by the microprocessor 1112, the photoelectric conversion circuit 1213 recognizes that 6 optical ports 1222 are required for output, and then controls 6 optical ports to output.
The optical port 1222 outputs video data or picture data. For example, a user needs 5 optical ports to output, then the main processing circuit 111 sets and generates corresponding data transmission interface configuration data according to the user's requirement, then the main processing circuit 111 transmits the data transmission interface configuration data to the photoelectric conversion circuit 1213, then the photoelectric conversion circuit 1213 converts and identifies the data transmission interface configuration data, and finally the photoelectric conversion circuit 1213 controls 5 optical ports 1222 to output according to the identified data.
In order to more clearly understand the display control apparatus 10 of the present embodiment, the operation thereof will be exemplified below with reference to fig. 1 to 7.
In this embodiment, the data interface board 12 having the structure of the signal conversion chip 1211 and the network port 1221 is mainly taken as an example, the number of the network ports (such as GigaETH shown in fig. 5) required is taken as 10, where the network ports are gigabit network ports, and the signal conversion chip 1211 is taken as an example of a signal conversion chip with a model 88E 1680.
As shown in fig. 1-7, firstly, the number of the required network ports is 10 by user setting, since the number of the network ports of the 88E1680 chip is 8, that is, two 88E1680 chips are required to be arranged in the data interface board 12, and then the power of the 10 network ports is balanced by internal control of the data interface board 12, so that one 88E1680 chip controls 6 network ports 1221 and the other 88E1680 chip controls 4 network ports 1221 to output, wherein the two 88E1680 chips share one reset signal. Each portal 1221 is then connected to a network transformer 1212 (shown as SG48001 in fig. 5). After the data interface board 12 is set, the data interface board 12 is detachably connected to the main processing circuit board 11 through the cooperation of the first connector 112 and the second connector 123, wherein a network transformer 1212 (shown as SG48001 in fig. 5) is further disposed on the data conversion circuit 121, and mainly eliminates interference of an external signal to the 88E1680 chip 1211 and the network port 1221.
The main processing circuit board 11 is provided with a main processing circuit 111, and the main processing circuit 111 includes a programmable logic device 1111 (FPGA shown in fig. 5) and a microprocessor 1112 (MCU shown in fig. 5). Then, Data transmission interface configuration Data of 10 network ports is set on the microprocessor 1112, and then the Data transmission interface configuration Data is sent to the two 88E1680 chips through a configuration signal transmission channel (such as MDC/MDIO (english full name: Management Data Clock/Management Data Input/Output) shown in fig. 5), and then the two 88E1680 chips respectively control the 10 network ports 1221 to Output according to the Data transmission interface configuration Data. The microprocessor 1112 is further connected to the two 88E1680 chips through a Reset signal transmission channel (RST (full name: Reset) shown in fig. 5), that is, the two 88E1680 chips share a Reset signal.
After the data Interface board 12 configures data through a data transmission Interface sent by the microprocessor 112 in the main processing circuit board 11 to complete configuration of output of the port 1221 in the data Interface board 12, the programmable logic device 1111 transmits video data to 10 ports expanded by the 88E1680 chip through a Serdes Interface (also called a high-speed transmission Interface) by using a QSGMII (full english name: Quad Serial bus Media Independent Interface) transmission protocol, and then outputs the video data to other devices through the 10 ports for display, for example, outputs the video data to a display screen for display. The Serdes Interface may also use an SGMII (generic name: Serial Media Independent Interface) transmission protocol or an XGMII (generic name: 10Gigabit Media Independent Interface) transmission protocol to transmit video data, which is not limited herein.
In summary, in the prior art, in the modules of the programmable logic device, the PHY chip and the network port, the number of the network ports with loads is determined, and when the number of the network ports with loads is more, the module functions and the network ports need to be redesigned, so that the design cost is increased, and the number of the network ports with loads cannot be flexibly changed. According to the data transmission interface card, the data interface card part is independent, when the carrying capacity of the data transmission interface is required to be changed, the number of the data transmission interfaces corresponding to the carrying capacity of the data transmission interface in the data interface card is only required to be detachably connected with the main processing circuit card, so that the purpose of flexibly changing the carrying capacity of the data transmission interface is achieved, and the design cost is reduced.
[ second embodiment ]
Fig. 8 is a schematic structural diagram of a display system 20 according to an embodiment of the present disclosure. As shown in fig. 6, the display system 20 includes: a display control device 10 and a display screen 21. The display screen 21 is connected to the display control apparatus 10.
The display control apparatus 10 may adopt the display control apparatus 10 described in the foregoing first embodiment, and the data transmission interface 122 of the data interface board 12 included in the display control apparatus 10 is connected to the display screen 21, so that the display screen 21 receives the video data output by the display control apparatus 10 to realize video display.
It is worth to say that the display screen 21 of this embodiment can be an LED display screen, and can also be an OLED display screen, and the LED display screen here can include at least one LED lamp panel or LED module, for example, the at least one LED lamp panel or LED module includes at least one LED lamp bead. Of course, the type of the display screen may also be determined according to actual needs, and is not limited herein.
In addition, it is understood that the foregoing embodiments are merely exemplary illustrations of the present application, and technical solutions of the embodiments can be arbitrarily combined and used without conflict, contradiction and conflict with technical features of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and/or method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units/modules is only one logical division, and there may be other divisions in actual implementation, for example, multiple units or modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units/modules described as separate parts may or may not be physically separate, and parts displayed as units/modules may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units/modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, functional units/modules in the embodiments of the present application may be integrated into one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated into one unit/module. The integrated units/modules may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units/modules.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. A display control apparatus characterized by comprising:
the main processing circuit board card is provided with a main processing circuit;
the data interface board card is detachably connected with the main processing circuit board card;
wherein, the data interface integrated circuit board includes:
the data conversion circuit is connected with the main processing circuit; and
and the data transmission interface is connected with the data conversion circuit.
2. The display control apparatus according to claim 1, wherein the data conversion circuit comprises:
and the signal conversion chip is connected with the main processing circuit.
3. The display control device according to claim 2, wherein the data transmission interface comprises at least one network port, and the at least one network port is connected with the signal conversion chip.
4. The display control apparatus according to claim 3, wherein the data conversion circuit further comprises: and the network transformer is connected between the signal conversion chip and the network port.
5. The display control apparatus according to claim 1, wherein the data conversion circuit comprises:
and the photoelectric conversion circuit is connected with the main processing circuit.
6. The device according to claim 5, wherein the data transmission interface comprises at least one optical port, and the at least one optical port is connected to the photoelectric conversion circuit.
7. The display control device of claim 1, wherein the main processing circuit comprises a microprocessor connected to the data conversion circuit; the microprocessor is provided with a configuration signal transmission channel and a reset signal transmission channel, and is connected with the data conversion circuit through the configuration signal transmission channel and the reset signal transmission channel.
8. The display control device according to claim 1, wherein the main processing circuit board is further provided with a first connector, and the first connector connects the data interface board and the main processing circuit.
9. The display control device of claim 8, wherein the data interface board further comprises: and a second connector connecting the data conversion circuit and the first connector.
10. A display system, comprising:
a display screen; and
the display control apparatus according to any one of claims 1 to 9;
the display control equipment is connected with the display screen through the data transmission interface of the data interface board card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021704535.4U CN213025335U (en) | 2020-08-14 | 2020-08-14 | Display control apparatus and display system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021704535.4U CN213025335U (en) | 2020-08-14 | 2020-08-14 | Display control apparatus and display system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213025335U true CN213025335U (en) | 2021-04-20 |
Family
ID=75465160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021704535.4U Active CN213025335U (en) | 2020-08-14 | 2020-08-14 | Display control apparatus and display system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213025335U (en) |
-
2020
- 2020-08-14 CN CN202021704535.4U patent/CN213025335U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1684446A2 (en) | A method and apparatus for testing optical network equipment | |
| CN103905281A (en) | FC-AE-1553 bus node card capable of interchangeably achieving functions of network controller and network terminal | |
| CN105141877A (en) | Programmable device-based signal conversion equipment | |
| CN211019067U (en) | Data exchange device, display control system, and display system | |
| CN215868585U (en) | Display screen control board card and display screen control system | |
| CN107908584B (en) | Multi-path RS-485 communication network | |
| CN104660989A (en) | Optical fiber-to-full configuration type Camera link real-time image optical transceiver based on FPGA (Field Programmable Gate Array) | |
| CN213025335U (en) | Display control apparatus and display system | |
| CN204948223U (en) | A kind of chromacoder based on programming device | |
| CN114442514A (en) | USB3.0/3.1 control system based on FPGA | |
| CN109147649B (en) | Display screen control card | |
| CN207503207U (en) | For the integrated test system of multiplex roles | |
| CN111277726A (en) | Video processing apparatus | |
| CN211236355U (en) | Photoelectric conversion apparatus, display control system, and display system | |
| CN214042270U (en) | KVM switch based on Type-C port | |
| CN211239967U (en) | Display controller, display control system and LED display system | |
| CN214042097U (en) | PLC serial port communication extension module capable of customizing protocol | |
| CN211016456U (en) | Display control system and L ED display system | |
| CN103716258A (en) | High-density line card, switching device, cluster system and electric signal type configuration method | |
| CN107070547A (en) | A kind of CPCI type gigabit Ethernet devices with failure monitoring ability | |
| CN213586010U (en) | Video output card and card insertion type video splicing processing equipment | |
| CN107564492B (en) | Adaptive cascade graphic signal generation system | |
| CN207164746U (en) | A kind of USB Type C adapters for realizing USB device detection | |
| CN111063286A (en) | Display control system and display unit board | |
| CN212660174U (en) | Network card and network equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |