CN220964923U - High-speed multi-protocol communication board card - Google Patents

Abstract

The utility model discloses a high-speed multi-protocol communication board card, which comprises a hardware module and a software module, wherein the hardware module comprises a host interface for supporting an x8 or x4 or x1PCIE bus, a high-performance Kintex-7 series FPGA of 2 Xilinx on board and a 2GB DDR3S DRAM cache, and Flash is externally expanded for storing logic. The external interface provides 2 SNAP12 interfaces, and can be connected with the optical module and the optical fiber cable for communication. Through the structure, the problems of low transmission rate, low signal quality, small number of communication channels, complicated communication rate and protocol modification, low bandwidth and the like of the traditional communication equipment are solved. When the discrete amount data is input, the upper computer can acquire the discrete amount data through software. When the discrete quantity data needs to be output, the upper computer can control the discrete quantity output data through software.

Description

High-speed multi-protocol communication board card

Technical Field

The utility model relates to the technical field of digital communication, in particular to a high-speed multi-protocol communication board card.

Background

With the development of digital communication technology, the bandwidth requirement of various data transmission schemes is rapidly increased, and the conventional data transmission mode can not meet the requirement of the technical scheme, so that high-speed serial data is widely used in the background. The equipment in the current market has the problems of low transmission rate, low signal quality, small number of communication channels, single supported communication rate and protocol, unadjustability and the like.

Disclosure of utility model

The utility model provides a high-speed multi-protocol communication board card which can support one of two communication protocols of SRIO and Aurora, wherein Rapid IO protocol supports nwrite, swrite, nwrite-r, nread, doorbell and maintenance message transmission.

In order to achieve the above purpose, a high-speed multi-protocol communication board card is provided, which comprises a hardware module and a software module, wherein the hardware module comprises a host interface for supporting an x8 or x4 or x1 PCIE bus, a high-performance Kintex-7 series FPGA of 2 Xilinx on board and a 2GB DDR3 SDRAM cache are provided, and Flash is used for storing logic. The external interface provides 2 SNAP12 interfaces, and can be connected with the optical module and the optical fiber cable for communication. In addition, a 24-way trigger input/output discrete quantity interface is also provided; the software module is an FPGA, and the FPGA comprises a data processing module, a REGAXI module and a RAM module.

According to the high-speed multi-protocol communication board card, the data processing module is connected with the REG AXI module, the RAM module and the IP (Aurora IP or SRIO according to different protocols), and the function of the module is to receive control information transmitted from the REG AXI module, put the control information into a corresponding channel register, finish sending or receiving information through the RAM, transmit control signals, and transmit different control signals to the IP according to different optical fiber interface protocols to control the working state of the IP.

According to the high-speed multi-protocol communication board card, the functions of the control signals include: writing transmission data, transmitting the transmission data, checking the transmission state, acquiring the receiving state, acquiring the storage address of the receiving data, reading the receiving data and setting the working state.

According to the high-speed multi-protocol communication board card, the RAM interface module is connected with the REG AXI bus and the RAM of the high-speed serial bus. The function of this module is to transfer the channel RAM information and AXI bus information.

The utility model has the beneficial effects that:

1. The fiber optic interface is capable of supporting a variety of communication protocols: one of two communication protocols of SRIO and Aurora can be supported;

2. the Rapid IO protocol supports nwrite, swrite, nwrite-r, nread, doorbell and maintenance message transmission.

3. The Aurora protocol supports 64b66b or 8b10b coding, streaming or frame modes, unidirectional or bidirectional modes, etc.

4. Can support 6 typical high-speed communication rates in the range of 1.25Gbps to 10 Gbps:

5. the number of channels is large: the fiber interface can be configured into 6 x4 or 12 x2 or 24 x1 working modes;

6. up to 24 trigger input/output discrete magnitude interfaces can be provided, wherein 20 paths are differential signal interfaces and 4 paths are single-end signal interfaces.

Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.

Drawings

The utility model is further described below with reference to the drawings and examples;

FIG. 1 is a schematic diagram of a hardware system of a high-speed multi-protocol communication board card according to the present utility model;

FIG. 2 is a block diagram of the internal logic of an FPGA of a high-speed multi-protocol communication board according to the present utility model;

FIG. 3 is a block diagram of a REGAXI module of a high-speed multi-protocol communications board according to the present utility model;

fig. 4 is a schematic diagram of a RAM interface module of a high-speed multi-protocol communication board according to the present utility model.

Wherein,

The model of a device used for transmitting the differential signals is MAX3485ESA, and the device is used for transmitting differential signal data, and the transmission direction can be controlled through FPGA control;

The Relay is a Relay, and the model is AQY282SX;

the TTL is used for transmitting TTL signals, the model of the device is SN74LVC2T45DCU, and the transmission direction of the signals can be controlled by the FPGA;

The high-speed serial signal is connected with the front panel through an optical fiber interface, and a user can use the optical module to connect with an optical fiber cable to communicate with the outside.

Detailed Description

Reference will now be made in detail to the present embodiments of the present utility model, examples of which are illustrated in the accompanying drawings, wherein the accompanying drawings are used to supplement the description of the written description so that one can intuitively and intuitively understand each technical feature and overall technical scheme of the present utility model, but not to limit the scope of the present utility model.

Examples:

referring to fig. 1-4, the high-speed multi-protocol communication board card of the embodiment of the utility model comprises a hardware module and a software module, wherein the hardware module comprises a host interface for supporting an x8 or x4 or x1 PCIE bus, a high-performance Kintex-7 series FPGA of 2-block Xilinx and a 2gb DDR3 SDRAM cache are carried on the board, and Flash is externally expanded for storing logic. The external interface provides 2 SNAP12 interfaces, and can be connected with the optical module and the optical fiber cable for communication. In addition, a 24-way trigger input/output discrete quantity interface is also provided; the software module is an FPGA, the FPGA comprises a data processing module, a REGAXI module and a RAM module, the scheme focuses on a high-speed communication part, the discrete quantity function is only an additional function, two SNAP12 interfaces are provided on the board card, two optical modules (only one of the two optical modules is inserted in the figure) can be inserted, 12 channels in total can be configured on each SNAP12 interface, each channel is provided with a transmitting end and a receiving end, and the transmitting ends and the receiving ends of the channels can be connected with 24-core optical fiber cables through the optical modules. The 12 channels are grouped into groups of 4 each, each group being configurable to a x1, x2 or x4 mode of operation.

The data processing module is connected with the REG AXI module, the RAM module and the IP (Aurora IP or SRIO according to different protocols), the function of the module is to receive the control information transmitted from the REG AXI module and put the control information into a corresponding channel register, send or receive the information through the RAM and transmit control signals, and transmit different control signals to the IP according to different fiber interface protocols to control the working state of the IP, the IP can process and receive and send the signals according to the configuration of a user, the REG AXI (SLAVE INTERFACE) module can transfer out an 8-path Wishbone bus (master) interface, and the information transmission and the function configuration of an upper computer to the outside are realized inside the FPGA. And transmitting signals in the FPGA through an AXI bus, transmitting data with the upper computer through a PCIE bus, realizing mode control and external information transmission of the upper computer in each FPGA, communicating the FPGA and the upper computer through the PCIE bus, mapping PCIE bus signals into AXI bus signals in the FPGA, dividing the signals into REG AXI and MEM AXI according to addresses, controlling the working mode of the high-speed serial bus, and monitoring the working state in the FPGA.

The functions of the control signal include: writing transmission data, transmitting the transmission data, checking the transmission state, acquiring the receiving state, acquiring the storage address of the receiving data, reading the receiving data and setting the working state, and the RAM interface module is connected with the REG AXI bus and the RAM of the high-speed serial bus. The function of this module is to transfer the channel RAM information and AXI bus information.

Working principle: when the software is used, the data transmission and receiving can be controlled through the PCIE bus by the upper computer software, and the work of each module is controlled. When transmitting data, the data to be transmitted is written into the transmitting RAM of the transmitting channel through the RAM AXI, then the transmitting control signal is written into the transmitting channel through the REG AXI, the data processing module can take out the transmitting data from the transmitting RAM according to the control information, and the data is transmitted to the external interface through the IP (Aurora or SRIO). When receiving, the data transmitted from the external interface is processed by IP and then stored in the receiving RAM, the upper computer software reads the data in the channel register through REG AXI to judge whether the received data exists, if yes, the upper computer software can read the data from the receiving RAM through REM interface module.

The embodiments of the present utility model have been described in detail with reference to the accompanying drawings, but the present utility model is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present utility model.

Claims (4)

1. The high-speed multi-protocol communication board card is characterized by comprising a hardware module and a software module, wherein the hardware module comprises a host interface for supporting an x8 or x4 or x1 PCIE bus, a high-performance Kintex-7 series FPGA of 2-block Xilinx and a 2GB DDR3 SDRAM cache are carried on the board, flash is used for storing logic, 2 SNAP12 interfaces are provided for an external interface, the optical module can be connected with an optical fiber cable for communication, and in addition, 24 paths of trigger input/output discrete quantity interfaces are also provided; the software module is an FPGA, and the FPGA comprises a data processing module, a REGAXI module and a RAM module.

2. The high-speed multi-protocol communication board card according to claim 1, wherein the data processing module is connected with the REG AXI module, the RAM module and the IP module, and has the functions of receiving the control information transmitted from the REG AXI module, placing the control information into a corresponding channel register, completing the transmission or reception of the information through the RAM, transmitting the control signals, transmitting different control signals to the IP according to different optical fiber interface protocols, and controlling the working state of the IP.

3. The high-speed multi-protocol communication board of claim 2, wherein the control signal functions include: writing transmission data, transmitting the transmission data, checking the transmission state, acquiring the receiving state, acquiring the storage address of the receiving data, reading the receiving data and setting the working state.

4. The high-speed multi-protocol communication board of claim 1, wherein the RAM interface module is connected to the REG AXI bus and the RAM of the high-speed serial bus, and the function of the module is to transfer the information of the channel RAM and the AXI bus information.