CN215679093U

CN215679093U - CAN interface motion controller based on ARM and FPGA

Info

Publication number: CN215679093U
Application number: CN202121879447.2U
Authority: CN
Inventors: 宋俊; 匡顺兰; 闫永鑫; 唐自祥; 李娟�
Original assignee: Chengdu Enfit Technology Co ltd
Current assignee: Chengdu Enfit Technology Co ltd
Priority date: 2021-08-11
Filing date: 2021-08-11
Publication date: 2022-01-28
Anticipated expiration: 2031-08-11

Abstract

The utility model discloses a CAN interface motion controller based on ARM and FPGA, which comprises a CAN interface motion controller based on ARM and FPGA, and is characterized by comprising an FPGA controller, a CAN controller and a CAN isolation transceiver, wherein the FPGA controller is connected to a USB interface of an upper computer through a USB data line and is connected to the CAN isolation transceiver through the CAN controller, the FPGA controller and the CAN controller are also provided with a storage SDRAM for data buffering and command buffering, and the CAN controller and the FPGA controller are respectively provided with a memory SDRAM for data buffering and command buffering, wherein: the FPGA controller is used for receiving the instruction of the upper computer to realize the control of the CAN controller and realize the data interaction between the upper computer and the CAN bus. The motion controller fully supports CANV2.0B specifications, has a maximum communication rate of 2Mb/s, and is capable of transmitting and receiving standard and extended data frames and remote frames in a variety of frame formats.

Description

CAN interface motion controller based on ARM and FPGA

Technical Field

The utility model relates to the field of data communication, in particular to a CAN interface motion controller based on ARM and FPGA.

Background

The CAN, which is called a Controller Area Network (Controller Area Network) entirely, is a multi-host asynchronous serial bus, and is one of the most widely used field buses internationally. Has now become an international standard adopted as the ISO11898 standard for high speed applications and as the ISO11519 standard for low speed applications. Among the field buses, it is the only field bus approved by the international organization for standardization. The CAN bus has the advantages of being excellent and popular with people. These characteristics include: the method has the advantages of low cost, extremely high bus utilization rate, data transmission distance of 10km, data transmission rate of 1Mbit/s, message selection according to the ID of the message, reliable error processing and detection mechanism, automatic retransmission of damaged information, automatic bus exit of a node under serious error condition, no address contained in the message, and indication of functional information and priority by using a marker. Because of its excellent error handling mechanism and reliable data transfer performance, the CAN bus has been widely used in the fields of the automotive industry, the aviation industry, medical instruments, industrial control, safety protection, and the like. In the prior art, CAN data exchange is realized through singlechip + SJA1000, carries out data analysis through the IO mouth simulation CAN controller of singlechip, and the host computer still needs the USB to change the serial ports after CAN communicate with the CAN interface after the singlechip carries out data conversion, and not only communication rate is low and very inconvenient when in actual application.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a CAN interface motion controller based on ARM and FPGA, which uses the FPGA capable of being programmed repeatedly to read and send data to realize the communication with an upper computer, and improves the communication speed by arranging a memory for data buffering and command buffering SDRAM.

The technical scheme of the utility model is as follows: CAN interface motion control ware based on ARM and FPGA, including FPGA controller, CAN controller and CAN isolation transceiver, the FPGA controller is connected to host computer USB interface through the USB data line, is connected to CAN isolation transceiver through the CAN controller, the FPGA controller still is connected with memory SDRAM for data buffering and command buffering.

The FPGA controller is used for receiving the instruction of the upper computer to realize the control of the CAN controller and realize the data interaction between the upper computer and the CAN bus.

The upper computer is interactively connected with the CAN controller through the FPGA controller; the CAN isolation transceiver is electrically connected with the CAN controller and the bus.

The motion controller also includes a power module for supplying power to the modules in the motion controller.

The CAN isolation transceiver is used for realizing the interchange of the logic level of the CAN controller and the differential level on the CAN bus.

The FPGA controller is responsible for realizing the control of the CAN controller: initializing CAN controller parameters when a node is started; when the CAN controller is interrupted, sending an interruption abnormal signal of the CAN controller to an upper computer; performing FPGA register configuration operation and CAN controller register configuration operation, and writing CMD sent by an upper computer into an FPGA sending command fifo;

when receiving a sending instruction from an upper computer, writing data into a SDRAM sending cache region;

when receiving the receiving instruction from the upper computer, the read memory SDRAM receives the data of the cache region.

USB interface module is connected with the host computer interactive mode, includes: transmitting the instruction and the corresponding register address sent by the upper computer to a register of the FPGA main control module, and storing data to a SDRAM sending buffer area; and transmitting the data of the SDRAM receiving buffer area of the memory to an ARM upper computer through a USB data line.

The FPGA main control module is used for analyzing the received instruction, judging the latched data and the length of the instruction by the FPGA main control module, obtaining a reset instruction, a read instruction, a write instruction, an RX buffer read instruction, a TX buffer loading instruction and a bit modification instruction, and sending the instructions to the CAN controller through the first SPI interface module; receiving CAN data through a first SPI interface module, and storing the CAN data in a SDRAM receiving buffer area; and storing the upper computer data and the commands to a SDRAM sending buffer area.

The first SPI interface module is used for serially outputting the instruction, the address of a register inside the CAN control device and the data of the SDRAM sending buffer area to a cache register in the CAN controller and storing the data received by the CAN controller into the SDRAM receiving buffer area.

The CAN controller is used for realizing a CAN bus protocol, sending and receiving data frames, including standard data frames, extended data frames and the like, and comprises a second SPI interface module, a CAN protocol module and a CAN control logic module.

The CAN protocol module is mainly responsible for data transmission with the CAN bus; the CAN control logic module is used for setting a chip and an operation mode thereof; and the second SPI interface module is mainly responsible for data transmission with the FPGA controller.

The CAN protocol module comprises: the CAN protocol machine is used for realizing data transmission with a CAN bus.

The CAN controllers connected with one end of the FPGA controller are multiple, and each CAN controller is connected with one CAN isolation transceiver.

The FPGA controller power supply is provided by a chip ADP 5024.

The power supply module comprises 9-37 VDCDC power supply circuits and is used for supporting USB power supply.

The motion controller exists on the bus in a node form, and the whole node is organically combined with the CAN control, the memory SCRAM and the CAN isolation transceiver by using an FPGA controller core and is connected with the upper computer through USB communication. The FPGA controller is provided with the USB interface module, so that the design of a peripheral circuit of the USB controller is omitted, the anti-interference capability of the CAN bus is further improved, and the nodes are electrically isolated and independent.

The utility model has the following beneficial effects:

the SPI interface is adopted, and the device has the characteristics of small volume, low power consumption, perfect function, convenience in use and the like. In order to realize the CAN interface motion controller based on the interface chip, an ARM + FPGA framework is adopted, SPI interface logic and CAN controller instruction conversion logic are realized in the FPGA to complete different SPI instructions, and an upper computer instruction is received in the ARM and the CAN controller is controlled. The communication unit has reasonable design and stable operation, and meets the actual requirement.

The motion controller completely supports CANV2.0B technical specification, the communication speed is at most 2Mb/s, and can send and receive standard and extended data frames and remote frames and other frame formats, and the communication speed is improved by setting a memory for data buffering and command buffering SDRAM.

Drawings

FIG. 1 is a schematic view of the overall structure of the present invention;

FIG. 2 is a schematic diagram of the operation of the motion controller of the present invention;

FIG. 3 is a schematic diagram of a CAN controller according to the present invention;

Detailed Description

The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited to these examples.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "longitudinal", "lateral", "horizontal", "inner", "outer", "front", "rear", "top", "bottom", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, or the orientations or positional relationships that are conventionally placed when the products of the present invention are used, and are used only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element that is referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "open," "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Examples

CAN interface motion control ware based on ARM and FPGA, including FPGA controller, CAN isolation transceiver, memory SDRAM and power module, wherein FPGA functional module divides into: USB interface module, master control module and first SPI interface module, the CAN controller includes second SPI interface module, CAN protocol module and CAN control logic module.

And an ARM is used as an upper computer, a user control panel is designed, and data interaction and baud rate setting and the like among different CAN nodes are carried out. Simultaneously, adopt ARM + FPGA framework to carry out CAN interface motion control unit design, the CAN controller is connected with the FPGA controller through second SPI interface module to carry out SPI interface logic and instruction conversion logic design inside the FPGA controller, first SPI interface module promptly receives host computer command and the control to the CAN controller in FPGA.

The upper computer is used for controlling the motion controller in real time and configuring parameters such as data frames, extended frame formats, baud rates and the like. The communication configuration comprises baud rate setting, data bit number selection, frame format selection, ID setting, verification shielding register setting and verification filtering register setting; the sending data area can be provided with a channel number, a sending frame type, a sending frame format, a frame ID, a data length, data bytes (0-8 bytes), and the sending form of the message is set, wherein special messages such as specific messages, broadcast messages, remote messages and the like can be sent; the receiving data area is used for receiving messages sent by other CAN nodes on the CAN bus, and the receiving data area needs to be emptied after one-time receiving is completed. Meanwhile, the initialization setting of the CAN controller is needed before the CAN communication configuration setting. Module initialization is to initialize all communication configurations, and the module enters an initialization state.

The power module is used for supplying power to each module in the motion controller.

when receiving a sending instruction from an upper computer, writing data into a sending cache region of a SDRAM (synchronous dynamic random access memory);

when receiving the receiving instruction from the upper computer, the data of the receiving cache region of the SDRAM is read.

The FPGA main control module is used for analyzing the received instruction, judging the latched data and the length of the instruction by the FPGA main control module, obtaining a reset instruction, a read instruction, a write instruction, an RX buffer read instruction, a TX buffer loading instruction and a bit modification instruction, and sending the instructions to the CAN controller through the first SPI interface module; receiving CAN data through a first SPI interface module, and storing the CAN data in a SDRAM receiving buffer area; and storing the upper computer data to a SDRAM sending buffer area.

The CAN controller is used for realizing a CAN bus protocol, sending and receiving standard data frames and extended data frames and has the functions of receiving, filtering and information management. The CAN protocol module is mainly responsible for data transmission with the CAN bus; the CAN control logic module is used for setting a chip and an operation mode thereof; and the second SPI interface module is mainly responsible for data transmission with the FPGA controller.

Wherein, CAN agreement module: the module is mainly used for receiving and sending CAN bus messages. When a message is sent, the message is loaded into a message buffer and a control register, an upper computer sets the contents of a data frame format bit, a data length bit and the like in the control register through an SPI (serial peripheral interface) to complete the CAN data frame sending setting, and a sending enabling pin is used for starting the message sending. When a message is received, the upper computer reads communication state information and message filtering information in a CAN protocol module register group through the SPI interface, and determines whether the CAN bus has the message or not and whether the message is sent into a receiving buffer or not.

CAN control logic module: the CAN controller is further controlled to set and operate through connection with the buffer, the filter group and a bit timing generator, a control register and an interrupt register which are related to the buffer and the filter group so as to transmit information and control.

The second SPI interface module: the FPGA controller realizes data transmission with the CAN controller through an SPI interface, and realizes the reading/writing of the chip register by using a standard SPI reading/writing instruction and an SPI data communication protocol of the controller. All commands and data of CAN communication are transmitted through the SPI interface, and the commands comprise a reset command, a read command, a write command, a read RX buffer command, a load TX buffer command and a bit modification command of the chip. The functions of initialization, data transmission, data reception and the like of the CAN controller are realized through the instructions.

The CAN controller that FPGA controller one end is connected is a plurality of, and every CAN controller all is connected with a CAN isolation transceiver, and every CAN controller forms a passageway rather than CAN isolation transceiver, FPGA controller that are connected respectively.

Multiple channels transmit data in parallel, all channels share one 8MByte transmit data buffer, one 4KByte command buffer. Each channel has an independent 256KByte receive data buffer capable of caching 26000 multi-frame CAN data frames.

The FPGA controller power supply is provided by a chip ADP 5024.

The CAN controller adopts MCP2515_ I/ST chip.

The CAN isolation transceiver adopts an ISO1050DUB chip.

The foregoing is only a preferred embodiment of the present invention, and the present invention is not limited thereto in any way, and any simple modification, equivalent replacement and improvement made to the above embodiment within the spirit and principle of the present invention still fall within the protection scope of the present invention.

Claims

1. CAN interface motion control ware based on ARM and FPGA, keep apart the transceiver including CAN controller and CAN, its characterized in that still includes the FPGA controller, the FPGA controller is connected to host computer USB interface, keeps apart the transceiver through the CAN controller through USB data line connection, the FPGA controller still has external memory SDRAM for data buffering and command buffering, wherein:

2. The ARM and FPGA-based CAN interface motion controller of claim 1, wherein said FPGA controller comprises: the system comprises a USB interface module, a main control module and a first SPI interface module, wherein the USB interface module is used for being interactively connected with an upper computer; the FPGA main control module is used for analyzing the received instruction and realizing the control of the CAN controller through the first SPI interface module; storing the CAN data to a SDRAM receiving buffer area; storing the upper computer data and the command to a SDRAM sending buffer area; and the first SPI interface module carries out SPI interface logic and instruction conversion logic inside the FPGA controller so as to realize data transmission with the CAN controller.

3. The ARM and FPGA based CAN interface motion controller of claim 1, wherein the CAN controller is configured to implement a CAN bus protocol, send and receive data frames, and comprises a second SPI interface module, a CAN protocol module, and a CAN control logic module.

4. The ARM and FPGA based CAN interface motion controller of claim 3, wherein the CAN protocol module is mainly responsible for data transmission with a CAN bus; the CAN control logic module is used for setting a CAN controller and an operation mode thereof; and the second SPI interface module is mainly responsible for data transmission with the FPGA controller.

5. The ARM and FPGA-based CAN interface motion controller of claim 1 further comprising a power module for providing power to portions of the motion controller.

6. The ARM and FPGA based CAN interface motion controller of claim 4, wherein the CAN protocol module comprises: the CAN protocol machine is used for realizing data transmission with a CAN bus.

7. The ARM and FPGA based CAN interface motion controller of claim 1, wherein a plurality of CAN controllers are connected to one end of the FPGA controller, and each CAN controller is connected to one CAN isolation transceiver.

8. The ARM and FPGA-based CAN interface motion controller of claim 1, wherein said FPGA controller power is provided by a chip ADP 5024.

9. The ARM and FPGA based CAN interface motion controller of claim 1, wherein the CAN controller employs MCP2515_ I/ST chip.

10. The ARM and FPGA based CAN interface motion controller of claim 5, wherein the power module comprises a 9 ~ 37VDCDC power supply circuit for supporting USB power supply.