CN218585983U - 半导体封装装置 - Google Patents

半导体封装装置 Download PDF

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CN218585983U
CN218585983U CN202221973861.4U CN202221973861U CN218585983U CN 218585983 U CN218585983 U CN 218585983U CN 202221973861 U CN202221973861 U CN 202221973861U CN 218585983 U CN218585983 U CN 218585983U
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conductive pad
electrical connection
semiconductor package
package device
oxide layer
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林而儒
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to US18/206,579 priority patent/US20240038698A1/en
Priority to EP23177602.2A priority patent/EP4312254A1/en
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Abstract

本申请涉及半导体封装装置。该半导体封装装置包括：基板；导电垫，位于基板上并且具有各向异性晶体结构；电连接线，与导电垫电接触。该半导体封装装置利用具有高度定向结构的各向异性晶体形成导电垫，能够提高导电垫的致密度，降低导电垫表面的氧化层厚度，有利于提高导电垫和电连接线的接合强度，以及提高导电垫和电连接线的接合品质。

Description

半导体封装装置
技术领域
本申请涉及半导体封装技术领域，具体涉及半导体封装装置。
背景技术
目前打线(Wire Bonding)制程中主要由芯片上的铝垫打线至基板上，芯片的铝垫与铜线的材料不同，因此铝垫会因不同金属间的电位差在有湿度的环境中出现电解腐蚀现象。此外，不同金属之间会形成金属间化合物(Intermetallic Compound，IMC)，消耗铝垫的材料，导致铝垫脆化，造成后续可靠度问题。此外，金属间化合物的形成会使铝垫中出现孔洞，造成铝垫的阻抗增大，影响结构的导电性。
若将铝垫改为与铜线相同的材料(即铜垫)，由于铜容易氧化，铜垫表面的氧化层会影响铜线与铜垫的接合，降低接合的品质。
若在铜垫表面电镀抗氧化层(例如镍层)避免铜氧化，其成本较高，并且还是会在铜垫与抗氧化层之间形成金属间化合物。
因此，有必要提出一种新的技术方案以解决上述至少一个技术问题。
实用新型内容
本申请提供了一种半导体封装装置，用于提高导电垫和电连接线的接合品质。
本申请提供的半导体封装装置包括：
基板；
导电垫，位于所述基板上并且具有各向异性晶体结构；
电连接线，与所述导电垫电接触。
在一些可选的实施方式中，所述各向异性晶体结构为高度定向结构。
在一些可选的实施方式中，所述高度定向结构的晶体方向为(1,1,1)方向。
在一些可选的实施方式中，所述各向异性晶体结构为纳米孪晶结构。
在一些可选的实施方式中，所述导电垫的表面具有氧化层，所述电连接线穿过所述氧化层。
在一些可选的实施方式中，所述电连接线与所述导电垫电连接。
在一些可选的实施方式中，所述氧化层接触所述电连接线的表面。
在一些可选的实施方式中，所述电连接线和所述导电垫的材料相同。
在一些可选的实施方式中，所述电连接线和所述导电垫的晶格结构不同。
在一些可选的实施方式中，所述电连接线与所述导电垫之间不存在金属间化合物。
在一些可选的实施方式中，所述电连接线具有球状端部，所述球状端部与所述导电垫直接接合。
本申请提供的半导体封装装置，利用具有高度定向结构的各向异性晶体形成导电垫，能够提高导电垫的致密度，降低导电垫表面的氧化层厚度，有利于提高导电垫和电连接线的接合强度，以及提高导电垫和电连接线的接合品质。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1是根据本申请实施例的半导体封装装置的示意图；
图2是根据本申请实施例的半导体封装装置的局部放大示意图；
图3-图7是根据本申请实施例的半导体封装装置的制造过程的示意图。
符号说明：
100、基板；200、导电垫；210、氧化层；211、第一氧化层；212、第二氧化层；300、电连接线；310、球状端部；400、种子层；500、过渡层；900、打线装置。
具体实施方式
下面结合附图和实施例对说明本申请的具体实施方式，通过本说明书记载的内容本领域技术人员可以轻易了解本申请所解决的技术问题以及所产生的技术效果。可以理解的是，此处所描述的具体实施例仅仅用于解释相关实用新型，而非对该实用新型的限定。另外，为了便于描述，附图中仅示出了与有关实用新型相关的部分。
需要说明的是，说明书附图中所绘示的结构、比例、大小等，仅用于配合说明书所记载的内容，以供本领域技术人员的了解与阅读，并非用以限定本申请可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本申请所能产生的功效及所能达成的目的下，均应仍落在本申请所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本申请可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本申请可实施的范畴。
还需要说明的是，本申请的实施例对应的纵向截面可以为对应前视图方向截面，横向截面可以为对应右视图方向截面，而水平截面可以为对应上视图方向截面。
应容易理解，本申请中的“在...上”、“在...之上”和“在...上面”的含义应该以最广义的方式解释，使得“在...上”不仅意味着“直接在某物上”，而且还意味着包括存在两者之间的中间部件或层的“在某物上”。
此外，为了便于描述，本申请中可能使用诸如“在...下面”、“在...之下”、“下部”、“在...之上”、“上部”等空间相对术语来描述一个元件或部件与附图中所示的另一元件或部件的关系。除了在图中描述的方位之外，空间相对术语还意图涵盖装置在使用或操作中的不同方位。设备可以以其他方式定向(旋转90°或以其他定向)，并且在本申请中使用的空间相对描述语可以被同样地相应地解释。
另外，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
图1是根据本申请实施例的半导体封装装置的示意图。如图1所示，该半导体封装装置包括基板100、导电垫200和电连接线300。导电垫200设置在基板 100的上表面。导电垫200的上表面具有氧化层210。电连接线300穿过氧化层 210并且与导电垫200电连接。其中，氧化层210接触电连接线300的表面。
在本实施例中，导电垫200的材料例如是铜。导电垫200具有各向异性晶体结构，并且其中的晶体高度定向。导电垫200中晶体的方向例如是(1,1,1)方向。
在一些实施方式中，导电垫200和电连接线300的材料可以相同，例如均为铜。由于导电垫200和电连接线300的材料相同，因此两者的接合处不存在金属间化合物，能够有效避免金属间化合物造成导电垫200脆化，或者导电垫200的表面出现空洞，保证导电垫200和电连接线300的接合强度。在一些实施方式中，导电垫200和电连接线300的晶格结构可以不同，具体来说，导电垫200的晶格结构可以是高度定向结构，电连接线300的晶格结构可以是非高度定向结构。
在一些实施方式中，导电垫200的晶体结构可以是纳米孪晶(nano twinned) 结构，由许许多多纳米尺度厚度的孪晶片层构成的材料。这里，孪晶是指两个晶体(或一个晶体的两部分)沿一个公共晶面(即特定取向关系)构成镜面对称的位向关系。
在一些实施方式中，电连接线300具有球状端部310，该球状端部310与导电垫200直接接合。
图2是根据本申请实施例的半导体封装装置中基板100和导电垫200的放大示意图。
如图2所示，基板100与导电垫200之间设置有种子层400和过渡层500。种子层400的材料例如是铜或者铜合金，过渡层500的材料例如是铜。
如图2所示，导电垫200包括的多个水平层即为多个孪晶片层，每个孪晶片层内进一步包括多组孪晶。
如图2所示，导电垫200的上表面具有氧化层210。氧化层210进一步包括第一氧化层211和第二氧化层212。其中，第一氧化层211的材料例如是氧化铜。
第二氧化层212的材料例如是一氧化二铜。
在本实施例中，利用具有高度定向结构的各向异性晶体形成导电垫200，能够提高导电垫200的致密度，降低导电垫200表面的氧化层210厚度，有利于提高导电垫200和电连接线300的接合强度，以及提高导电垫200和电连接线300 的接合品质。
在现有的铜-铝打线接合中，会出现导电垫凹坑(cratering)和导电垫溅射(splash)等问题，本实施例采用铜-铜接合，并且利用较薄的氧化层210起到保护作用，能够避免上述凹坑和溅射问题。
在本实施例中，能够将铜-铜界面中85％以上的面积形成接合区域，有利于提高接合强度。
不同金属之间容易出现电腐蚀现象。本实施例中采用同种金属接合，能够有效防止电腐蚀的发生。
本实施例中将铜作为导电材料，能够有效减小电传输路径中的电阻。此外，铜具有更小的电子迁移阻力(electron-migration-resistance)，因此铜形成的结构具有更高的寿命以及稳定性。
由于铜易氧化，因此现有的铜-铜接合需要在氮氧气氛中和较高的温度下进行，借助昂贵的设备实现。本实施例中的铜具有高度定向结构，对氧化的敏感程度降低，对反应环境的要求降低，能够将反应温度降低至100℃以下，无需借助高昂的设备实现。
图3-图7是根据本申请实施例的半导体封装装置的制造过程的示意图。如图 3-图7所示，该制造过程包括以下步骤：
第一步，如图3所示，利用打线装置900将电连接线300置于基板100上方，并且使球状端部310与导电垫200相对。
第二步，如图4所示，利用超声波和/或加热将第一氧化层211破坏，并且将球状端部310下压。
第三步，如图5所示，利用超声波和/或加热将第二氧化层212破坏，并继续将球状端部310下压。
第四步，如图6所示，将第二氧化层212破坏至导电垫200得以暴露的程度，并且使球状端部310与导电垫200直接接触(如图6中虚线区域所示)。
第五步，如图7所示，通过加热使球状端部310表面的颗粒生长，实现与导电垫200的接合。
由于该实施例中的导电垫200具有高度定向结构，其表面的氧化层210厚度更小，因此破坏保护层所需的温度更低，有利于降低接合温度，进而降低异质界面带来的热应力冲击。
尽管已参考本申请的特定实施例描述并说明本申请，但这些描述和说明并不限制本申请。所属领域的技术人员可清楚地理解，可进行各种改变，且可在实施例内替代等效元件而不脱离如由所附权利要求书限定的本申请的真实精神和范围。图示可能未必按比例绘制。归因于制造过程中的变量等等，本申请中的技术再现与实际设备之间可能存在区别。可存在未特定说明的本申请的其它实施例。应将说明书和图式视为说明性的，而非限制性的。可作出修改，以使特定情况、材料、物质组成、方法或过程适应于本申请的目标、精神以及范围。所有此些修改都落入在此所附权利要求书的范围内。虽然已参考按特定次序执行的特定操作描述本申请中所公开的方法，但应理解，可在不脱离本申请的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本申请中特别指示，否则操作的次序和分组并不限制本申请。

Claims (8)

1.一种半导体封装装置，其特征在于，包括：
基板；
导电垫，位于所述基板上并且具有各向异性晶体结构；
电连接线，与所述导电垫电接触；
所述各向异性晶体结构为高度定向结构；
所述导电垫的表面具有氧化层，所述电连接线穿过所述氧化层。
2.根据权利要求1所述的半导体封装装置，其特征在于，所述高度定向结构的晶体方向为(1,1,1)方向。
3.根据权利要求1所述的半导体封装装置，其特征在于，所述各向异性晶体结构为纳米孪晶结构。
4.根据权利要求1所述的半导体封装装置，其特征在于，所述电连接线与所述导电垫电连接。
5.根据权利要求1所述的半导体封装装置，其特征在于，所述氧化层接触所述电连接线的表面。
6.根据权利要求1所述的半导体封装装置，其特征在于，所述电连接线和所述导电垫的材料相同。
7.根据权利要求6所述的半导体封装装置，其特征在于，所述电连接线和所述导电垫的晶格结构不同。
8.根据权利要求1所述的半导体封装装置，其特征在于，所述电连接线具有球状端部，所述球状端部与所述导电垫直接接合。
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