CN218123402U - Bus bar for semiconductor device and chip packaging structure - Google Patents
Bus bar for semiconductor device and chip packaging structure Download PDFInfo
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- CN218123402U CN218123402U CN202222280984.6U CN202222280984U CN218123402U CN 218123402 U CN218123402 U CN 218123402U CN 202222280984 U CN202222280984 U CN 202222280984U CN 218123402 U CN218123402 U CN 218123402U
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Abstract
The utility model discloses a bus bar and chip packaging structure for a semiconductor device, wherein the bus bar comprises at least two first bonding pads and a second bonding pad; two adjacent first bonding pads are connected through an arched connecting part; the first bonding pad is provided with a first through hole, and a convex hull structure facing the welding surface of the first bonding pad is arranged on the peripheral side of the first through hole; the second pad is connected to the first pad located on the outermost side. The utility model provides a bus bar for semiconductor device of high reliability.
Description
Technical Field
The utility model relates to a semiconductor package technical field, in particular to a busbar, chip packaging structure for semiconductor device.
Background
In the packaging of a power electronic semiconductor with single-side heat dissipation, power loop connection between chips and power loop connection between the chips and a substrate are required to form a chip packaging structure.
In the prior art, the following three methods are mainly used for power loop connection: firstly, an aluminum bonding (wire binding) mode is adopted, but the mode is mainly connected with the silver-plated or aluminum-plated surface of the chip through high-frequency ultrasonic welding, the stress of a joint is concentrated, the bonding strength of the joint is easy to reduce along with temperature circulation, and the reliability is low; secondly, a DTS + TCB (Die Top system & click Cu Bonding) process is adopted, however, nano silver paste needs to be used for sintering, the price is high, and the material cost is high; and thirdly, a mode of an aluminum-clad copper bonding wire is adopted, but the preparation process of the aluminum-clad copper bonding wire used in the mode is complex, the price is also high, and the material cost is also high.
SUMMERY OF THE UTILITY MODEL
The main objective of the present invention is to provide a bus bar and a chip packaging structure for semiconductor device, which aims to provide a bus bar with high reliability.
To achieve the above object, the present invention provides a bus bar for a semiconductor device, including:
at least two first bonding pads, wherein two adjacent first bonding pads are connected through an arch connecting part; the first bonding pad is provided with a first through hole, and a convex hull structure facing the welding surface of the first bonding pad is arranged on the periphery of the first through hole;
and a second pad connected to the first pad located at the outermost side.
In an embodiment of the present invention, the first through hole is provided with a plurality of first through holes, and the plurality of first through holes are arranged at intervals along the first direction of the first bonding pad.
In an embodiment of the present invention, the first through hole is a waist-shaped hole, and the waist-shaped hole extends along the second direction of the first pad.
In an embodiment of the present invention, the length of the waist-shaped hole is L 1 The width of the first bonding pad is L 2 ，0.7L 2 <L 1 <L 2 。
In an embodiment of the present invention, an outer contour of the first bonding pad bonding surface is a rectangle, and a second through hole is further disposed at least one corner of the first bonding pad, and the second through hole is juxtaposed to the first through hole.
In an embodiment of the present invention, the second through hole is a semi-waist-shaped hole, an opening of the semi-waist-shaped hole faces an outer side of the first pad, and the semi-waist-shaped hole is disposed along the second direction of the first pad.
In an embodiment of the present invention, a convex hull structure facing the first pad bonding surface is disposed on the periphery of the second through hole.
In an embodiment of the invention, a sum of a length of one of the first through holes and a length of at least one of the second through holes is greater than a width of the first pad.
In an embodiment of the present invention, a length of the first pad in the first direction is greater than a length of the first pad in the second direction.
The utility model discloses an in one embodiment, the second pad is including the connecting portion of buckling and base plate weld part, the base plate weld part is passed through the connecting portion of buckling is connected with the outermost first pad.
The utility model also provides a chip packaging structure, include:
a substrate;
the at least two chips are arranged on the surface of the substrate in parallel at intervals;
the bus bar for a semiconductor device as described above, wherein the bus bar is located above the substrate, each of the first pads of the bus bar is soldered to one of the chips, and the second pad of the bus bar is soldered to the substrate.
The bus bar for the semiconductor device comprises a first bonding pad and a second bonding pad, two adjacent first bonding pads are connected through an arch connecting portion, the second bonding pad is connected with the first bonding pad located on the outermost side, and due to the fact that one first bonding pad is connected with one chip on the substrate, the bus bar achieves power loop connection between the chip and the chip on the substrate, the second bonding pad is welded with the substrate, and power loop connection between the chip and the substrate is achieved.
The first pad is provided with a first through hole, and the periphery of the first through hole is provided with a convex hull structure facing the welding surface of the first pad. When a bus bar is welded with a chip on a substrate, the first through hole is beneficial to reducing the tangential stress born by the solder between the chip and a first bonding pad during temperature circulation, the convex hull structure arranged on the peripheral side of the first through hole can avoid the stress concentration of the solder caused by sharp edges, and meanwhile, the convex hull structure on the peripheral side of the first through hole is used for ensuring the gap between the chip and the first bonding pad, so that the solder is uniformly dispersed during welding, the thickness of the solder between the chip and the first bonding pad is stably controlled, the temperature-shock cycle reliability life of the solder is greatly prolonged, and the reliability of a chip packaging structure is improved.
In addition, redundant solder can overflow through the first through hole when the chip is welded with the first bonding pad, so that the solder is in the largest and thinnest state after welding, the generation of heat is reduced, and the cycle life of the solder is prolonged; the first through hole is convenient for observing the state of the solder, and the welding yield is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a bus bar for a semiconductor device according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a chip package structure according to an embodiment of the present disclosure;
fig. 3 is a cross-sectional view of a chip package structure according to an embodiment of the disclosure;
fig. 4 is a cross-sectional view of another position of a chip package structure according to an embodiment of the disclosure.
The reference numbers illustrate:
the realization, the functional characteristics and the advantages of the utility model are further explained by combining the embodiment and referring to the attached drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, back, 8230; \8230;) are provided in the embodiments of the present invention, the directional indications are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the attached drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description relating to "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory to each other or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The embodiment of the present application provides a bus bar 30 and a chip packaging structure 100 for a semiconductor device, and the following description will be made on the specific structure of the bus bar 30 and the chip packaging structure 100 for a semiconductor device provided by the present application:
referring to fig. 1 to 4 in combination, a bus bar 30 for a semiconductor device according to an embodiment of the present disclosure includes at least two first pads 31 and a second pad 33; two adjacent first pads 31 are connected through a raised connecting part 32; the first land 31 is provided with a first through hole 311, and a convex hull structure 3111 facing the welding surface of the first land 31 is arranged on the peripheral side of the first through hole 311; the second pad 33 is connected to the first pad 31 located on the outermost side.
It can be understood that the bus bar 30 for the semiconductor device provided in the embodiment of the present application includes the first pads 31 and the second pads 33, two adjacent first pads 31 are connected by the arch connection portion 32, the second pads 33 are connected to the outermost first pads 31, and since one first pad 31 is connected to one chip 20 on the substrate 10, the bus bar 30 implements power loop connection between the chip 20 and the chip 20 on the substrate 10, and then the second pad 33 is soldered to the substrate 10, implementing power loop connection between the chip 20 and the substrate 10.
The first pad 31 has a first through hole 311, and a convex structure 3111 facing the bonding surface of the first pad 31 is disposed around the first through hole 311. When the bus bar 30 is soldered to the chip 20 on the substrate 10, the first through hole 311 helps to reduce the tangential stress borne by the solder between the chip 20 and the first pad 31 during temperature cycling, the convex hull structure 3111 arranged around the first through hole 311 can avoid the stress concentration of the solder caused by sharp edges, and meanwhile, the convex hull structure 3111 arranged around the first through hole 311 is used to ensure the gap between the chip 20 and the first pad 31, so that the solder is uniformly dispersed during soldering, the thickness of the solder between the chip 20 and the first pad 31 is stably controlled, the temperature shock cycling reliability life of the solder is greatly prolonged, and the reliability of the chip packaging structure 100 is improved.
In addition, when the chip 20 is soldered to the first pad 31, the excessive solder can overflow through the first through hole 311, so that the solder is in the thinnest state after soldering, the generation of heat is reduced, and the cycle life of the solder is prolonged; the first through hole 311 is convenient for observing the state of the solder, and the welding yield is improved.
Optionally, the bus bar 30 for the semiconductor device, which is composed of the first pad 31, the arching connection portion 32, and the second pad 33, is the bus bar 30 formed in one piece, and the integral forming can not only ensure the connection strength between the first pad 31 and the arching connection portion 32 and between the first pad 31 and the second pad 32, but also reduce the manufacturing cost and the material cost.
Alternatively, in order to secure the flow area, the first pad 31 may cover most of the solderable area of the chip 20, for example, the first pad 31 may cover more than 90% of the solderable area of the chip 20.
Optionally, the convex hull structure 3111 is an arc-shaped convex hull structure, so that when the bus bar 30 is welded to the chip 20 on the substrate 10, the peripheral side of the first through hole 311 is prevented from being in vertical contact with the solder, thereby preventing the solder from generating a stress concentration phenomenon, reducing the risk of solder failure, and further ensuring reliability.
In some cases, the height of the arch connection 32 is set low, such as: the height H of the arch connecting portion 32 can be controlled to be 0.4 mm-0.6 mm, on one hand, the lower arch connecting portion 32 can be used to ensure that the arch connecting portion 32 and the first pad 31 have enough rigidity, and on the other hand, when tangential stresses in opposite directions are generated between two adjacent chips 20, the tangential stresses can be transmitted through the arch connecting portion 32, so that the tangential stresses in opposite directions can be finally offset at the arch connecting portion 32, the risk of failure of the first solder layer 40 is reduced, and the reliability is further ensured.
Note that the height of the arch connecting portion 32 refers to a distance between the top surface of the arch connecting portion 32 and the top surface of the first pad 31.
Optionally, referring to fig. 1 to fig. 3 in combination, in an embodiment, a plurality of first through holes 311 are disposed on each first pad 31, and the plurality of first through holes 311 are disposed at intervals along the first direction of the first pad 31. When the bus bar 30 is soldered to the chip 20 on the substrate 10, the tangential stress transmission path caused by mismatch of CTE (Coefficient of thermal expansion) of the system during temperature cycle is blocked by the first through holes 311, which are arranged at intervals, so that the tangential stress borne by the solder between the chip 20 and the first pad 31 during temperature cycle is reduced, the service life of the solder (such as the first solder layer 40) between the first pad 31 and the chip 20 is prolonged, the bonding strength of the bonding part between the first pad 31 and the chip 20 is improved, and the reliability of the product is further improved.
Optionally, referring to fig. 1 and fig. 2 in combination, in an embodiment, the first through hole 311 is a waist-shaped hole, and the waist-shaped hole extends along the second direction of the first pad 31. Alternatively, referring to fig. 1 and 2 in combination, in one embodiment, the length of the kidney-shaped hole is L 1 The width of the first pad 31 is L 2 ，0.7L 2 <L 1 <L 2 。
Optionally, referring to fig. 1, fig. 2 and fig. 4 in combination, in an embodiment, an outer contour of the bonding surface of the first pad 31 is rectangular, at least one corner of the first pad 32 is further provided with a second through hole 312, and the second through hole 312 is arranged in parallel with the first through hole 311.
A gap is present between the first through-hole 311 and the second through-hole 312.
In some cases, since the outer contour of the bonding surface of the first pad 31 is rectangular, when the first pad 31 is bonded to the chip 20, the solder (for example, the first solder layer 40) at four corners corresponding to the bonding surface also has a large stress, and by providing the second through hole 312 at least one corner of the first pad 31 and arranging the second through hole 312 in parallel with the first through hole 311, the area of the maximum stress region at the solder corner can be greatly reduced through the second through hole 312, so as to sufficiently reduce the risk of solder failure, and enable the reliability of the packaged product to be higher.
Alternatively, the second through holes 312 are provided at all four corners of the first pad 31; alternatively, three second through holes 312 are provided at four corners of the first pad 31, that is, the second through holes 312 are provided at three corners, and the second through holes 312 are not provided at one corner; alternatively, 2 second through holes 312 are provided at four corners of the first pad 31, for example, the second through holes 312 are provided at diagonal corners of the first pad 31, or the second through holes 312 are provided at two corners on the same side on the first pad 31; alternatively, the second through hole 312 is provided at any one corner portion of the first pad 31.
The number and the arrangement positions of the second through holes 312 are determined according to the stress release requirement on the first pad 31.
The bus bar 30 is soldered to the chip 21 on the substrate 10 to form the chip package structure 100, and in some alternative embodiments, in order to completely block a tangential stress transmission path caused by CTE mismatch of the system when the chip package structure 100 is subjected to temperature cycling, a sum of a length of one first through hole 311 and a length of at least one second through hole 312 on the first pad 31 is greater than a width of the first pad 31. Such as: when the second through holes 312 are provided at both corners of the same short side of the first pad 31, the sum of the lengths of the two second through holes 312 plus the length of one first through hole 311 is larger than the width of the first pad 31; alternatively, when the second through holes 312 are provided only at one corner portion of two corner portions of the same short side of the first pad 31, the length of one second through hole 312 plus the length of one first through hole 311 is larger than the width of the first pad 31.
Alternatively, referring to fig. 1, fig. 2 and fig. 4 in combination, in an embodiment, the second through hole 312 is a semi-waist-shaped hole, an opening of the semi-waist-shaped hole faces to an outer side of the first pad 31, and the semi-waist-shaped hole is disposed to extend along the second direction of the first pad 31. The semi-kidney-shaped hole can better block a tangential stress transmission path caused by mismatch of system CTE during temperature circulation, reduce the tangential stress borne by solder (such as the first solder layer 40) between the chip 20 and the first bonding pad 31 during temperature circulation, prolong the service life of the solder between the first bonding pad 31 and the chip 20, improve the bonding strength of the bonding part of the first bonding pad 31 and the chip 20, and improve the reliability of the chip packaging structure 100.
Alternatively, referring to fig. 1 and fig. 2 in combination, in an embodiment, a convex structure 3111 facing the bonding surface of the first pad 31 is disposed on the peripheral side of the second through hole 312. The convex hull structure 3111 is utilized to avoid stress concentration of solder (such as solder) caused by sharp edges when the bus bar 30 is welded with the chip 20 on the substrate 10, and the convex hull structure 3111 around the second through hole 312 is utilized to ensure a gap between the chip 20 and the first pad 31, so that the solder is uniformly dispersed during welding, the thickness of the solder between the chip 20 and the first pad 31 is stably controlled, the temperature punching cycle reliability of the solder is greatly prolonged, and the reliability of the chip packaging structure 100 is improved.
In addition, when the chip 20 is soldered to the first pad 31, the excess solder (such as solder) may also overflow through the second through hole 312, so as to ensure that the solder is in the thinnest state after soldering, reduce heat generation, and improve the cycle life of the solder; the second through hole 312 is convenient for observing the state of the solder, and the soldering yield is improved.
Optionally, referring to fig. 1 and fig. 2 in combination, in an embodiment, the length of the first pad 31 in the first direction is greater than the length of the first pad 31 in the second direction, so that the characteristic of current transmission nearby can be fully utilized, the cross-sectional area through which current passes is increased, the structure is more compact, and the space utilization rate is higher.
In some alternative embodiments, referring to fig. 1 and 2 in combination, in an embodiment, the second pad 33 includes a bending connection portion 331 and a substrate soldering portion 332, and the substrate soldering portion 332 is connected to the outermost first pad 31 through the bending connection portion 331.
When the bus bar 30 is soldered to the chip on the substrate, the substrate soldering portion 332 of the second pad 33 of the bus bar 30 is soldered to the substrate 10, the bent connecting portion 331 is connected to the outermost first pad 31 of the bus bar, and the substrate soldering portion 332 is connected to the bent connecting portion 331, thereby realizing the power circuit connection between the chip 20 and the substrate 10.
With reference to fig. 2 to fig. 4, an embodiment of the present application further provides a chip package structure 100, where the chip package structure 100 includes a substrate 10, at least two chips 20, and the bus bar 30 for a semiconductor device as described above, and the specific structure of the bus bar 30 refers to the above embodiments, and since the chip package structure 100 adopts all technical solutions of all the above embodiments, at least all beneficial effects brought by the technical solutions of the above embodiments are achieved, and are not described again. Wherein, at least two chips 20 are arranged on the surface of the substrate 10 in parallel and at intervals; the bus bar 30 is positioned above the substrate 10, and each first pad 31 of the bus bar 30 is soldered to one chip 20 and the second pad 33 of the bus bar 30 is soldered to the substrate 10.
In an alternative embodiment to the above described embodiment, each first pad 31 is soldered to one die 20 via a first solder layer 40 and the second pad 33 is soldered to the substrate 10 via a second solder layer 50.
The above only is the preferred embodiment of the present invention, not limiting the scope of the present invention, all the equivalent structure changes made by the contents of the specification and the drawings under the inventive concept of the present invention, or the direct/indirect application in other related technical fields are included in the patent protection scope of the present invention.
Claims (11)
1. A bus bar for a semiconductor device, comprising:
at least two first bonding pads, wherein two adjacent first bonding pads are connected through an arch connecting part; the first bonding pad is provided with a first through hole, and a convex hull structure facing the welding surface of the first bonding pad is arranged on the periphery of the first through hole;
and a second pad connected to the first pad positioned at the outermost side.
2. The bus bar for a semiconductor device according to claim 1, wherein the first through holes are provided in a plurality, and the plurality of first through holes are arranged at intervals in a first direction of the first pad.
3. The bus bar for a semiconductor device according to claim 1, wherein the first through hole is a kidney-shaped hole, and the kidney-shaped hole is provided to extend in the second direction of the first pad.
4. The bus bar for semiconductor devices according to claim 3, wherein the kidney-shaped hole has a length L 1 The width of the first bonding pad is L 2 ，0.7L 2 <L 1 <L 2 。
5. The bus bar for a semiconductor device according to claim 1, wherein an outer contour of the bonding surface of the first land is rectangular, and a second through hole is further provided at least one corner of the first land, the second through hole being juxtaposed to the first through hole.
6. The bus bar for a semiconductor device according to claim 5, wherein the second through hole is a semi-waist-shaped hole having an opening facing an outer side of the first pad, the semi-waist-shaped hole being provided to extend in a second direction of the first pad.
7. The bus bar for a semiconductor device according to claim 5, wherein a peripheral side of the second through hole is provided with a convex structure facing the first pad bonding face.
8. The bus bar for a semiconductor device according to claim 5, wherein a sum of a length of one of the first through holes and a length of at least one of the second through holes is larger than a width of the first pad.
9. The bus bar for semiconductor devices according to any one of claims 1 to 8, wherein a length of the first pad in a first direction is larger than a length of the first pad in a second direction.
10. The bus bar for a semiconductor device according to any one of claims 1 to 8, wherein the second pad includes a bent connection portion and a substrate welding portion, the substrate welding portion being connected to the outermost first pad through the bent connection portion.
11. A chip package structure, comprising:
a substrate;
at least two chips which are arranged on the surface of the substrate in parallel at intervals;
the bus bar for a semiconductor device according to any one of claims 1 to 10, the bus bar being located above the substrate, each of the first pads of the bus bar being soldered to one of the chips, and the second pad of the bus bar being soldered to the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222280984.6U CN218123402U (en) | 2022-08-29 | 2022-08-29 | Bus bar for semiconductor device and chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222280984.6U CN218123402U (en) | 2022-08-29 | 2022-08-29 | Bus bar for semiconductor device and chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218123402U true CN218123402U (en) | 2022-12-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222280984.6U Active CN218123402U (en) | 2022-08-29 | 2022-08-29 | Bus bar for semiconductor device and chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218123402U (en) |
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2022
- 2022-08-29 CN CN202222280984.6U patent/CN218123402U/en active Active
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Address after: 215000 52 tianedang Road, Yuexi, Wuzhong District, Suzhou City, Jiangsu Province Patentee after: Suzhou Huichuan United Power System Co.,Ltd. Address before: 215104 No. 52, tiandang Road, Yuexi, Wuzhong District, Suzhou City, Jiangsu Province Patentee before: SUZHOU HUICHUAN UNITED POWER SYSTEM Co.,Ltd. |