CN111326489A - Power device packaging structure - Google Patents

Power device packaging structure Download PDF

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Publication number
CN111326489A
CN111326489A CN202010270187.2A CN202010270187A CN111326489A CN 111326489 A CN111326489 A CN 111326489A CN 202010270187 A CN202010270187 A CN 202010270187A CN 111326489 A CN111326489 A CN 111326489A
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China
Prior art keywords
bonding
area
chip
power device
copper sheet
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CN202010270187.2A
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Chinese (zh)
Inventor
朱袁正
朱久桃
胡伟
叶美仙
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Wuxi Dianji Integrated Technology Co ltd
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Wuxi Dianji Integrated Technology Co ltd
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Priority to CN202010270187.2A priority Critical patent/CN111326489A/en
Publication of CN111326489A publication Critical patent/CN111326489A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention relates to the technical field of semiconductor device processing technology, in particular to a power device packaging structure which comprises a chip, a lead frame, a copper sheet and an epoxy resin packaging body, wherein the lead frame comprises a pin area and a base island area, the chip is arranged on the base island area, the epoxy resin packaging body fully wraps the chip and the base island area and partially wraps the pin area, the chip is provided with a first bonding area and a second bonding area, the surface of the second bonding area is provided with a bonding point, one end of the copper sheet is welded on the bonding point through a welding material, the other end of the copper sheet is welded on the pin area, and the epoxy resin packaging body fully wraps or partially wraps the copper sheet; the scheme realizes the connection of the copper sheet lead and the chip by arranging the bonding point on the second bonding area of the power device, the copper sheet can increase the contact area, greatly reduce the thermal resistance and temperature rise of the power device, effectively improve the maximum fusing current of chip packaging, reduce the on-resistance of the device, furthest exert the actual current capacity of the chip and improve the reliability of the device.

Description

Power device packaging structure
Technical Field
The invention relates to the technical field of semiconductor device processing technology, in particular to a power device packaging structure.
Background
With the continuous development of the power device packaging technology, under the traditional packaging technology, the proportion of the packaging resistance of the power device in the total resistance is gradually increased and even exceeds the internal resistance of the chip, in addition, the packaging thermal resistance of the power device is larger, and the packaging thermal resistance determines the maximum power loss of the device, if the packaging thermal resistance and the parasitic resistance can be reduced, the conduction loss of the power device is favorably reduced, the use temperature rise of the power device is reduced, and the overall efficiency of the power device is improved.
In a traditional power device (such as MOSFET and IGBT products) packaging process, metal materials such as gold wires, copper wires, aluminum strips and the like are generally used as leads to weld a chip and a pin, so as to realize electrical connection, and the existing metal wire welding methods have the following problems:
the wire welding process of the gold wire or the copper wire is limited by the process capability, although the gold wire or the copper wire has the advantages of high conductivity, corrosion resistance and the like and is suitable for high-speed bonding and packaging processes, the through-current capability of a single gold wire or a single copper wire is limited, and the gold wire or the copper wire can be blown by overlarge current, so that a power device generally needs to adopt the process of a plurality of gold wires or copper wires to realize the high-current passing capability, but the plurality of gold wires or copper wires can generate larger parasitic resistance, so that the power efficiency is reduced, and the power loss is increased. As shown in fig. 1, a schematic diagram of a conventional gold or copper wire bonded package is given.
Although the single through-current capacity of the aluminum wire is greater than that of a gold wire and a copper wire, in the aluminum wire welding process, the aluminum wire is quickly rubbed on the surface of an aluminum metalized layer of a welded area, so that the aluminum wire and the surface of a chip electrode generate plastic deformation to achieve the welding effect, and therefore, the chip is greatly impacted after multiple wedge welding, the chances of dark cracks and craters in the chip are increased, the thickness of the aluminum layer serving as a chip bonding pad is required to be increased, and the manufacturing cost and difficulty of the chip are increased; meanwhile, since the impedance of the aluminum wire itself is greater than that of the gold wire and the copper wire, the greater impedance causes transmission loss of current, thereby increasing power consumption.
As shown in fig. 2, a schematic diagram of conventional aluminum strip welding is given. Although the aluminum tape has a large through-current capacity, the aluminum tape requires a large amount of pressure and ultrasonic energy during bonding, which causes a large impact on the chip, and this requires that the thickness of the aluminum layer serving as the chip pad must be increased, so as to avoid damaging the circuit below the chip pad during bonding, which in turn causes an increase in the manufacturing cost and difficulty of the chip.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a power device packaging structure.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
a power device packaging structure comprises a chip, a lead frame, a copper sheet and an epoxy resin packaging body, wherein the lead frame comprises a pin area and a base island area, the chip is arranged on the base island area, the epoxy resin packaging body fully wraps the chip and the base island area and partially wraps the pin area, the chip is provided with a first bonding area and a second bonding area, the surface of the second bonding area is provided with a bonding point, one end of the copper sheet is welded on the bonding point through a welding material, the other end of the copper sheet is welded on the pin area, and the epoxy resin packaging body fully wraps or partially wraps the copper sheet.
As an improvement, the lead frame further comprises a heat dissipation area, and the epoxy resin packaging body part wraps the heat dissipation area.
Preferably, the material of the bonding point is gold, silver, copper or alloy.
Preferably, the bonding points are circular, square, rectangular or irregular in shape.
Preferably, the bonding point is disposed on the surface of the second bonding region through a tin-coating process, a tin-melting process, a cold-pressure welding process, a friction welding process, an explosion welding process, an electron beam welding process, an ultrasonic welding process, or a brazing process.
Preferably, the solder material is a tin-based alloy material, a silver sintered material, or a copper sintered material.
Preferably, the height of the bonding point is 20um to 5 mm.
Preferably, the number of bonding sites is at least 1.
Preferably, when the number of the bonding sites is plural, the plural bonding sites are spaced apart from each other.
Preferably, adjacent bonding points are connected through copper wires.
From the above description, it can be seen that the present invention has the following advantages:
1. the bonding point is arranged on the second bonding area of the power device, so that the copper sheet is connected with the chip.
2. The shape and distribution of the bonding points can be determined according to the functions of the product, the universality of the copper sheet is effectively improved, the copper sheet is connected with the chip through the bonding points, the process yield and the product reliability of the copper sheet when the copper sheet is applied to packaging of the power product are effectively improved, and the method plays a vital role in the performance of the product.
3. The bonding points are used as transition connection materials between the chip and the copper sheet, so that the technical difficulty of packaging is effectively reduced, and the additional process and cost pressure caused by the need of carrying out surface metallization treatment on the wafer are avoided.
Drawings
FIG. 1 is a diagram of a conventional gold or copper wire bonded package;
FIG. 2 is a diagram of a conventional aluminum tape welded package;
FIG. 3 is a perspective view of the structure of embodiment 1 of the present invention;
FIG. 4 is a front view of embodiment 1 of the present invention;
FIG. 5 is a side view of embodiment 1 of the present invention;
FIG. 6 is a sectional view taken along A-A in example 1 of the present invention;
FIG. 7 is an enlarged view of a portion of the bond site of FIG. 6;
FIG. 8 is an internal structural view of embodiment 1 of the present invention;
FIG. 9 is a perspective view of the structure of embodiment 2 of the present invention;
FIG. 10 is a front view of embodiment 2 of the present invention;
FIG. 11 is a front view of embodiment 2 of the present invention;
FIG. 12 is a front view of embodiment 2 of the present invention;
FIG. 13 is a front view of embodiment 2 of the present invention;
FIG. 14 is a diagram of a packaging process in embodiment 2 of the present invention;
fig. 15 is a diagram of a packaging process in embodiment 2 of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail with reference to fig. 3-15, but the present invention is not limited thereto.
Example 1
As shown in fig. 3-8, taking a TO-263 surface mount package as an example, a power device package structure is provided, which includes a MOSFET chip 1, a lead frame 2, a copper sheet 3, and an epoxy package 4, where the lead frame 2 includes a lead region 21, a base island region 22, and a heat dissipation region 23, the chip 1 is disposed on the base island region 22, the chip 1 has a first bonding region 11 and a second bonding region 12, a bonding point 5 is disposed on a surface of the second bonding region 12, one end of the copper sheet 3 is soldered TO the bonding point 5 through a soldering material 6, and the other end is soldered TO the lead region 21, and the epoxy package 4 completely wraps the chip 1, the copper sheet 3, and the base island region 22, and partially wraps the lead region 21 and the heat dissipation region 23.
Wherein:
(1) the material of the bonding point 5 can be gold, silver, copper or alloy, and then the bonding point is arranged on the surface of the second bonding area through an ultrasonic welding process;
(2) the number of the bonding points 5 is 2, the bonding points are mutually separated and are rectangular;
(3) one end of the copper sheet 3 is welded on the bonding point 5 through a welding material such as a tin-based alloy material, a silver sintered material or a copper sintered material, and the effect of wetting the bonding point with the welding material is formed, as shown in fig. 7.
In order TO facilitate understanding of the technical solution of embodiment 1, taking the specific structure of the TO-263 chip package given in embodiment 1 as an example, the application of the technical solution in the T0-263 package structure is further described in detail: as shown in fig. 3, the heat dissipation region 23 of the lead frame 2 is connected to the base island region 22, the lead region 21 includes a first pin 211, a second pin 212, and a third pin 213 sequentially arranged, the second pin 212 is located between the first pin 211 and the third pin 213, a first bonding region 2111 is disposed on the top of the first pin 211, a second bonding region 2131 is disposed on the top of the third pin 213, the back surface of the MOSFET chip 1 is a drain, the front surface is provided with a gate and a source (i.e., a first bonding region 11 and a second bonding region 12), the first bonding region 11 is connected to the first bonding region 2111 by a lead, the drain is connected to the second pin 212 by the base island region 22, one end of the copper sheet 3 is soldered to the bonding pad 5 by a solder material 6, the other end is soldered to the second bonding region 2131, the epoxy resin package 4 encapsulates the chip 1, the copper sheet 3, the lead area 21, the base island area 22 and the heat dissipation area 23 are partially exposed, and the lead area 21 and the heat dissipation area 23 are partially exposed. This section is described as a specific solution of the present technical solution applied to the T0-263 package structure, and does not limit the protection scope of the present invention, and when the present invention is applied, the basic package implementation schemes of the chip, the lead frame, and the epoxy resin package are the same as the prior art, and the differences are only: and designing a bonding point on a second bonding area of the chip, and forming a connecting structure between the bonding point and the lead frame through the copper sheet.
Example 2
As shown in fig. 9, taking a PDFN5X6 chip package form as an example, a power device package structure is provided, which includes a chip 1, a lead frame 2, a copper sheet 3, and an epoxy package 4, where the lead frame 2 includes a lead region 21 and a base island region 22, the chip 1 is disposed on the base island region 22, the chip 1 has a first bonding region 11 and a second bonding region 12, a bonding point 5 is disposed on a surface of the second bonding region 12, one end of the copper sheet 3 is soldered to the bonding point 5 through a soldering material 6, and the other end is soldered to the lead region 21, and the epoxy package 4 fully wraps the chip 1 and the base island region 22, partially wraps the lead region 21, and fully wraps or partially wraps the copper sheet 3. The solder material portion is simplified in fig. 9 for convenience of showing the structure of the bonding point.
Wherein:
(1) the material of the bonding point 5 can be gold, silver, copper or alloy, and then the bonding point is arranged on the surface of the second bonding area through a tin coating process, a tin melting process, a cold-press welding process, a friction welding process, an explosion welding process, an electron beam welding process, an ultrasonic welding process or a brazing process;
(2) the number and shape of the bonding points 5 can adopt the following structures: as shown in fig. 10, the number of the bonding points is 1, and the bonding points are rectangular (the bonding points are made of copper strips and are disposed in the second bonding region through an ultrasonic welding process); as shown in fig. 11 and 12, the number of the bonding points is 8, the bonding points are distributed in a matrix, each bonding point 5 is rectangular, the bonding points 5 located in the same column are connected by copper wires 7, and the connection manner of the copper wires 7 can be that the copper wires shown in fig. 11 are attached to the surface of the bonding area for connection or the copper wires shown in fig. 12 are suspended above the surface of the bonding area for connection; as shown in fig. 13, the number of the bonding points is 10, the bonding points are irregularly distributed, each bonding point 5 is circular, and the bonding points are not connected with each other; in fig. 10 to 13, only the internal structure of the package structure is shown for the purpose of showing the structure of the bonding point, and the solder material portion is simplified.
(3) One end of the copper sheet 3 is welded on the bonding point 5 through a tin-based alloy material, a silver sintering material or a copper sintering material, and the effect of wetting the bonding point and the welding material is formed.
Fig. 14 and 15 are schematic views of the packaging process of example 2. The packaging effect of fig. 14 is that the epoxy resin packaging body fully wraps the copper sheet 3, and the packaging effect of fig. 15 is that the epoxy resin packaging body partially wraps the copper sheet 3, and the surface of the copper sheet 3 is partially exposed, so that the heat dissipation area of the device can be increased, and the heat dissipation effect is improved. The solder material portions are simplified in fig. 14 and 15 for the convenience of showing the structure of the bonding points.
When the invention is applied specifically, the invention is not limited to the schemes of the two specific embodiments, and the following choices can be made:
1. the number of bond sites is not limited and there may be 1 or more bond sites. When a plurality of bonding points exist, the distribution form of the bonding points can be determined according to the actual functional requirements of the product, such as matrix type, annular array, irregular array and the like; the plurality of bonding points are separated, or are connected through copper wires after being separated (when the copper wires are used for connection, the copper wires are attached to the surfaces of the bonding areas to be connected as shown in the figure), and the bonding points forming the connection relationship can be all bonding points or partial bonding points; when the bonding points are spaced apart, they may be equally spaced apart or may be unequally spaced apart.
2. The material of the bonding point can be gold, silver, copper or alloy, and then the bonding point is arranged on the surface of the second bonding area through a tin coating process, a tin melting process, a cold pressure welding process, a friction welding process, an explosion welding process, an electron beam welding process, an ultrasonic welding process or a brazing process;
3. one end of the copper sheet is welded on the bonding point through a tin-based alloy material, a silver sintering material or a copper sintering material, and the effect of infiltrating the bonding point and the welding material is formed;
4. the applicable chip range in the scheme is a silicon-based MOSFET chip, a silicon-based IGBT chip, a SiC chip or a GaN chip.
5. The shape and structure of the copper sheet are not limited as long as the copper sheet can play a role of a lead, and the copper sheet can be a bent structure formed by a stamping process shown in fig. 3 or other shape structures.
The bonding point is arranged on the second bonding area of the power device, so that the copper sheet lead is connected with the chip. The shape and the distribution of the bonding points can be determined according to the functions of the product, the universality of the copper sheet is effectively improved, the copper sheet is connected with the chip through the bonding points, the process yield and the product reliability of the copper sheet when the copper sheet is applied to packaging of the power product are effectively improved, and the method plays a vital role in the performance of the product.
In summary, the invention has the following advantages:
1. the bonding point is arranged on the second bonding area of the power device, so that the copper sheet lead is connected with the chip.
2. The shape and distribution of the bonding points can be determined according to the functions of the product, the universality of the copper sheet is effectively improved, the copper sheet is connected with the chip through the bonding points, the process yield and the product reliability of the copper sheet when the copper sheet is applied to packaging of the power product are effectively improved, and the method plays a vital role in the performance of the product.
3. The bonding points are used as transition connection materials between the chip and the copper sheet, so that the technical difficulty of packaging is effectively reduced, and the additional process and cost pressure caused by the need of carrying out surface metallization treatment on the wafer are avoided.
It should be understood that the detailed description of the invention is merely illustrative of the invention and is not intended to limit the invention to the specific embodiments described. It will be appreciated by those skilled in the art that the present invention may be modified or substituted equally as well to achieve the same technical result; as long as the use requirements are met, the method is within the protection scope of the invention.

Claims (10)

1. A power device packaging structure comprises a chip, a lead frame, a copper sheet and an epoxy resin packaging body, wherein the lead frame comprises a pin area and a base island area, the chip is arranged on the base island area, the epoxy resin packaging body fully wraps the chip and the base island area, and partially wraps the pin area, and the power device packaging structure is characterized in that: the chip is provided with a first bonding area and a second bonding area, a bonding point is arranged on the surface of the second bonding area, one end of the copper sheet is welded on the bonding point through a welding material, the other end of the copper sheet is welded on the pin area, and the epoxy resin packaging body fully wraps or partially wraps the copper sheet.
2. The power device package structure of claim 1, wherein: the lead frame further comprises a heat dissipation area, and the epoxy resin packaging body portion wraps the heat dissipation area.
3. The power device package structure according to claim 1 or 2, wherein: the bonding points are made of gold, silver, copper or alloy.
4. The power device package structure according to claim 1 or 2, wherein: the bonding points are round, square, rectangular or irregular.
5. The power device package structure according to claim 1 or 2, wherein: the bonding point is arranged on the surface of the second bonding area through a tin hanging process, a tin melting process, a cold welding process, a friction welding process, an explosion welding process, an electron beam welding process, an ultrasonic welding process or a brazing process.
6. The power device package structure according to claim 1 or 2, wherein: the welding material is a tin-based alloy material, a silver sintering material or a copper sintering material.
7. The power device package structure according to claim 1 or 2, wherein: the height of the bonding point is 20 um-5 mm.
8. The power device package structure according to claim 1 or 2, wherein: the number of bonding points is at least 1.
9. The power device package structure of claim 8, wherein: when the number of the bonding points is multiple, the multiple bonding points are mutually separated.
10. The power device package structure of claim 9, wherein: and adjacent bonding points are connected through copper wires.
CN202010270187.2A 2020-04-08 2020-04-08 Power device packaging structure Pending CN111326489A (en)

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CN112086372A (en) * 2020-09-21 2020-12-15 南瑞联研半导体有限责任公司 Packaging material structure layer for front connection of high junction temperature power module chip and manufacturing method thereof
CN112530894A (en) * 2020-11-25 2021-03-19 通富微电子股份有限公司技术研发分公司 Power module, electronic device with power module and preparation method of bonding metal sheet
CN116314069A (en) * 2023-05-23 2023-06-23 深圳市秀武电子有限公司 MOS semiconductor power device and packaging method thereof

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CN205984966U (en) * 2016-07-12 2017-02-22 无锡新洁能股份有限公司 Big current power semiconductor device's packaging structure
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CN112086372A (en) * 2020-09-21 2020-12-15 南瑞联研半导体有限责任公司 Packaging material structure layer for front connection of high junction temperature power module chip and manufacturing method thereof
CN112530894A (en) * 2020-11-25 2021-03-19 通富微电子股份有限公司技术研发分公司 Power module, electronic device with power module and preparation method of bonding metal sheet
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