CN218867091U - Package substrate - Google Patents

Package substrate Download PDF

Info

Publication number
CN218867091U
CN218867091U CN202222529916.9U CN202222529916U CN218867091U CN 218867091 U CN218867091 U CN 218867091U CN 202222529916 U CN202222529916 U CN 202222529916U CN 218867091 U CN218867091 U CN 218867091U
Authority
CN
China
Prior art keywords
substrate
layer
metal line
package substrate
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202222529916.9U
Other languages
Chinese (zh)
Inventor
曹菲菲
张馥麟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Liding Semiconductor Technology Qinhuangdao Co ltd
Liding Semiconductor Technology Shenzhen Co ltd
Original Assignee
Liding Semiconductor Technology Qinhuangdao Co ltd
Liding Semiconductor Technology Shenzhen Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Liding Semiconductor Technology Qinhuangdao Co ltd, Liding Semiconductor Technology Shenzhen Co ltd filed Critical Liding Semiconductor Technology Qinhuangdao Co ltd
Priority to CN202222529916.9U priority Critical patent/CN218867091U/en
Application granted granted Critical
Publication of CN218867091U publication Critical patent/CN218867091U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A package substrate having a thickness direction along which the package substrate includes an inner circuit substrate and an outer circuit substrate disposed on at least one side of the inner circuit substrate, the package substrate further comprising: the first metal wire is arranged along the thickness direction, one end of the first metal wire is electrically connected with the inner side circuit substrate, and the other end of the first metal wire is electrically connected with the outer side circuit substrate. The application provides a packaging substrate has the advantage that wiring density is big.

Description

Package substrate
Technical Field
The present application relates to a package substrate.
Background
The packaging substrate not only provides supporting, heat dissipation and protection effects for the chip, but also can establish signal connection between the chip and other components, and plays a role of ' starting from the top ' and stopping from the bottom '. With the development of semiconductor technology, the size of a chip is continuously reduced, the integration level is continuously improved, and the corresponding chip package is developed towards the trend of multiple pins, narrow spacing and high density. However, the wiring density and the number of pins of the conventional package substrate are difficult to satisfy the above trend.
SUMMERY OF THE UTILITY MODEL
To solve the problems in the background art, the present application provides a package substrate.
A package substrate having a thickness direction along which the package substrate includes an inner circuit substrate and an outer circuit substrate disposed on at least one side of the inner circuit substrate, the package substrate further comprising: the first metal wire is arranged along the thickness direction, one end of the first metal wire is electrically connected with the inner side circuit substrate, and the other end of the first metal wire is electrically connected with the outer side circuit substrate.
Furthermore, the package substrate further comprises an inner side insulating layer, the inner side insulating layer covers the inner side circuit substrate, the inner side insulating layer is provided with a first opening in a penetrating mode, part of the inner side circuit substrate is exposed out of the bottom of the first opening, and the first metal wire is contained in the first opening.
Further, the inner circuit substrate further comprises a first filling body, the first filling body fills the first opening, and the first filling body wraps the first metal wire.
Further, the inboard circuit substrate includes the inboard substrate layer and set up in the inboard circuit layer of inboard substrate layer, inboard circuit layer includes inboard connecting pad, the one end of metal wire is connected inboard inner joint pad.
Further, outside circuit substrate includes outside insulating layer, first outside circuit layer and second outside circuit layer, first outside circuit layer with second outside circuit layer set up respectively in the relative both sides of inboard substrate layer, first outside circuit layer includes first outside connection pad, the other end of first metal wire is connected first outside connection pad.
Further, the outside circuit substrate further comprises a second metal wire, the second outside circuit layer further comprises a plurality of second outside connection pads, the second metal wire is arranged on the outside insulating layer along the thickness direction, one end of the second metal wire is electrically connected with the first outside connection pads, and the other end of the second metal wire is electrically connected with the second outside connection pads.
Furthermore, the inner substrate layer is provided with a second opening in a penetrating manner, the outer circuit substrate further comprises a second filling body, the second metal wire is contained in the second opening, and the second filling body wraps the second metal wire.
Furthermore, the first metal wire and the second metal wire are formed by a routing mode.
Further, the first metal wire or the second metal wire includes a body portion and end portions disposed at opposite ends of the body portion, and a cross-sectional width of the end portions is greater than a cross-sectional width of the body portion.
Furthermore, the inner connecting pad is arranged corresponding to the first outer connecting pad, and the first outer connecting pad is arranged corresponding to the second outer connecting pad.
The utility model provides a packaging substrate passes through first metal wire is connected inboard circuit substrate with outside circuit substrate, because single the diameter of first metal wire is less to be favorable to realizing that it is limited in the volume packaging substrate arranges more first metal wire, and then increase wiring density.
Drawings
Fig. 1 is a schematic cross-sectional view of a package substrate according to a first embodiment of the disclosure.
Fig. 2 is a schematic cross-sectional view of a package substrate according to a second embodiment of the present application.
Description of the main elements
Package substrates 100, 200
Inner circuit board 10
First filling body 11
Inner base material layer 12
Inner circuit layer 13
Inner connecting pad 131
Outer circuit board 20
Outer insulating layer 21
Second opening 211
First outer wiring layer 22
First outer connecting pad 221
Second outer wiring layer 23
Second outside connection pad 231
Second metal line 24
Second filling body 25
First metal line 40
Body part 41
First end 42
Second end 43
Inner insulating layer 50
First opening 51
Third metal line 201
Fourth metal line 202
Thickness direction A
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments.
Referring to fig. 1, a package substrate 100 according to a first embodiment of the present disclosure includes an inner circuit substrate 10, two outer circuit substrates 20, and a plurality of first metal lines 40. The two outer circuit boards 20 are respectively disposed on two opposite sides of the inner circuit board 10. The first metal line 40 is disposed between the inner circuit board 10 and the outer circuit board 20.
Referring to fig. 1, in the present embodiment, the package substrate 100 has a thickness direction a, and the first metal line 40 is disposed between the inner circuit substrate 10 and the outer circuit substrate 20 along the thickness direction a. One end of the first metal line 40 is electrically connected to the inner circuit board 10, and the other end is electrically connected to the outer circuit board 20. Wherein the first metal line 40 has a diameter of less than 10 microns.
The application provides a packaging substrate 100 passes through first metal wire 40 connects inboard circuit substrate 10 with outside circuit substrate 20, because single first metal wire 40's diameter is less than the diameter of blind hole or through-hole to be favorable to realizing in the volume is limited packaging substrate 100 arranges more first metal wire 40, and then increases wiring density.
Referring to fig. 1, in the present embodiment, the package substrate 100 further includes an inner insulating layer 50, the inner insulating layer 50 is disposed between the inner circuit substrate 10 and the outer circuit substrate 20, and the first metal line 40 is embedded in the inner insulating layer 50. Specifically, the inner insulating layer 50 is provided with a first opening 51, a portion of the inner circuit substrate 10 is exposed at the bottom of the first opening 51, and the first metal line 40 is accommodated in the first opening 51. The inner circuit board 10 further includes a first filling body 11, the first filling body 11 is filled in the first opening 51, and the first filling body 11 covers the first metal wire 40, so as to fix the first metal wire 40, and improve the connection stability between the first metal wire 40 and the inner circuit board 10 and between the first metal wire and the outer circuit board 20.
Referring to fig. 1, in the present embodiment, the first metal line 40 is substantially in an "i" shape, and the first metal line 40 includes a body portion 41, a first end portion 42, and a second end portion 43. The first end portion 42 and the second end portion 43 are respectively provided at opposite ends of the body portion 41. The first end portion 42 and the second end portion 43 have a cross-sectional width greater than a cross-sectional width of the body portion 41. Specifically, the first metal line 40 is formed by Wire Bonding (Wire Bonding). The first metal line 40 may be made of one or more of gold, silver, copper, iron, aluminum, or other metals that can be connected to the inner connecting pad 131.
Referring to fig. 1, in the present embodiment, the inner circuit board 10 includes an inner base material layer 12 and two inner circuit layers 13. The two inner side circuit layers 13 are respectively disposed on two opposite sides of the inner side base material layer 12. The inner circuit layer 13 includes an inner connecting pad 131, and the first end 42 is connected to the inner connecting pad 131 substantially perpendicularly. The outer circuit board 20 includes an outer insulating layer 21, a first outer wiring layer 22, and a second outer wiring layer 23. The first outer circuit layer 22 and the second outer circuit layer 23 are respectively disposed on two opposite sides of the outer circuit substrate 20, the first outer circuit layer 22 includes a first outer connecting pad 221, and the second end 43 is substantially perpendicularly connected to the first outer connecting pad 221. As the arrangement density of the first metal lines 40 increases, the arrangement density of the inner connecting pads 131 and the arrangement density of the first outer connecting pads 221 also increase accordingly. The second outer circuit layer 23 includes a second outer connection pad 231, and the second outer connection pad 231 is used for connecting a chip (not shown). The material of the inner insulating layer 50 is the same as that of the outer insulating layer 21.
Referring to fig. 1, in the present embodiment, the outer circuit substrate 20 further includes a second metal line 24, the second metal line 24 is disposed in the outer insulating layer 21 along the thickness direction a, one end of the second metal line 24 is electrically connected to the first outer connecting pad 221, the other end is electrically connected to the second outer connecting pad 231, and the first outer circuit layer 22 and the second outer circuit layer 23 are electrically connected through the second metal line 24. The shape of the first metal line 40 is similar, and the second metal line 24 is formed by wire bonding.
Referring to fig. 1, in the present embodiment, a second opening 211 is formed through the outer insulation layer 21, and the second opening 211 is substantially corresponding to the first opening 51. The outer circuit substrate 20 further includes a second filling body 25, the second metal line 24 is accommodated in the second opening 211, and the second filling body 25 covers the second metal line 24. The inner connecting pad 131 is disposed corresponding to the first outer connecting pad 221, and the first outer connecting pad 221 is disposed corresponding to the second outer connecting pad 231.
Referring to fig. 2, a package substrate 200 is provided according to a second embodiment of the present disclosure. The difference from the first embodiment is that the package substrate 200 includes a third metal line 201 and a fourth metal line 202, and the third metal line 201 is connected between the inner connecting pad 131 and the first outer connecting pad 221. The fourth metal line 202 is connected between the first outer connection pad 221 and the second outer connection pad 231. The third metal line 201 and the fourth metal line 202 are substantially "T" shaped, that is, the first end 42 or the second end 43 is removed from the first metal line 40. Specifically, the third metal line 201 and the fourth metal line 202 may also be formed by wire bonding to form a metal Bump (Ball Bump).
Hereinbefore, specific embodiments of the present application are described with reference to the drawings. However, those skilled in the art will appreciate that various modifications and substitutions can be made to the specific embodiments of the present application without departing from the spirit and scope of the application. Such modifications and substitutions are intended to be within the scope of the present application.

Claims (10)

1. A package substrate having a thickness direction, the package substrate including an inner circuit substrate and an outer circuit substrate disposed on at least one side of the inner circuit substrate, the package substrate further comprising:
the first metal wire is arranged along the thickness direction, one end of the first metal wire is electrically connected with the inner side circuit substrate, and the other end of the first metal wire is electrically connected with the outer side circuit substrate.
2. The package substrate of claim 1, further comprising an inner insulating layer covering the inner circuit substrate, wherein the inner insulating layer has a first opening formed therethrough, a portion of the inner circuit substrate is exposed at a bottom of the first opening, and the first metal line is received in the first opening.
3. The package substrate of claim 2, wherein the inner circuit substrate further comprises a first filler, the first filler filling the first opening, the first filler encapsulating the first metal line.
4. The package substrate of claim 1, wherein the inner circuit substrate comprises an inner substrate layer and an inner circuit layer disposed on the inner substrate layer, the inner circuit layer comprises inner connection pads, and one end of the metal wire is connected to the inner connection pads.
5. The package substrate according to claim 4, wherein the outer circuit substrate comprises an outer insulating layer, a first outer circuit layer and a second outer circuit layer, the first outer circuit layer and the second outer circuit layer are respectively disposed on two opposite sides of the inner substrate layer, the first outer circuit layer comprises a first outer connection pad, and the other end of the first metal wire is connected to the first outer connection pad.
6. The package substrate of claim 5, wherein the outer circuit substrate further comprises a second metal line, the second outer circuit layer further comprises a plurality of second outer connection pads, the second metal line is disposed on the outer insulation layer along the thickness direction, and one end of the second metal line is electrically connected to the first outer connection pads and the other end of the second metal line is electrically connected to the second outer connection pads.
7. The package substrate of claim 6, wherein the inner substrate layer has a second opening formed therethrough, and the outer circuit substrate further comprises a second filler, the second metal wire is received in the second opening, and the second filler encapsulates the second metal wire.
8. The package substrate of claim 6, wherein the first metal line and the second metal line are formed by wire bonding.
9. The package substrate of claim 6, wherein the first metal line or the second metal line comprises a body portion and end portions disposed at opposite ends of the body portion, the end portions having a cross-sectional width greater than a cross-sectional width of the body portion.
10. The package substrate of claim 6, wherein the inner connection pad is disposed corresponding to the first outer connection pad, and the first outer connection pad is disposed corresponding to the second outer connection pad.
CN202222529916.9U 2022-09-23 2022-09-23 Package substrate Active CN218867091U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202222529916.9U CN218867091U (en) 2022-09-23 2022-09-23 Package substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202222529916.9U CN218867091U (en) 2022-09-23 2022-09-23 Package substrate

Publications (1)

Publication Number Publication Date
CN218867091U true CN218867091U (en) 2023-04-14

Family

ID=87367510

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202222529916.9U Active CN218867091U (en) 2022-09-23 2022-09-23 Package substrate

Country Status (1)

Country Link
CN (1) CN218867091U (en)

Similar Documents

Publication Publication Date Title
JP3147053B2 (en) Resin-sealed ball grid array IC package and method of manufacturing the same
JP3066579B2 (en) Semiconductor package
KR100753415B1 (en) Stack package
US6507098B1 (en) Multi-chip packaging structure
TWI404175B (en) Semiconductor package having electrical connecting structures and fabrication method thereof
JPH07169872A (en) Semiconductor device and manufacture thereof
KR20050064144A (en) Semiconductor module having semiconductor chip package which is vertically mounted on module board
US20090146314A1 (en) Semiconductor Device
JPH03291869A (en) Electronic device
US7015591B2 (en) Exposed pad module integrating a passive device therein
KR20010056618A (en) Semiconductor package
CN218867091U (en) Package substrate
JPS61137335A (en) Semiconductor device
KR20010056778A (en) Chip size package
CN115995440A (en) Semiconductor packaging structure and manufacturing method thereof
JP2018190882A (en) Semiconductor device
CN209312758U (en) A kind of silicon wafer encapsulating structure
KR101089647B1 (en) Board on chip package substrate and manufacturing method thereof
JP2891426B2 (en) Semiconductor device
US20060180902A1 (en) Semiconductor package with low and high-speed signal paths
JP2722451B2 (en) Semiconductor device
US20080087999A1 (en) Micro BGA package having multi-chip stack
KR950014124B1 (en) Semiconductor package and manufacture method
JPH10209321A (en) Semiconductor integrated circuit device
KR20060133800A (en) Chip stack package

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant