CN209312758U - A kind of silicon wafer encapsulating structure - Google Patents
A kind of silicon wafer encapsulating structure Download PDFInfo
- Publication number
- CN209312758U CN209312758U CN201920223070.1U CN201920223070U CN209312758U CN 209312758 U CN209312758 U CN 209312758U CN 201920223070 U CN201920223070 U CN 201920223070U CN 209312758 U CN209312758 U CN 209312758U
- Authority
- CN
- China
- Prior art keywords
- silicon wafer
- layer
- insulating protective
- protective layer
- slot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model discloses a kind of silicon wafer encapsulating structures and preparation method thereof in field of semiconductor devices; encapsulating structure includes covering to be equipped with silicon wafer sheath on silicon wafer and aluminium pad; the first insulating protective layer and adherency conductive layer are equipped with above silicon wafer sheath; it adheres to and is equipped with metal wiring layer and the second insulating protective layer on the upside of conductive layer, offer windowing slot on the second insulating protective layer；The method includes the first insulating protective layer is formed above silicon wafer sheath；It is exposed and develops to metal line sandwich circuit place is needed to form, exposed portion metal connects solder joint and covers adherency conductive layer, removes extra metallic region to form metal wiring layer；The second insulating protective layer is finally covered on silicon wafer, is exposed and develops to the place for newly connecing solder joint is needed to form, and the metal wiring layer of exposing, that is, new connects spot area.The utility model can rearrange the rational position for connecing solder joint to chip, and chip design is more flexible, solve the problems, such as turning route overetch, promote IC chip reliability.
Description
Technical field
The utility model belongs to field of semiconductor devices, in particular to a kind of silicon wafer encapsulating structure and preparation method thereof.
Background technique
In the prior art, integrated circuit device generally includes the IC chip being accommodated in encapsulation or bare chip.The IC
Chip is generally included using known manufacturing technology on the thin wafer of semiconductor, is made of photoengraving pattern conduction and insulating materials
Circuit.The IC chip is supported and is protected in the encapsulation, and provides being electrically connected between the circuit and the external circuit board.Citing
For, some known encapsulated types are used to accommodate IC chip, such as ball grid array (ball grid array, BGA), needle grid
Array (pin grid arrays, PGA), plastic packaging leaded chip carrier (plastic leaded chip carrier,
PLCC), plastic packaging flat package (plastic quadflat pack) and other.
Encapsulation, just refers to the circuit pin on silicon wafer, is connect and guided at external lug with conducting wire, to connect with other devices
It connects.Packing forms refer to the shell of installation semiconductor integrated circuit chip.It not only plays installation, fixation, sealing, protection core
The effect of piece and enhancing electric heating property etc., but also it is wired to by the contact on chip the pin of package casing
On, these pins are connected further through the conducting wire on printed circuit board with other devices, to realize inside chip and external electrical
The connection on road.
The encapsulating structure of tradition silicon wafer can not rearrange any rational position for connecing solder joint to chip at present, and chip is being set
Timing is inflexible；Traditional metal wiring layer uses right angle corner, using chemical etching by extra metallic region removal from
And when forming metallic circuit, etching solution accumulation easily occurs for route corner angle, lead to corner's bottom metal overetch,
Reduce IC reliability；The stress of substrate and inter-module is larger, and component is less reliable.
Utility model content
One of the purpose of this utility model is to provide a kind of silicon wafer encapsulating structure, can rearrange and connect solder joint to chip
Any rational position, chip is more flexible when designing, and can improve the hot property of IC chip, reduce impedance and limitation induction reactance, drop
The stress of low substrate and inter-module, component are relatively reliable.
Purpose of the utility model is realized as follows: a kind of silicon wafer encapsulating structure, including silicon wafer, on the silicon chip surface
Distribution is provided with several aluminium pads, and also covering is equipped with silicon wafer sheath on the silicon wafer and aluminium pad, and the thickness of silicon wafer sheath is greater than aluminium pad
Thickness, each aluminium pad is corresponded on silicon wafer sheath and offers several aluminium pad slots, the outer diameter of aluminium pad is greater than the internal diameter of aluminium pad slot, the silicon
Also covering is equipped with using the first insulating protective layer made of polyimides above piece sheath, and the first insulating protective layer downside is integrally set
The lower convexity of insertion aluminium pad slot is installed, first insulating protective layer, which is located above lower convexity, offers windowing slot one, opens
Window slot one is located at the top of aluminium pad, and adherency conductive layer is provided with above first insulating protective layer, and adherency conductive layer includes
Insertion section in windowing slot one and positioned at the upper lateral section of the first insulation protection layer surface, the adherency conductive layer upside is covered
Lid is provided with metal wiring layer, and covering is provided with using polyimides system above first insulating protective layer and metal wiring layer
At the second insulating protective layer, windowing slot two is offered on second insulating protective layer, the metal wiring layer is located at windowing
What the part of two lower section of slot was set as redistributing connects bonding wire road.
The utility model forms a thickness by covering one layer of silicon wafer sheath on the aluminium pad of silicon wafer above silicon wafer sheath
The first uniform insulating protective layer is spent, aluminium pad is successively connected with adherency conductive layer, metal wiring layer, so that metal wiring layer
It is connected with aluminium pad, so that it may re-start wires design in metal wiring layer, the second insulating protective layer is set to metal line
Layer surface, the second insulating protective layer need aperture, expose metal wiring layer and connect solder joint, are used for subsequent encapsulation step, and the second insulation is protected
Sheath plays a protective role.Compared with prior art, bonding wire road is connect the utility model has the beneficial effects that: can rearrange
Contact to IC chip any rational position, it is possible to increase I/O spacing provides biggish convex block area, reduces substrate and component
Between stress, increase the reliability of component, can also make IC chip be suitable for different packaged types, minimize nonrepeatability at
This expense.
Bonding wire road is connect described in as a further improvement of the utility model, and is located at the second insulating protective layer in-plane, is connect
The route corner on bonding wire road is obliquely installed, and the sum of two adjacent angles of route corner are 270 °, and each angle is 120 ° ~
150°.Conventional metals wiring layer uses right angle corner, and extra metallic region removal is connect bonding wire road to be formed by chemical etching
When, etching solution accumulation easily occurs for corner's angle, and etching solution is contacted with bottom metal layers for a long time, and cause etch quantity excessive,
Lead to corner's bottom metal overetch, bottom chamfer is excessive, becomes smaller with lower layer contacts face, in conjunction with insecure, practical conductor wire
Width narrows, and eventually leads to the reduction of IC chip reliability；The metal wiring layer corner of this programme is designed using obtuse angle, avoids immersing
When etching solution, etching solution is deposited in turning angle, solves the problems, such as the route overetch at turning, reinforces metal wiring layer and adherency
The binding force of conductive layer, promotes IC chip reliability, and such design passes through when carrying out the test of JEDEC standard program reliability
Rate is obviously improved.
The silicon wafer sheath is made of titanium nitride, titanium oxide or silica as a further improvement of the utility model,.
The windowing slot one is trapezoidal as a further improvement of the utility model, and the internal diameter for the slot one that opens a window is from top to bottom
Successively decrease setting.This programme, which to adhere to, combines even closer, the knot of metal wiring layer between conductive layer and the first insulating protective layer
Structure is stronger reliable.
The upper lateral section includes being located at a left side for one left and right sides of windowing slot as a further improvement of the utility model,
Side section and right side section.Adherency conductive layer upper lateral section is distributed in windowing one two sides of slot, so that adherency conductive layer and the first insulation protection
Even closer combination between layer.
The adherency conductive layer is made of titanium-tungsten as a further improvement of the utility model, and titanium and tungsten contain
Amount ratio is (0.9 ~ 1.1): 9, the metal wiring layer, which is adopted, to be made of gold.Adhering to conductive layer, mainly there are two functions: first is that working as
Adhesive layer, second is that working as protective layer.It adheres to conductive layer titanium-tungsten and is capable of forming good associativity with aluminium pad, effectively enhance
Bond strength of the metal wiring layer with silicon wafer；In addition gold will form alloy with aluminium under the working environment of high temperature, and then affect
The function of IC chip, and titanium-tungsten can stop gold to form alloy with aluminium.
The two of the purpose of this utility model are to provide a kind of preparation method of silicon wafer encapsulating structure, can quickly prepare silicon
Chip package.
Purpose of the utility model is realized as follows: a kind of preparation method of silicon wafer encapsulating structure, includes the following steps:
(1) several aluminium pads are welded and fixed on silicon chip surface；
(2) also one layer of silicon wafer sheath is fixed in covering on silicon wafer and aluminium pad, and the thickness of silicon wafer sheath is greater than the thickness of aluminium pad,
Then each aluminium pad is corresponded on silicon wafer sheath and opens up several aluminium pad slots, so that the outer diameter of aluminium pad is greater than the internal diameter of aluminium pad slot；
(3) the first insulating protective layer is fixed in covering on silicon wafer sheath and aluminium pad, so that convex under the first insulating protective layer
Rise insertion aluminium pad slot in, the first insulating protective layer successively through exposure and development, solidification and plasma-based processing after, be located at aluminium pad above
Part form trapezoidal windowing slot one, exposed in the middle part of aluminium pad；
(4) secure attachment conductive layer is covered above the first insulating protective layer by sputter, so that adherency conductive layer is embedding
Enter in section insertion windowing slot one；
(5) one layer of eurymeric photoresist layer is covered in adherency conductive layer surface, so that the filling of eurymeric photoresist layer is fallen to adhere to conductive layer
The dovetail groove being embedded in above section, is exposed eurymeric photoresist layer by light shield, and photochemical reaction occurs for eurymeric photoresist layer, then passes through
After development, solidification and plasma-based processing, the linear metal wiring layer slot with turning is formed on eurymeric photoresist layer, so that linear gold
The corner's angle for belonging to wiring layer slot is 120 ° ~ 150 °；
(6) metal wiring layer is embedded in the metal wiring layer slot of eurymeric photoresist layer by plating；
(7) eurymeric photoresist layer is removed, then passes through chemical etching for the adherency conductive layer not below metal wiring layer
Removal；
(8) the second insulating protective layer is fixed in covering above the first insulating protective layer and metal wiring layer, and the second insulation is protected
Sheath successively forms windowing slot two after overexposure, development, solidification, plasma-based processing, the metal line exposed below the slot two that opens a window
What floor as redistributed connects bonding wire road.
The utility model covers one layer of silicon wafer sheath on the aluminium pad of silicon wafer, and it is equal that a layer thickness is formed above silicon wafer sheath
One the first insulating protective layer；The place for needing to form metal line sandwich circuit is exposed and is developed on silicon wafer, is exposed
Part metals connect solder joint and cover adherency conductive layer；The place for needing to form metal line sandwich circuit is exposed and is developed,
And in the region surface deposited metal；It removes extra metallic region to form metal wiring layer by chemical etching；Finally exist
It covers the second insulating protective layer on silicon wafer, and is exposed and develops to the new place for connecing solder joint is needed to form, the gold of exposing
Belong to wiring layer, that is, new connects spot area.Compared with prior art, the utility model has the beneficial effects that: this method can weigh
It is new to arrange to connect solder joint to any rational position of IC chip, keep IC chip more flexible in design；IC core can be improved
The hot property of piece reduces impedance and limitation induction reactance.This method in same metal wiring layer width and in the case where same etch,
Metal wiring layer turning is designed using obtuse angle, and metal wiring layer is more firm in conjunction with lower section adherency conductive layer and the first insulating protective layer
Gu IC chip reliability is higher.
The liquid medicine that chemical etching uses in the step (7) as a further improvement of the utility model, is blocking solution.
The main component of blocking solution is N-Methyl pyrrolidone, quality accounting about 40% ~ 60%；Solvent carrier be sulfone class account for about 30% ~
50%, such as dimethyl sulfoxide；And add amine alkalescent additive.
Detailed description of the invention
Fig. 1 is the top view of the silicon wafer encapsulating structure of the utility model.
Fig. 2 is the enlarged drawing in Fig. 1 at A.
Fig. 3 is cross-sectional view of the silicon wafer encapsulating structure in vertical direction.
Fig. 4 is the structural schematic diagram that the first insulating protective layer is encapsulated on silicon wafer.
Fig. 5 is the structural schematic diagram of encapsulation adherency conductive layer on silicon wafer.
Fig. 6 is the structural schematic diagram that eurymeric photoresist layer is encapsulated on silicon wafer.
Fig. 7 is the structural schematic diagram being exposed by light shield to eurymeric photoresist layer.
Fig. 8 is the structural schematic diagram that metal wiring layer slot is formed on eurymeric photoresist layer.
Fig. 9 is the structural schematic diagram that metal wiring layer is arranged in metal wiring layer slot.
Figure 10 is that will adhere to the structural schematic diagram after conductive layer removes by chemical etching.
Figure 11 is the structural schematic diagram that the second insulating protective layer is encapsulated on silicon wafer.
Figure 12 is the structural schematic diagram that windowing slot two is opened up on the second insulating protective layer.
Figure 13 is the structural schematic diagram that aluminium pad and aluminium pad slot.
Wherein, 1 silicon wafer, 2 aluminium pads, 2a aluminium pad slot, 3 silicon wafer sheaths, 4 first insulating protective layers, 4a lower convexity, 4b windowing slot
One, 5 adherency conductive layers, 5a is embedded in section, and 5b upper lateral section, the left side 5b1 section, the right side 5b2 section, 6 metal wiring layers, 7 second, which insulate, protects
Sheath, 7a windowing slot two, 8 connect bonding wire road, 8a angle, 9 eurymeric photoresist layers, 10 light shields, 11 metal wiring layer slots.
Specific embodiment
It as shown in figures 1-13, is a kind of silicon wafer encapsulating structure, including silicon wafer 1, distribution is provided with several aluminium on 1 surface of silicon wafer
Also covering is equipped with silicon wafer sheath 3 on pad 2, silicon wafer 1 and aluminium pad 2, and the thickness of silicon wafer sheath 3 is greater than the thickness of aluminium pad 2, silicon wafer sheath
Each aluminium pad 2 is corresponded on 3 and offers several aluminium pad slot 2a, and the outer diameter of aluminium pad 2 is greater than the internal diameter of aluminium pad slot 2a, 3 top of silicon wafer sheath
Also covering, which is equipped with, uses the first insulating protective layer 4 made of polyimides, is wholely set on the downside of the first insulating protective layer 4 equipped with embedding
Enter the lower convexity 4a of aluminium pad slot 2a, the first insulating protective layer 4, which is located above lower convexity 4a, offers windowing one 4b of slot, and open a window slot
One 4b is located at the top of aluminium pad 2, and the top of the first insulating protective layer 4 is provided with adherency conductive layer 5, and adherency conductive layer 5 includes position
In the insertion section 5a in windowing one 4b of the slot and upper lateral section 5b positioned at 4 surface of the first insulating protective layer, 5 upside of adherency conductive layer
Covering is provided with metal wiring layer 6, covers and is provided with using polyimides above the first insulating protective layer 4 and metal wiring layer 6
Manufactured second insulating protective layer 7, windowing two 7a of slot is offered on the second insulating protective layer 7, and metal wiring layer 6 is located at windowing slot
What the part below two 7a was set as redistributing connects bonding wire road 8.It connects bonding wire road 8 and is located at 7 in-plane of the second insulating protective layer,
The route corner for connecing bonding wire road 8 is obliquely installed, and the sum of two adjacent angle 8a of route corner are 270 °, and each angle 8a is
120°~150°.Silicon wafer sheath 3 is made of titanium nitride, titanium oxide or silica.One 4b of slot that opens a window is trapezoidal, and open a window one 4b of slot
Internal diameter successively decrease from top to bottom setting.Upper lateral section 5b includes left side section 5b1 and the right side being located at left and right sides of windowing one 4b of slot
Side section 5b2.Adherency conductive layer 5 is made of titanium-tungsten, and the content ratio of titanium and tungsten is (0.9 ~ 1.1): 9, metal wiring layer 6
It adopts and is made of gold.
A kind of preparation method of above-mentioned silicon wafer encapsulating structure, includes the following steps:
(1) several aluminium pads 2 are welded and fixed on 1 surface of silicon wafer；
(2) also one layer of silicon wafer sheath 3 is fixed in covering on silicon wafer 1 and aluminium pad 2, and the thickness of silicon wafer sheath 3 is greater than aluminium pad 2
Then thickness corresponds to each aluminium pad 2 on silicon wafer sheath 3 and opens up several aluminium pad slot 2a, so that the outer diameter of aluminium pad 2 is greater than aluminium and pads slot 2a
Internal diameter；
(3) the first insulating protective layer 4 is fixed in covering on silicon wafer sheath 3 and aluminium pad 2, so that the first insulating protective layer 4
Lower convexity 4a be embedded in aluminium pad slot 2a in, the first insulating protective layer 4 successively through exposure and development, solidification and plasma-based processing after, be located at
The part of 2 top of aluminium pad forms trapezoidal one 4b of windowing slot, exposes in the middle part of aluminium pad 2, as shown in Figure 4；
(4) secure attachment conductive layer 5 is covered above the first insulating protective layer 4 by sputter, so that adherency conductive layer 5
It is embedded in section 5a insertion windowing one 4b of slot, as shown in Figure 5；
(5) such as Fig. 6, cover one layer of eurymeric photoresist layer 9 on adherency 5 surface of conductive layer so that the filling of eurymeric photoresist layer 9 fall it is viscous
Dovetail groove above conductive layer-attached 5 insertion section 5a, such as Fig. 7 are exposed eurymeric photoresist layer 9 by light shield 10, eurymeric photoresist
After photochemical reaction, then developed, solidification and plasma-based processing occur for layer 9, being formed on eurymeric photoresist layer 9 has the linear of turning
Metal wiring layer slot 11, so that the corner angle 8a of linear metal wiring layer slot 11 is 120 ° ~ 150 °, as shown in Figure 8；
(6) metal wiring layer 6 is embedded in the metal wiring layer slot 11 of eurymeric photoresist layer 9 by plating；
(7) eurymeric photoresist layer 9 is removed, as shown in figure 9, then will not be below metal wiring layer 6 by chemical etching
Adherency conductive layer 5 remove, as shown in Figure 10；The liquid medicine that chemical etching uses in step (7) is blocking solution.Blocking solution
Main component is N-Methyl pyrrolidone, quality accounting about 40% ~ 60%；Solvent carrier is that sulfone class accounts for about 30% ~ 50%, such as dimethyl
Sulfoxide；And add amine alkalescent additive；
(8) such as Figure 11, the second insulating protective layer 7 is fixed in covering above the first insulating protective layer 4 and metal wiring layer 6,
Second insulating protective layer 7 successively forms windowing two 7a of slot, the lower section windowing two 7a of slot after overexposure, development, solidification, plasma-based processing
What the metal wiring layer 6 of exposing as redistributed connects bonding wire road 8, as shown in figure 12.
The utility model forms one above silicon wafer sheath 3 by covering one layer of silicon wafer sheath 3 on the aluminium pad 2 of silicon wafer 1
Aluminium pad 2 is successively connected with adherency conductive layer 5, metal wiring layer 6, so that golden by the first uniform insulating protective layer 4 of thickness degree
Belong to wiring layer 6 to be connected with aluminium pad 2, so that it may re-start wires design in metal wiring layer 6, the second insulating protective layer 7 is set
It is placed in 6 surface of metal wiring layer, the second insulating protective layer 7 needs aperture, exposes metal wiring layer 6 and connects solder joint, is used for subsequent encapsulation
Step, the second insulating protective layer 7 play a protective role.Bonding wire road 8 is connect utility model has the advantages that can rearrange
Any rational position of the contact to IC chip, it is possible to increase I/O spacing provides biggish convex block area, reduces substrate and inter-module
Stress, increase the reliability of component, can also make IC chip be suitable for different packaged types, minimize nonrepeatability cost
Expense.The IC chip of the utility model can be more flexible in design；The hot property of IC chip can be improved, reduce impedance
With limitation induction reactance.In the case where same metal wiring layer width and same etch, 6 turning of metal wiring layer uses this method
Obtuse angle design, metal wiring layer 6 adheres to conductive layer 5 with lower section and the first insulating protective layer 4 is combined stronger, IC chip reliability
It is higher.
The utility model is not limited to above-described embodiment, on the basis of technical solution disclosed by the utility model, this
For the technical staff in field according to disclosed technology contents, not needing creative labor can be special to some of which technology
Sign makes some replacements and deformation, these replacements and deformation are within the protection scope of the present utility model.
Claims (6)
1. a kind of silicon wafer encapsulating structure, including silicon wafer, which is characterized in that distribution is provided with several aluminium pads on the silicon chip surface,
Also covering is equipped with silicon wafer sheath on the silicon wafer and aluminium pad, and the thickness of silicon wafer sheath is greater than the thickness of aluminium pad, right on silicon wafer sheath
Each aluminium pad is answered to offer several aluminium pad slots, the outer diameter of aluminium pad is greater than the internal diameter of aluminium pad slot, and also covering is set above the silicon wafer sheath
Have using the first insulating protective layer made of polyimides, the first insulating protective layer downside, which is wholely set, is equipped with insertion aluminium pad slot
Lower convexity, first insulating protective layer, which is located above lower convexity, offers windowing slot one, and windowing slot one is located at the upper of aluminium pad
It is square, adherency conductive layer is provided with above first insulating protective layer, adherency conductive layer includes embedding in windowing slot one
Enter section and the upper lateral section positioned at the first insulation protection layer surface, covering is provided with metal line on the upside of the adherency conductive layer
Covering is provided with using the second insulation protection made of polyimides above layer, first insulating protective layer and metal wiring layer
Layer, windowing slot two is offered on second insulating protective layer, the part that the metal wiring layer is located at two lower section of windowing slot is set
Be set to redistribution connects bonding wire road.
2. a kind of silicon wafer encapsulating structure according to claim 1, which is characterized in that the bonding wire road that connects is positioned at the second insulation
Protective layer in-plane, the route corner for connecing bonding wire road are obliquely installed, and the sum of two adjacent angles of route corner are 270 °,
Each angle is 120 ° ~ 150 °.
3. a kind of silicon wafer encapsulating structure according to claim 1 or 2, which is characterized in that the silicon wafer sheath is using nitridation
Titanium, titanium oxide or silica are made.
4. a kind of silicon wafer encapsulating structure according to claim 1 or 2, which is characterized in that the windowing slot one is trapezoidal, opens
The internal diameter of window slot one successively decreases setting from top to bottom.
5. a kind of silicon wafer encapsulating structure according to claim 1 or 2, which is characterized in that the upper lateral section includes difference position
Left side section and right side section in one left and right sides of windowing slot.
6. a kind of silicon wafer encapsulating structure according to claim 1 or 2, which is characterized in that the adherency conductive layer uses titanium
Tungsten alloy is made, and the content ratio of titanium and tungsten is (0.9 ~ 1.1): 9, the metal wiring layer, which is adopted, to be made of gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920223070.1U CN209312758U (en) | 2019-02-22 | 2019-02-22 | A kind of silicon wafer encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920223070.1U CN209312758U (en) | 2019-02-22 | 2019-02-22 | A kind of silicon wafer encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209312758U true CN209312758U (en) | 2019-08-27 |
Family
ID=67681776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920223070.1U Active CN209312758U (en) | 2019-02-22 | 2019-02-22 | A kind of silicon wafer encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209312758U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109727949A (en) * | 2019-02-22 | 2019-05-07 | 江苏汇成光电有限公司 | A kind of silicon wafer encapsulating structure and preparation method thereof |
-
2019
- 2019-02-22 CN CN201920223070.1U patent/CN209312758U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109727949A (en) * | 2019-02-22 | 2019-05-07 | 江苏汇成光电有限公司 | A kind of silicon wafer encapsulating structure and preparation method thereof |
| CN109727949B (en) * | 2019-02-22 | 2024-04-16 | 江苏汇成光电有限公司 | Silicon chip packaging structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7259448B2 (en) | Die-up ball grid array package with a heat spreader and method for making the same | |
| US7109065B2 (en) | Bumped chip carrier package using lead frame and method for manufacturing the same | |
| US6693349B2 (en) | Semiconductor chip package having a leadframe with a footprint of about the same size as the chip | |
| CN100499104C (en) | Flip chip contact(PCC) power package and package method | |
| US6787923B2 (en) | Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks | |
| US9564387B2 (en) | Semiconductor package having routing traces therein | |
| CN101258609B (en) | Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers | |
| US5708304A (en) | Semiconductor device | |
| WO2008027694A2 (en) | Stackable packages for three-dimensional packaging of semiconductor dice | |
| CN101416308A (en) | Semiconductor die packages using thin dies and metal substrates | |
| TWI404175B (en) | Semiconductor package having electrical connecting structures and fabrication method thereof | |
| US6130477A (en) | Thin enhanced TAB BGA package having improved heat dissipation | |
| EP3577684B1 (en) | Power semiconductor module | |
| WO2008084276A1 (en) | A semiconductor package | |
| WO2004043130A2 (en) | Mechanically enhanced package and method of making same | |
| US6864588B2 (en) | MCM package with bridge connection | |
| TWI227051B (en) | Exposed pad module integrated a passive device therein | |
| US20060226534A1 (en) | Structure and assembly method of integrated circuit package | |
| CN209312758U (en) | A kind of silicon wafer encapsulating structure | |
| US6989295B1 (en) | Method of making a semiconductor package device that includes an insulative housing with first and second housing portions | |
| CN109727949A (en) | A kind of silicon wafer encapsulating structure and preparation method thereof | |
| CN204927283U (en) | Embedded semiconductor package structure of support plate level of improvement | |
| TW457662B (en) | Fabrication method and structure of a chip size package | |
| CN201229938Y (en) | Chip packaging structure | |
| TWI281738B (en) | Structure and assembly method of IC packaging |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |