CN219246675U - Flat pin-free packaging structure - Google Patents

Abstract

The utility model provides a flat leadless packaging structure, which comprises: a substrate disposed at the bottom of the package; the substrate has a multi-layered substrate circuit; a substrate circuit on the upper surface of the substrate, terminal pads arranged on the peripheral edge part, and grounding pads arranged on the central part; the chip power-on end is positioned at the connection of the substrate circuit and the metallized chip; the chip power-on end is correspondingly connected with the terminal bonding pad through wiring and metallization holes of the substrate circuit of each layer; the terminal pad and the ground pad are electrically connected to a lead terminal and a ground terminal provided on the lower surface of the substrate. The utility model can solve the problems of the prior integrated circuit package shell that the internal space layout is tension and the size is bigger, thereby meeting the requirements of miniaturization, integration and high reliability of 6218-2 chips.

Description

Flat pin-free packaging structure

Technical Field

The utility model relates to the technical field of integrated circuit packaging, in particular to a flat pin-free packaging structure.

Background

In recent years, electronic products are being miniaturized and portable, and the market demand is required to increase the density of circuit assembly, which is an important factor for promoting the development of chip packaging technology, and the progress of packaging technology is promoting the forward development of chip technology.

The integrated circuit packaging technology is a technology for packaging integrated circuits, and the quality of the packaging technology directly influences the performance of a chip and the design and manufacture of a PCB connected with the chip, so that the integrated circuit packaging technology is of great importance. However, the existing integrated circuit packaging technology has the problems of shortage of internal space layout, large size of a packaging shell and unstable chip performance.

Disclosure of Invention

In order to solve the technical problems, the utility model provides a flat pin-free packaging structure, which aims to solve the problems of the prior integrated circuit packaging shell that the internal space layout is tension and the size of the packaging shell is bigger, thereby meeting the requirements of miniaturization, integration and high reliability of 6218-2 chips.

In order to achieve the above purpose, the utility model adopts the following technical scheme: provided is a flat leadless package structure, comprising: a substrate arranged at the bottom of the packaging structure; the substrate has a multi-layered substrate circuit; a substrate circuit on the upper surface of the substrate, terminal pads arranged on the peripheral edge part, and grounding pads arranged on the central part; the chip power-on end is positioned at the connection of the substrate circuit and the metallized chip; the chip power-on end is correspondingly connected with the terminal bonding pad through wiring and metallization holes of the substrate circuit of each layer; the terminal pad and the ground pad are electrically connected to a lead terminal and a ground terminal provided on the lower surface of the substrate.

Further, a package material layer is provided under the substrate, and the lead terminal and the ground terminal are exposed from the lower surface of the package material layer, and the lead terminal is exposed from the side of the package material layer.

Further, the height of the lead-out terminal exposed from the side of the sealing material layer is 0.3mm to 0.5mm.

Further, the thickness of the lead-out terminal is 0.2 mm-0.5 mm, and the lead-out terminal extends from the bottom surface of the substrate to the outside to 0.05 mm-0.15 mm beyond the projection edge of the plane of the substrate.

Further, a plurality of welding spots are arranged on the terminal bonding pad and uniformly distributed on the upper surface of the substrate, and the grounding bonding pad is wrapped.

Further, the substrate circuit and the upper and lower metallized holes penetrating through each layer of the substrate circuit form a coaxial-like structure.

Further, the chip power connection end consists of a plurality of special-shaped power connection ends, and the whole chip power connection end is distributed in a shape of a loop and forms a chip placement position with the substrate circuit.

Further, the package structure is applied to a 6218-2 chip.

Compared with the prior art, the technical scheme provided by the utility model has the following beneficial effects: on the substrate, terminal pads are uniformly distributed around the substrate and wrap the grounding pads, and the space of the substrate is reasonably utilized, so that the overall layout of the substrate is more compact; the substrate circuit adopts a miniaturized integrated circuit design, so that the substrate circuit can realize the required electrical properties in a small space; the chip electric connection end is positioned above the substrate circuit, one end of the chip electric connection end penetrates through the substrate circuit through the metallized hole and is correspondingly connected with the terminal bonding pad, the other end of the chip electric connection end is used for connecting a chip, the inner space of the chip substrate packaging shell is reasonably utilized, the required binding wire size is shortened, the inner layout of the chip substrate packaging shell is more compact, and meanwhile the requirement of high reliability is met; the substrate circuit and the upper and lower metallized holes penetrating through each layer of the substrate circuit form a coaxial-like structure, so that the signal transmission required by the coverage of the power connection terminal can be met.

It should be understood that the description in this summary is not intended to limit the critical or essential features of the embodiments of the utility model, nor is it intended to limit the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.

Drawings

The above and other features, advantages and aspects of embodiments of the present utility model will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:

FIGS. 1 to 4 are schematic diagrams showing the layout of the wiring of each layer from top to bottom of the substrate circuit according to the present utility model;

fig. 5 to 7 are perspective views showing interconnections between layers of a substrate circuit according to the present utility model;

fig. 8 is a perspective view of layers of a substrate of a flat leadless package structure according to the present utility model.

Reference numerals in the schematic drawings illustrate:

1 substrate, 2 substrate circuit, 3 terminal pads, 4 ground pads, 5 chip electrical terminals, 6 through holes, 7 first blind holes, 8 second blind holes, 9 ground vias, buried vias 10.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

In addition, the term "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

The utility model aims to provide a chip substrate packaging shell which fully utilizes the internal space of the shell, shortens the connection distance between a bare chip and a substrate, ensures compact internal layout of the shell, meets the miniaturization and integration of a chip and ensures the stability of the performance of the chip.

A flat leadless package structure provided by embodiments of the present utility model is described below with reference to fig. 1 through 8.

The present embodiment is based on a 6218-2 chip, which is a Wire Bonding (WB) chip, in the form of a flat leadless package. Wherein, the liquid crystal display device comprises a liquid crystal display device,

wire bonding refers to bonding the interface of a chip to the interface of a substrate with high purity gold wire after the adhesive between the chip and the substrate is treated to provide better adhesion. The gold wire comprises gold (purity is 99.999%) doped with silver, palladium, magnesium, iron, copper, silicon and other elements. The hardness, rigidity, extensibility, conductivity and other parameters of the gold wires can be changed by doping different elements.

The flat leadless package is an emerging surface-mounted chip packaging technology with small size and small volume of bonding pads and plastic as sealing materials, a large-area exposed bonding pad is arranged at the central position of the bottom of the structure, the heat conduction effect is achieved, and a conductive bonding pad for realizing electrical connection is arranged at the periphery of the package with the large bonding pad.

The flat leadless package of this embodiment, as shown in fig. 8, comprises: a substrate 1 arranged at the bottom of the packaging structure; the substrate 1 has a multilayer substrate circuit 2; a substrate circuit 2 positioned on the upper surface of the substrate 1, wherein terminal pads 3 are provided at peripheral edge portions, and a ground pad 4 is provided at a central portion; the chip power-on terminal 5 is positioned at the connection of the substrate circuit and the metallized chip; the chip electric connection end 5 is correspondingly connected with the terminal bonding pad 3 through wiring and metallization holes of the substrate circuit 2 of each layer; the terminal pad 3 and the ground pad 4 are electrically connected to a lead terminal and a ground terminal provided on the lower surface of the substrate 1. The design can reasonably utilize the internal space of the substrate shell, shorten the required binding wire size, and meet the requirements of miniaturization, integration and high reliability of chips in cooperation with the packaging form of no pins at the bottom.

In the present embodiment, the substrate 1 satisfies the GJB7400 standard.

In this embodiment, the substrate circuit 2 and the metallization holes penetrating the layers of the substrate circuit 2 and connecting up and down form a coaxial-like structure.

In this embodiment, the chip power connection terminal 5 is composed of a plurality of special-shaped power connection terminals, and is distributed in a loop shape integrally, and forms a chip placement position with the substrate circuit 2.

In this embodiment, the package structure is applied to a 6218-2 chip.

Specifically, the connection condition of each layer of the substrate circuit 2 is described with reference to fig. 1 to 8:

FIGS. 1 to 4 are schematic diagrams showing the layout of the wiring of each layer from top to bottom of the substrate circuit according to the present utility model; FIG. 5 to the extent

Fig. 7 is a perspective view of the interconnections between layers of a substrate circuit of the present utility model.

As shown in fig. 1, the electrical terminals of the 6218-2 chip are electrically connected to the electrical terminals 5 of the chips shown in fig. 1 by wire bonding, in this embodiment gold wire bonding.

The first substrate circuit layer shown in fig. 1 and the second substrate circuit layer shown in fig. 2 are electrically connected to the wiring through the metallized holes shown in fig. 5; the second substrate circuit layer shown in fig. 2 and the third substrate circuit layer shown in fig. 3 are electrically connected to the wiring through the metallized holes shown in fig. 6; the third substrate circuit layer shown in fig. 3 and the fourth substrate circuit layer shown in fig. 4 are electrically connected to the wiring through the metallized holes shown in fig. 7.

Fig. 8 is a perspective view of layers of a substrate of a flat leadless package structure according to the present utility model. As shown in fig. 8, the chip terminals 5 are connected to the terminal pads 3 through the wiring and the metallized holes of the substrate circuit 2.

In the present embodiment, the layers of the substrate circuit 2 are electrically connected to the inside of the metallized holes through wirings. Wherein the metallized holes comprise: a through hole 6, a first blind hole 7, a second blind hole 8, a grounding via hole 9 and a buried hole 10. As shown in fig. 8, the through holes 6 penetrate through each layer of the connection substrate circuit 2 and are correspondingly connected with the terminal pads 3; as shown in fig. 5, the first blind hole 7 is electrically connected with the second blind hole 8, the first blind hole 7 connects the upper surface trace of the substrate circuit 2 to the inside of the board connecting circuit 2, and connects the internal trace through the second blind hole 8, and the second blind hole 8 correspondingly connects the terminal pad 3 through the substrate circuit 2.

As shown in fig. 3 and fig. 7, the ground via hole 9 is located in the third substrate circuit layer, and connects the internal wiring of the substrate circuit 2 to the ground pad 4, so as to improve the anti-interference capability of the whole circuit and effectively shorten the total current loop length of the circuit.

As shown in fig. 2, the buried hole 10 is located in the second substrate circuit layer and is responsible for connecting the upper and lower wires, so as to realize electrical connection between the upper and lower layers.

In this embodiment, the electrical terminal of the 6218-2 chip is bonded with the electrical terminal 5 of the substrate circuit 2 through gold wires, and the electrical terminal 5 is electrically connected with the terminal pad 3 and the ground pad 4 through the wiring and the through hole 6, the first blind hole 7, the second blind hole 8, the ground via hole 9 and the buried hole 10; the terminal pad 3 and the ground pad 4 are electrically connected to the lead terminal and the ground terminal through wirings.

In this embodiment, as shown in fig. 8, the substrate circuit 2 is designed as a miniaturized integrated circuit, and the required circuits are integrated. The design can reduce the internal space of the whole structure, and simultaneously, the design is matched with the shortening of the dimension of the binding wire, so that the requirement of high reliability is met while the internal layout of the packaging structure is more compact.

In this embodiment, the package material layer is provided under the substrate, the lead terminals and the ground terminals are exposed from the lower surface of the package material layer, and the lead terminals are exposed from the sides of the package material layer.

In this embodiment, the height of the lead terminals exposed from the side of the sealing material layer is 0.3mm to 0.5mm.

In this embodiment, the thickness of the lead-out terminal is 0.2mm to 0.5mm, and the lead-out terminal extends from the bottom surface of the substrate to the outside by 0.05mm to 0.15mm beyond the projected edge of the substrate plane.

In this embodiment, as shown in fig. 4, a plurality of solder joints are disposed on the terminal pad 3, and are uniformly distributed on the upper surface of the substrate and wrap the bottom grounding pad. The design can reasonably utilize the space of the substrate 1, and achieves the effects of compact layout and miniaturization and integration.

According to the embodiment of the utility model, the following technical effects are achieved:

through the integral design structure, the connection distance between the bare chip and the substrate can be effectively shortened; forming an effective intra-substrate signal transmission structure; the structure layout is compact, the space is fully utilized, and the requirements of miniaturization, integration and high reliability of the chip substrate packaging shell are met.

In the description of the present specification, the terms "connected," "mounted," "secured," and the like are to be construed broadly, and for example, "connected" may be a fixed connection, a removable connection, or an integral connection; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

In the description of the present specification, the terms "one embodiment," "some embodiments," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and variations may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (8)

1. A flat leadless package structure comprising:

a substrate (1) arranged at the bottom of the packaging structure;

the substrate (1) has a multilayer substrate circuit (2);

a substrate circuit (2) located on the upper surface of the substrate (1), wherein terminal pads (3) are provided at peripheral edge portions, and a ground pad (4) is provided at the central portion;

the chip power-on terminal (5) is positioned at the connection of the substrate circuit (2) and the metallized chip;

the chip electric connection end (5) is correspondingly connected with the terminal bonding pad (3) through wiring and metallization holes of the substrate circuit (2) of each layer;

the terminal pad (3) and the ground pad (4) are electrically connected to a lead-out terminal and a ground terminal provided on the lower surface of the substrate (1).

2. The structure of claim 1, wherein,

and a packaging material layer is arranged below the substrate (1), the lead-out terminal and the grounding terminal are exposed from the lower surface of the packaging material layer, and the lead-out terminal is exposed from the side of the packaging material layer.

3. The structure of claim 2, wherein,

the height of the lead-out terminal exposed from the side of the packaging material layer is 0.3 mm-0.5 mm.

4. A structure according to any one of claims 2 to 3, characterized in that,

the length of the lead-out terminal exposed from the bottom of the packaging material layer is 0.2-0.5 mm, and the lead-out terminal extends outwards from the bottom surface of the substrate (1) to 0.05-0.15 mm beyond the plane projection edge of the substrate (1).

5. The structure of claim 1, wherein,

the terminal bonding pad (3) is provided with a plurality of welding spots which are uniformly distributed on the upper surface of the substrate (1) and wrap the grounding bonding pad (4).

6. The structure of claim 1, wherein,

the substrate circuit (2) and the metallization holes penetrating through each layer of the substrate circuit (2) and connecting up and down form a coaxial-like structure.

7. The structure of claim 1, wherein,

the chip power connection end (5) is composed of a plurality of special-shaped power connection ends, is distributed in a loop shape as a whole, and forms a chip placement position with the substrate circuit (2).

8. The structure of claim 1, wherein,

the packaging structure is applied to a 6218-2 chip.

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