CN216849934U - Packaging structure of full-bridge power device - Google Patents
Packaging structure of full-bridge power device Download PDFInfo
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- CN216849934U CN216849934U CN202220375463.6U CN202220375463U CN216849934U CN 216849934 U CN216849934 U CN 216849934U CN 202220375463 U CN202220375463 U CN 202220375463U CN 216849934 U CN216849934 U CN 216849934U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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Abstract
The embodiment of the utility model discloses full-bridge power device's packaging structure. The structure comprises a lead frame, wherein the lead frame comprises m base islands which are sequentially arranged along a first direction; each transistor corresponds to one base island, and each transistor is arranged on the surface of the corresponding base island; the transistor comprises a first transistor group and a second transistor group, wherein the first transistor group comprises m/2 transistors; the second transistor group comprises m/2 transistors; the drains of m/2 transistors in the first transistor group are electrically connected in series; the source electrodes of the m/2 transistors in the first transistor group are respectively electrically connected with the drain electrodes of the m/2 transistors in the second transistor group in a one-to-one correspondence manner; the drains of m/2 transistors in the second transistor group are used as signal output ends; m is an even number greater than or equal to 2. The embodiment of the utility model provides a reduce the printed circuit board area occupied who uses full-bridge power device, improve radiating effect and product uniformity.
Description
Technical Field
The embodiment of the utility model provides a relate to the semiconductor technology field, especially relate to a full-bridge power device's packaging structure.
Background
At present, a plurality of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices are required to be used as a driving control circuit of three-phase working voltage for a direct-current 12V three-phase pump motor control board in the market, and the three-phase working voltage for the operation of a pump and a motor is generated.
In the prior art, a 3pcs MOSFET half-bridge device is generally designed, combined and welded on a printed circuit board to form a full-bridge power control scheme; however, this solution results in large footprint and poor heat dissipation of the printed circuit board; the printed circuit board has complex wiring layout design and poor device consistency.
SUMMERY OF THE UTILITY MODEL
The utility model provides a packaging structure of full-bridge power device to reduce printed circuit board area occupied, improve the radiating effect, reduce the printed circuit board winding displacement layout design degree of difficulty, improve the device uniformity.
The embodiment of the utility model provides a full-bridge power device's packaging structure is provided, this packaging structure includes:
the lead frame comprises m base islands, and the m base islands are sequentially arranged along a first direction;
each transistor corresponds to one base island, and each transistor is arranged on the surface of the corresponding base island;
the transistors include a first transistor group and a second transistor group, the first transistor group including m/2 transistors; the second transistor group comprises m/2 transistors;
the drains of m/2 transistors in the first transistor group are electrically connected in series;
the source electrodes of the m/2 transistors in the first transistor group are respectively and correspondingly electrically connected with the drain electrodes of the m/2 transistors in the second transistor group;
the drains of m/2 transistors in the second transistor group are used as signal output ends; wherein m is an even number greater than or equal to 2.
Optionally, the value of m is 6.
Optionally, m/2 transistors in the second transistor group are not adjacent.
Optionally, the package structure of the full-bridge power device further includes:
m gate connection electrodes which are arranged in an insulating mode are electrically connected with the gates of the m transistors in a one-to-one correspondence mode;
the m gate connection electrodes are disposed in a first region of the lead frame, wherein the first region is located on one side of the base island along a second direction, and the second direction is perpendicular to the first direction.
Optionally, the package structure of the full-bridge power device further includes: m/2 source electrode connecting electrodes, wherein m/2 source electrode connecting electrodes are electrically connected with the source electrodes of the transistors in the second transistor group in a one-to-one correspondence manner;
and m/2 of the source connecting electrodes are arranged in a second area of the lead frame, wherein the first area and the second area are positioned on two sides of the base island along a second direction.
Optionally, the package structure of the full-bridge power device further includes:
m/2 drain electrode connecting electrodes, wherein the m/2 drain electrode connecting electrodes are electrically connected with the drain electrodes of the transistors in the first transistor group in a one-to-one correspondence manner;
m/2 drain connection electrodes are arranged in the second area of the lead frame.
Optionally, the package structure of the full-bridge power device further includes: m/2 output electrodes which are electrically connected with the drain electrodes of the transistors in the second transistor group in a one-to-one correspondence manner;
m/2 output electrodes are arranged on the first area of the lead frame.
Optionally, the packaging structure of the full-bridge power device further comprises a connecting sheet, and the gate connection electrode is electrically connected with the gates of the transistors in the first transistor group and the gates of the transistors in the second transistor group through the connecting sheet; the source electrode connecting electrode is electrically connected with the source electrodes of the transistors in the second transistor group through a connecting sheet; the output electrode is electrically connected with the source electrodes of the transistors in the first transistor group through a connecting sheet.
Optionally, the connecting piece comprises at least one of: welding gold wires, welding copper wires, welding aluminum strips and welding copper sheets.
Optionally, the package structure of the full-bridge power device further comprises an epoxy plastic package layer, and the epoxy plastic package layer is used for plastically packaging the lead frame and the transistor.
The technical scheme of this embodiment is through integrateing a plurality of transistors on a lead frame, has realized the circuit integration with full-bridge power device on a lead frame, when using full-bridge power device, need not to weld a plurality of transistors on printed circuit board again, only need with full-bridge power device's packaging structure weld on printed circuit board can, reduced the printed circuit board's of using full-bridge power device volume, and it is more convenient to make full-bridge power device's printed circuit walk the line. A plurality of transistors are integrated in the same lead frame unit, so that quick heat dissipation is facilitated, and the junction temperature of the device is reduced. A plurality of transistors are highly integrated together, and the product consistency is good. The DFN package is provided with a direct heat dissipation channel for releasing heat in the package, so that the heat dissipation effect of the package structure of the full-bridge power device can be improved, and the heat dissipation effect of the printed circuit board of the full-bridge power device is improved. The technical scheme of the embodiment solves the problems that in the prior art, a plurality of transistors are welded on a printed circuit board, so that the printed circuit board occupies a large area and has poor heat dissipation; the printed circuit board has the advantages that the printed circuit board is complex in flat cable layout design and poor in device consistency, the occupied area of the printed circuit board using the full-bridge power device is reduced, the heat dissipation effect is improved, the flat cable layout design complexity is reduced, and the device consistency is improved.
Drawings
Fig. 1 is a schematic diagram of a package structure of a full-bridge power device according to an embodiment of the present invention;
fig. 2 is a schematic circuit structure diagram of a full-bridge power device corresponding to fig. 1 according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a package structure of another full-bridge power device according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a package structure of another full-bridge power device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures associated with the present invention are shown in the drawings, not all of them.
Fig. 1 is the utility model discloses the implementation provides a packaging structure's of full-bridge power device schematic diagram, and referring to fig. 1, the packaging structure of full-bridge power device includes: the lead frame 100, the lead frame 100 includes m pieces of base islands 101, m pieces of base islands 101 are arranged along the first direction 1 sequentially; m transistors 102, each transistor 102 corresponding to a base island 101, and each transistor 102 disposed on the surface of the corresponding base island 101; the transistor 102 includes a first transistor group 200 and a second transistor group 300, the first transistor group 200 including m/2 transistors 102; the second transistor group 300 includes m/2 transistors 102; the drains of m/2 transistors 102 in the first transistor group 200 are electrically connected in series; the sources 1022 of the m/2 transistors 102 in the first transistor group 200 are respectively electrically connected with the drains of the m/2 transistors 102 in the second transistor group 300 in a one-to-one correspondence manner; the drains of m/2 transistors 102 in the second transistor group 300 are used as signal output terminals; wherein m is an even number greater than or equal to 2.
Specifically, the drains of the 3 transistors 102 of the first transistor group 200 are electrically connected in series, so that the drains of the 3 transistors 102 of the first transistor group 200 are connected to the outside, for example, may be connected to an ac power signal input terminal or a dc signal input terminal.
The drains of the 3 transistors 102 of the first transistor group 200 are located on the surface of the transistors adjacent to the base island 101, and the sources 1022 and gates 1021 of the 3 transistors 102 of the first transistor group 200 are located on the surface of the transistors away from the base island 101. The drains of the 3 transistors 102 of the second transistor group 300 are located on the surface of the transistors adjacent to the base island 101, and the sources 1022 and gates 1021 of the 3 transistors 102 of the second transistor group 300 are located on the surface of the transistors away from the base island 101. The drains of the 3 transistors 102 in the second transistor group 300 are in contact with the surface of the corresponding base island 101, and when the base island 101 can conduct electricity, the sources 1022 of the 3 transistors 102 in the first transistor group 200 are connected to the corresponding base island 101, that is, the sources 1022 of the 3 transistors 102 in the first transistor group 200 are respectively electrically connected to the drains of the 3 transistors 102 in the second transistor group 300 in a one-to-one correspondence manner.
The drains of the 3 transistors 102 in the second transistor group 300 are used as signal output terminals, and may be, for example, a dc power signal output terminal or an ac power signal output terminal, that is, the 3 transistors 102 of the first transistor group 200 and the 3 transistors 102 of the second transistor group 300 convert the drain ac power signal of the 3 transistors 102 of the first transistor group 200 into a dc power signal for output or convert the dc power signal into an ac power signal for output, so as to implement the conversion of the power signal.
Specifically, the full-bridge power device generally includes an upper bridge circuit and a lower bridge circuit, where the upper bridge circuit and the lower bridge circuit correspond to the first transistor group and the second transistor group, respectively, the upper bridge circuit includes m/2 upper bridge arm circuits, the lower bridge circuit includes m/2 lower bridge arm circuits, and a value range of m includes an even number greater than or equal to 2.
Illustratively, m in fig. 1 and 2 may take a value of 6. Fig. 2 is a schematic circuit structure diagram of the full-bridge power device corresponding to fig. 1 provided in the embodiment of the present invention, referring to fig. 2, the full-bridge power device includes an upper bridge arm circuit and a lower bridge arm circuit. The upper bridge arm circuit comprises a first transistor Q1, a second transistor Q2 and a third transistor Q3, wherein the first transistor Q1, the second transistor Q2 and the third transistor Q3 form a first transistor assembly 200; the lower arm circuit includes a fourth transistor Q4, a fifth transistor Q5, and a sixth transistor Q6, and the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor Q6 constitute a second transistor group 300. The gate G1 of the first transistor Q1, the gate G2 of the second transistor Q2, the gate G3 of the third transistor Q3, the gate G4 of the fourth transistor Q4, the gate G5 of the fifth transistor Q5 and the gate G6 of the sixth transistor Q6 are used for connecting control signals; the drain D1 of the first transistor Q1, the drain D2 of the second transistor Q2, and the drain D3 of the third transistor Q3 are electrically connected in series, and are connected to a power supply VCC as an ac signal input terminal, or may also be used as a dc signal input terminal; the source S1 of the first transistor Q1, the source S2 of the second transistor Q2 and the source S3 of the third transistor Q3 are electrically connected with the drain D4 of the fourth transistor Q4, the drain D5 of the fifth transistor Q5 and the drain D6 of the sixth transistor Q6 in a one-to-one correspondence, and the drain D4 of the fourth transistor Q4, the drain D5 of the fifth transistor Q5 and the drain D6 of the sixth transistor Q6 are three signal output terminals, A, B and C in the figure denote three signal output terminals; the source S4 of the fourth transistor Q4, the source S5 of the fifth transistor Q5, and the source S6 of the sixth transistor Q6 are grounded. Fig. 2 shows only one circuit configuration of the full-bridge power device, and is not limited thereto.
In addition, the full-bridge power device is packaged in a Double Flat No-lead (DFN) package, which is a latest electronic packaging process and adopts advanced Double-side or square Flat lead-free packaging. The DFN package has versatility to allow one or more semiconductor devices to be connected within a lead-free package.
The technical scheme of this embodiment is through integrateing a plurality of transistors on a lead frame, has realized the circuit integration with full-bridge power device on a lead frame, when using full-bridge power device, need not to weld a plurality of transistors on printed circuit board again, only need with full-bridge power device's packaging structure weld on printed circuit board can, reduced the printed circuit board's of using full-bridge power device volume, and it is more convenient to make full-bridge power device's printed circuit walk the line. A plurality of transistors are integrated in the same lead frame unit, so that the rapid heat dissipation is facilitated, and the junction temperature of the device is reduced. A plurality of transistors are highly integrated together, and the product consistency is good. The DFN package is provided with a direct heat dissipation channel for releasing heat in the package, so that the heat dissipation effect of the package structure of the full-bridge power device can be improved, and the heat dissipation effect of the printed circuit board of the full-bridge power device is improved. The technical scheme of the embodiment solves the problems that in the prior art, a plurality of transistors are welded on the printed circuit board, so that the printed circuit board occupies a large area and has poor heat dissipation; the printed circuit board has the advantages that the printed circuit board is complex in flat cable layout design and poor in device consistency, the occupied area of the printed circuit board using the full-bridge power device is reduced, the heat dissipation effect is improved, the flat cable layout design complexity is reduced, and the device consistency is improved.
With continuing reference to fig. 1, optionally, m has a value of 6.
Specifically, fig. 1 shows that a full-bridge power device is formed by integrating 6 transistors 102 inside in a DFN package form. The first transistor group 200 of the full-bridge power device comprises 3 transistors 102, and the second transistor group 300 comprises 3 transistors 102; the drains of the 3 transistors 102 in the second transistor group 300 can output three power signals, that is, three-phase electrical signals, which can meet the use requirement of a three-phase motor.
With continued reference to fig. 1, optionally, the m/2 transistors 102 in the second transistor group 300 are not adjacent.
Specifically, the first transistor group 200 includes 3 transistors 102, which are a first transistor Q1, a second transistor Q2, and a third transistor Q3; the second transistor group 300 includes 3 transistors 102; a fourth transistor Q4, a fifth transistor Q5, and a sixth transistor Q6, respectively; the non-adjacency of the 3 transistors 102 in the second transistor group 300 means that the fourth transistor Q4 and the fifth transistor Q5 are separated by the first transistor Q1 and the second transistor Q2, and the fifth transistor Q5 and the sixth transistor Q6 are separated by the third transistor Q3. That is, the transistors 102 arranged in order in the first direction 1 are a fourth transistor Q4, a first transistor Q1, a second transistor Q2, a fifth transistor Q5, a third transistor Q3, and a sixth transistor Q6 in order. It should be noted that the specific position of the transistor 102 can be adjusted according to actual needs, and the embodiment of the present invention does not limit this.
With continuing reference to fig. 1, optionally, the package structure of the full-bridge power device further includes: m gate connection electrodes 401 arranged in an insulated manner, wherein the m gate connection electrodes 401 are electrically connected with the gates 1021 of the m transistors 102 in a one-to-one correspondence manner; the m gate connection electrodes 401 are disposed in a first region of the lead frame 100, wherein the first region is located on one side of the base island 101 along a second direction 2, and the second direction 2 is perpendicular to the first direction 1.
Specifically, the m gate connection electrodes 401 are electrically connected to the gates 1021 of the m transistors 102 in a one-to-one correspondence, so that the gates 1021 of the m transistors 102 can be led out, and the gates 1021 of the m transistors 102 can be electrically connected to other devices.
With continuing reference to fig. 1, optionally, the package structure of the full-bridge power device further includes: m/2 source connection electrodes 402, the m/2 source connection electrodes 402 being electrically connected to the sources 1022 of the transistors 102 in the second transistor group 300 in a one-to-one correspondence; the m/2 source connection electrodes 402 are disposed in a second region of the lead frame 100, wherein the first region and the second region are located on two sides of the base island 101 along the second direction 2.
Specifically, m/2 source connection electrodes 402 are further disposed on the lead frame 100 of the package structure of the full-bridge power device, and the m/2 source connection electrodes 402 are electrically connected to the sources 1022 of the transistors 102 in the second transistor group 300 in a one-to-one correspondence manner, so that the sources 1022 of the transistors 102 in the second transistor group 300 can be led out for connection with other devices, or the sources 1022 of the transistors 102 in the second transistor group 300 are grounded.
It should be noted that each source connection electrode includes two source connection electrode pins that are aggregated together.
With continued reference to fig. 1, optionally, the package structure of the full-bridge power device further includes: m/2 drain connection electrodes 403, the m/2 drain connection electrodes 403 being electrically connected to the drains of the transistors 102 in the first transistor group 200 in a one-to-one correspondence; m/2 drain connection electrodes 403 are disposed in the second region of the lead frame 100.
Specifically, the m/2 drain connection electrodes 403 are electrically connected to the drains of the transistors 102 in the first transistor group 200 in a one-to-one correspondence, so that the drains of the m/2 transistors 102 can be led out, and the drains of the m/2 transistors 102 can be conveniently connected to an external power supply. The drain connection electrode 403 is integrally formed with the base island 101 corresponding to the transistor 102 in the first transistor group 200, so that the manufacturing process is simplified, and the drain of the transistor 102 in the first transistor group 200 is electrically connected to the corresponding base island 101 in a one-to-one correspondence manner without providing a connection line.
It should be noted that each drain connection electrode includes two drain connection electrode leads that are gathered together.
With continuing reference to fig. 1, optionally, the package structure of the full-bridge power device further includes: m/2 output electrodes 404, the output electrodes 404 being electrically connected to the drains of the transistors 102 in the second transistor group 300 in a one-to-one correspondence; m/2 output electrodes 404 are disposed on the first region of the lead frame 100.
Specifically, the output electrodes 404 are electrically connected to the drains of the transistors 102 in the second transistor group 300 in a one-to-one correspondence, so that the signal output from the drains of the transistors 102 in the second transistor group 300 can be output to other devices through the output electrodes 404. The output electrode 404 is integrally formed with the base island 101 corresponding to the transistor 102 in the second transistor group 300, so that the manufacturing process is simplified, and the drains of the transistors 102 in the second transistor group 300 are electrically connected with the corresponding base islands 101 in a one-to-one correspondence manner, without the need of providing a connection line.
It should be noted that each output electrode includes two output electrode pins that are grouped together.
With continued reference to fig. 1, optionally, the package structure of the full-bridge power device further includes a connection pad 405, and the gate connection electrode 401 is electrically connected to the gate 1021 of the transistor 102 in the first transistor group 200 and the gate 1021 of the transistor 102 in the second transistor group 300 through the connection pad 405; the source connection electrode 402 is electrically connected to the sources 1022 of the transistors 102 in the second transistor group 300 via the connection pad 405; the output electrode 404 is electrically connected to the source 1022 of the transistor 102 in the first transistor group 200 via the connection pad 405.
The connecting sheet 405 has a heat conducting function, and can enhance the heat dissipation effect of the packaging structure of the full-bridge power device.
With continued reference to fig. 1, optionally, the connecting tab 405 includes at least one of: welding gold wires, welding copper wires, welding aluminum strips and welding copper sheets.
Fig. 3 is a schematic diagram of another full-bridge power device package structure provided by an embodiment of the present invention, referring to fig. 3, optionally, the full-bridge power device package structure further includes an epoxy molding compound layer 500, and the epoxy molding compound layer 500 is used for molding the lead frame and the transistor.
Specifically, the epoxy molding layer 500 is formed by epoxy resin, and the epoxy molding layer 500 can protect the package structure of the full-bridge power device from being damaged during transportation. After the epoxy resin is used for forming the epoxy plastic package layer 500, the redundant epoxy plastic package layer 500 can be removed in a cutting mode, so that the grid electrode connecting electrode 401, the source electrode connecting electrode 402, the drain electrode connecting electrode 403 and the output electrode 404 can be exposed, the connection with other devices is facilitated, the rapid heat dissipation is facilitated, and the temperature of the packaging structure of the full-bridge power device is favorably reduced.
Fig. 4 is a schematic diagram of another full-bridge power device package structure provided by an embodiment of the present invention, referring to fig. 4, the lead frame of the full-bridge power device package structure is etched, and may be filled with an epoxy molding layer after etching, for example, the thickness of the filling may be 0.2mm, the thickness of the full-bridge power device package structure may be 1mm, the etched lead frame is shown in fig. 4, a blank area in fig. 4 is a portion that needs to be etched away, and a black area is a portion that needs to be retained.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.
Claims (10)
1. A packaging structure of a full-bridge power device is characterized by comprising:
the lead frame comprises m base islands, wherein the m base islands are sequentially arranged along a first direction;
each transistor corresponds to one base island, and each transistor is arranged on the surface of the corresponding base island;
the transistors include a first transistor group and a second transistor group, the first transistor group including m/2 transistors; the second transistor group comprises m/2 transistors;
the drains of m/2 transistors in the first transistor group are electrically connected in series;
the source electrodes of m/2 transistors in the first transistor group are electrically connected with the drain electrodes of m/2 transistors in the second transistor group in a one-to-one correspondence manner;
the drains of m/2 transistors in the second transistor group are used as signal output ends; wherein m is an even number greater than or equal to 2.
2. The package structure of the full-bridge power device according to claim 1, wherein m is 6.
3. The package structure of the full-bridge power device according to claim 1, wherein m/2 transistors in the second transistor group are not adjacent.
4. The package structure of the full-bridge power device according to claim 1, further comprising:
m grid connecting electrodes which are arranged in an insulating mode are electrically connected with the grids of the m transistors in a one-to-one correspondence mode;
the m gate connection electrodes are disposed in a first region of the lead frame, wherein the first region is located on one side of the base island along a second direction, and the second direction is perpendicular to the first direction.
5. The package structure of the full-bridge power device according to claim 4, further comprising: m/2 source electrode connecting electrodes, wherein m/2 source electrode connecting electrodes are electrically connected with the source electrodes of the transistors in the second transistor group in a one-to-one correspondence manner;
and m/2 of the source connecting electrodes are arranged in a second area of the lead frame, wherein the first area and the second area are positioned on two sides of the base island along the second direction.
6. The package structure of the full-bridge power device according to claim 5, further comprising:
m/2 drain electrode connecting electrodes, wherein the m/2 drain electrode connecting electrodes are electrically connected with the drain electrodes of the transistors in the first transistor group in a one-to-one correspondence manner;
m/2 of the drain connection electrodes are disposed in the second region of the lead frame.
7. The package structure of the full-bridge power device according to claim 6, further comprising: m/2 output electrodes which are electrically connected with the drain electrodes of the transistors in the second transistor group in a one-to-one correspondence manner;
m/2 output electrodes are arranged on the first area of the lead frame.
8. The package structure of the full-bridge power device according to claim 7, further comprising a connecting pad, wherein the gate connecting electrode is electrically connected with the gates of the transistors in the first transistor group and the gates of the transistors in the second transistor group through the connecting pad; the source electrode connecting electrode is electrically connected with the source electrodes of the transistors in the second transistor group through a connecting sheet; the output electrode is electrically connected with the source electrodes of the transistors in the first transistor group through a connecting sheet.
9. The package structure of the full-bridge power device according to claim 8, wherein the connecting pad comprises at least one of the following: welding gold wires, welding copper wires, welding aluminum strips and welding copper sheets.
10. The package structure of the full-bridge power device according to claim 1, further comprising an epoxy molding compound layer, wherein the epoxy molding compound layer is used for molding the lead frame and the transistor in a plastic manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220375463.6U CN216849934U (en) | 2022-02-23 | 2022-02-23 | Packaging structure of full-bridge power device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202220375463.6U CN216849934U (en) | 2022-02-23 | 2022-02-23 | Packaging structure of full-bridge power device |
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| CN216849934U true CN216849934U (en) | 2022-06-28 |
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Address after: Room 608, 6th Floor, No. 39 Yonghe Road, Yuzui Town, Jiangbei District, Chongqing 400020 Patentee after: Chongqing Yuntong Technology Co.,Ltd. Address before: 518000 Room 401, building 1, xiehechang District B, No. 5, Baodong Road, xiuxin community, Kengzi street, Pingshan District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Yuntong Technology Co.,Ltd. |