JP2012089794A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2012089794A
JP2012089794A JP2010237488A JP2010237488A JP2012089794A JP 2012089794 A JP2012089794 A JP 2012089794A JP 2010237488 A JP2010237488 A JP 2010237488A JP 2010237488 A JP2010237488 A JP 2010237488A JP 2012089794 A JP2012089794 A JP 2012089794A
Authority
JP
Japan
Prior art keywords
power semiconductor
lead frame
semiconductor elements
elements
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010237488A
Other languages
Japanese (ja)
Inventor
Seiki Sakata
世紀 坂田
Kazuo Kayano
和夫 榧野
Sachikazu Suzuki
祥和 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Industries Corp
Toyota Motor Corp
Original Assignee
Toyota Industries Corp
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Industries Corp, Toyota Motor Corp filed Critical Toyota Industries Corp
Priority to JP2010237488A priority Critical patent/JP2012089794A/en
Publication of JP2012089794A publication Critical patent/JP2012089794A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing the number of components, performing the mounting process easily, and realizing high output.SOLUTION: In an inverter device 20 serving as a power semiconductor module, modularization is performed on power semiconductor devices 21a to 21c and 22a to 22c constituting a three-phase inverter circuit and serving as six switching elements. The inverter device 20 is formed by performing wiring connection between power semiconductor devices 21a to 21c and 22a to 22c using one piece of a lead frame 28, and in each of the power semiconductor devices 21a to 21c and 22a to 22c, a surface opposite to a surface connected to the lead frame 28 is connected to heat spreaders 23a and 23b made of a conductive material.

Description

本発明は、半導体装置に係り、詳しくは交流モータの駆動回路、交流電源装置等に使用される3相インバータ回路を構成する6個のスイッチング素子がモジュール化された半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which six switching elements constituting a three-phase inverter circuit used in an AC motor drive circuit, an AC power supply device and the like are modularized.

この種の半導体装置として、図6に示す構成のものが提案されている(特許文献1参照。)。半導体装置は、複数の第1、第2、第3リードを有する外部リードフレーム50a,50b,50cを有し、外部リードフレーム50a上にパワー半導体素子52、制御半導体素子53及びダイオード54の一方の面の電極が半田で接続されている。パワー半導体素子52及びダイオード54の他方の面に形成された電極と、複数の第3リードの内の1つのリードとは第1の内部リードフレーム51aで接続され、制御半導体素子53の他方の面に形成された電極と、複数の第3リードの内の他の1つのリードとは第2の内部リードフレーム51bで接続されている。そして、パワー半導体素子52、制御半導体素子53、ダイオード54、内部リードフレーム51a,51b及び外部リードフレーム50a,50b,50cのリードは封止樹脂55でモールドされている。   As this type of semiconductor device, a semiconductor device having the structure shown in FIG. 6 has been proposed (see Patent Document 1). The semiconductor device has external lead frames 50a, 50b, 50c having a plurality of first, second, and third leads, and one of a power semiconductor element 52, a control semiconductor element 53, and a diode 54 is provided on the external lead frame 50a. The surface electrodes are connected by solder. The electrode formed on the other surface of the power semiconductor element 52 and the diode 54 and one lead of the plurality of third leads are connected by the first internal lead frame 51a, and the other surface of the control semiconductor element 53 is connected. The electrode formed on the second lead and the other lead of the plurality of third leads are connected by a second internal lead frame 51b. The leads of the power semiconductor element 52, the control semiconductor element 53, the diode 54, the internal lead frames 51a and 51b, and the external lead frames 50a, 50b, and 50c are molded with a sealing resin 55.

特開2001−291823号公報JP 2001-291823 A

ところが、特許文献1に記載の半導体装置では、素子間の配線接続を複数の内部リードフレームで行う構成のため、部品点数が多くなる。また、素子の他の面の放熱は、内部リードフレームが外部リードフレームに電気的に接続されている部分を介して行われる構成のため、放熱効果が低く、例えば、電気自動車の走行モータ駆動用のインバータのように高出力のパワー半導体素子を用いる半導体装置の場合、放熱が不十分になる。   However, in the semiconductor device described in Patent Document 1, the number of parts is increased because the wiring connection between elements is performed by a plurality of internal lead frames. In addition, heat dissipation on the other surface of the element is performed through a portion in which the internal lead frame is electrically connected to the external lead frame, so that the heat dissipation effect is low, for example, for driving a traveling motor of an electric vehicle. In the case of a semiconductor device using a high-power power semiconductor element such as an inverter, heat dissipation is insufficient.

本発明は、前記の問題に鑑みてなされたものであって、その目的は、部品点数を少なくでき、実装工程を簡単にできるとともに、より高出力を図ることが可能になる半導体装置を提供することにある。   The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device that can reduce the number of components, simplify the mounting process, and achieve higher output. There is.

前記の目的を達成するため、請求項1に記載の発明は、3相インバータ回路を構成する6個のスイッチング素子としてのパワー半導体素子がモジュール化された半導体装置であって、前記各パワー半導体素子間の配線接続を1枚のリードフレームで行うことにより形成され、前記各パワー半導体素子は前記リードフレームに接続される側の面と反対側の面が導電材製のヒートスプレッダに接続されている。ここで、「1枚のリードフレームで行うことにより形成され」とは、製造工程においてパワー半導体素子が樹脂モールドされるまではリードフレームが1枚の状態にあり、樹脂モールドされた後、各リード端子に切断されることを意味する。   In order to achieve the above object, the invention described in claim 1 is a semiconductor device in which power semiconductor elements as six switching elements constituting a three-phase inverter circuit are modularized, and each of the power semiconductor elements The power semiconductor elements are formed by performing a wiring connection between them, and each power semiconductor element has a surface opposite to a surface connected to the lead frame connected to a heat spreader made of a conductive material. Here, “formed by performing with one lead frame” means that the lead frame is in a single state until the power semiconductor element is resin-molded in the manufacturing process. It means that the terminal is disconnected.

この発明では、6個のパワー半導体素子間の配線接続が1枚のリードフレームで行うことにより形成されるため、パワー半導体素子間の配線接続に必要な部品点数が少なくなり、実装工程が簡単になる。また、各パワー半導体素子は前記リードフレームに接続される側の面と反対側の面が導電材製のヒートスプレッダに接続されているため、半導体装置の放熱性能が高くなり、より高出力を図ることが可能になる。   In the present invention, since the wiring connection between the six power semiconductor elements is formed by one lead frame, the number of parts required for the wiring connection between the power semiconductor elements is reduced, and the mounting process is simplified. Become. In addition, since each power semiconductor element has a surface opposite to the surface connected to the lead frame connected to a heat spreader made of a conductive material, the heat dissipation performance of the semiconductor device is improved, and higher output is achieved. Is possible.

本発明によれば、部品点数を少なくでき、実装工程を簡単にできるとともに、より高出力を図ることが可能になる半導体装置を提供することができる。   According to the present invention, it is possible to provide a semiconductor device in which the number of components can be reduced, the mounting process can be simplified, and higher output can be achieved.

(a)は一実施形態の半導体装置の樹脂モールドする前の平面図、(b)は(a)のA−A線に対応する位置で切断した樹脂モールド、タイバーカット後の半導体装置の断面図、(c)は同じく(a)のB−B線に対応する位置で切断した断面図。(A) is a top view before resin molding of the semiconductor device of one Embodiment, (b) is a resin mold cut | disconnected in the position corresponding to the AA line of (a), Sectional drawing of the semiconductor device after a tie bar cut (C) is sectional drawing similarly cut | disconnected in the position corresponding to the BB line of (a). 3相インバータの回路図。The circuit diagram of a three-phase inverter. リードフレームの平面図。The top view of a lead frame. 樹脂モールド、タイバーカット後の半導体装置の平面図。The top view of the semiconductor device after a resin mold and a tie bar cut. (a)は別の実施形態の半導体装置の図1(b)に対応する断面図,(b)は同じく図1(c)に対応する断面図。(A) is sectional drawing corresponding to FIG.1 (b) of the semiconductor device of another embodiment, (b) is sectional drawing corresponding to FIG.1 (c) similarly. 従来技術の断面図。Sectional drawing of a prior art.

以下、本発明を具体化した半導体装置(パワー半導体モジュール)の一実施形態を図1〜図4にしたがって説明する。
先ずインバータ回路の構成を説明する。図2に示すように、インバータ回路11は、6個のスイッチング素子Q1〜Q6を有し、各スイッチング素子Q1〜Q6には、パワー半導体素子が使用される。この実施形態では各スイッチング素子Q1〜Q6としてIGBT(絶縁ゲートバイポーラ型トランジスタ)が使用されている。インバータ回路11は、第1及び第2のスイッチング素子Q1,Q2、第3及び第4のスイッチング素子Q3,Q4、第5及び第6のスイッチング素子Q5,Q6がそれぞれ直列に接続されている。各スイッチング素子Q1〜Q6のコレクタとエミッタ間には、ダイオードDが、逆並列に、即ちカソードがコレクタにアノードがエミッタに対応する状態に接続されている。第1、第3及び第5のスイッチング素子Q1,Q3,Q5とダイオードDの組はそれぞれ上アームと呼ばれ、第2、第4及び第6のスイッチング素子Q2,Q4,Q6とダイオードDの組はそれぞれ下アームと呼ばれる。
Hereinafter, an embodiment of a semiconductor device (power semiconductor module) embodying the present invention will be described with reference to FIGS.
First, the configuration of the inverter circuit will be described. As shown in FIG. 2, the inverter circuit 11 has six switching elements Q1 to Q6, and a power semiconductor element is used for each switching element Q1 to Q6. In this embodiment, IGBTs (insulated gate bipolar transistors) are used as the switching elements Q1 to Q6. In the inverter circuit 11, first and second switching elements Q1 and Q2, third and fourth switching elements Q3 and Q4, and fifth and sixth switching elements Q5 and Q6 are connected in series, respectively. Between the collectors and emitters of the switching elements Q1 to Q6, a diode D is connected in antiparallel, that is, in a state where the cathode corresponds to the collector and the anode corresponds to the emitter. A set of the first, third and fifth switching elements Q1, Q3, Q5 and the diode D is called an upper arm, respectively, and a set of the second, fourth and sixth switching elements Q2, Q4, Q6 and the diode D is called an upper arm. Are each called the lower arm.

スイッチング素子Q1,Q3,Q5のコレクタがそれぞれ配線12を介して直流電源13のプラス端子に接続され、スイッチング素子Q2,Q4,Q6のエミッタがそれぞれ配線14を介して直流電源13のマイナス端子に接続される。スイッチング素子Q1,Q2の間の接合点は3相モータ15のU相端子Uに、スイッチング素子Q3,Q4の間の接合点は3相モータ15のV相端子Vに、スイッチング素子Q5,Q6の間の接合点は3相モータ15のW相端子Wに、それぞれ接続される。   The collectors of switching elements Q1, Q3, and Q5 are connected to the positive terminal of DC power supply 13 through wiring 12, respectively, and the emitters of switching elements Q2, Q4, and Q6 are connected to the negative terminal of DC power supply 13 through wiring 14, respectively. Is done. The junction between the switching elements Q1 and Q2 is at the U-phase terminal U of the three-phase motor 15, the junction between the switching elements Q3 and Q4 is at the V-phase terminal V of the three-phase motor 15, and the switching elements Q5 and Q6. The junction point between them is connected to the W-phase terminal W of the three-phase motor 15.

次にパワー半導体モジュールとしてのインバータ装置20の構造を説明する。図1(a)に示すように、インバータ装置20は、6個のパワー半導体素子21a,21b,21c,22a,22b,22cを有し、図1(a)において下側の3個のパワー半導体素子21a,21b,21cが図2のインバータ回路11の上アームを構成し、上側の3個のパワー半導体素子22a,22b,22cが下アームを構成する。このパワー半導体素子21a〜21c,22a〜22cは、それぞれ1個のスイッチング素子(IGBT)及び1個のダイオードが一つのデバイスとして組み込まれており、素子の一方の面にはゲート電極およびエミッタ電極が設けられ、他方の面にはコレクタ電極が設けられている。   Next, the structure of the inverter device 20 as a power semiconductor module will be described. As shown in FIG. 1A, the inverter device 20 has six power semiconductor elements 21a, 21b, 21c, 22a, 22b, and 22c, and the lower three power semiconductors in FIG. The elements 21a, 21b, and 21c constitute the upper arm of the inverter circuit 11 of FIG. 2, and the upper three power semiconductor elements 22a, 22b, and 22c constitute the lower arm. Each of the power semiconductor elements 21a to 21c and 22a to 22c includes one switching element (IGBT) and one diode as one device, and a gate electrode and an emitter electrode are formed on one surface of the element. A collector electrode is provided on the other surface.

図1(a),(b),(c)に示すように、上アームを構成する各パワー半導体素子21a〜21cは、1個のヒートスプレッダ23a上に他方の面(コレクタ電極側)が半田24を介して電気的に接続されている。また、下アームを構成する各パワー半導体素子22a〜22cは、それぞれ独立したヒートスプレッダ23b上に他方の面(コレクタ電極側)が半田24を介して電気的に接続されている。ヒートスプレッダ23a,23bは、導電材製(例えば、銅製)で、後記するリードフレームより厚く形成されている。   As shown in FIGS. 1A, 1B, and 1C, each of the power semiconductor elements 21a to 21c constituting the upper arm has a solder 24 on the other surface (collector electrode side) on one heat spreader 23a. It is electrically connected via. The power semiconductor elements 22 a to 22 c constituting the lower arm are electrically connected to the other surface (collector electrode side) via solder 24 on independent heat spreaders 23 b. The heat spreaders 23a and 23b are made of a conductive material (for example, made of copper) and are formed thicker than a lead frame described later.

図1(c)に示すように、上アーム用のヒートスプレッダ23aのパワー半導体素子21a〜21cが接続された面上には、正極用配線部25の先端が半田24を介して電気的に接続されている。正極用配線部25は、ヒートスプレッダ23aの長手方向(パワー半導体素子21a〜21cの配列方向)と直交する方向に延び、かつその先端側にヒートスプレッダ23aに近づくように屈曲形成された屈曲部25aを有し、屈曲部25aにおいてヒートスプレッダ23aに接続されている。   As shown in FIG. 1C, the tip of the positive electrode wiring portion 25 is electrically connected via a solder 24 on the surface of the upper arm heat spreader 23 a to which the power semiconductor elements 21 a to 21 c are connected. ing. The positive electrode wiring portion 25 has a bent portion 25a that extends in a direction orthogonal to the longitudinal direction of the heat spreader 23a (the arrangement direction of the power semiconductor elements 21a to 21c) and is bent to approach the heat spreader 23a at the tip side. The bent portion 25a is connected to the heat spreader 23a.

下アーム用のパワー半導体素子22a〜22cの一方の面(エミッタ電極側)は、それぞれ負極用配線部26に半田24を介して電気的に接続されている。負極用配線部26は、3個のパワー半導体素子22a〜22cの配列方向に対して平行に延びる部分と、直交する方向に延びる部分とを有し、直交する方向に延びる部分の一端側が端子部26bとなるように形成されている。   One surface (emitter electrode side) of the power semiconductor elements 22 a to 22 c for the lower arm is electrically connected to the negative electrode wiring portion 26 via the solder 24. The negative electrode wiring portion 26 has a portion extending in parallel with the arrangement direction of the three power semiconductor elements 22a to 22c and a portion extending in the orthogonal direction, and one end side of the portion extending in the orthogonal direction is a terminal portion. 26b.

上アームを構成するパワー半導体素子21aの一方の面は、U相用電極部27Uの中間部に半田24を介して電気的に接続されている。パワー半導体素子21bの一方の面は、V相用電極部27Vの中間部に、パワー半導体素子21cの一方の面は、W相用電極部27Wの中間部に、それぞれ半田24を介して電気的に接続されている。U相用電極部27U、V相用電極部27V、W相用電極部27Wは、それぞれ先端側がヒートスプレッダ23bに近づくように屈曲形成された屈曲部27aを有し、屈曲部27aがヒートスプレッダ23bにそれぞれ半田24を介して電気的に接続されている。   One surface of the power semiconductor element 21a constituting the upper arm is electrically connected to an intermediate portion of the U-phase electrode portion 27U via the solder 24. One surface of the power semiconductor element 21b is electrically connected to the intermediate portion of the V-phase electrode portion 27V, and one surface of the power semiconductor element 21c is electrically connected to the intermediate portion of the W-phase electrode portion 27W via the solder 24, respectively. It is connected to the. The U-phase electrode portion 27U, the V-phase electrode portion 27V, and the W-phase electrode portion 27W each have a bent portion 27a that is bent so that the tip side approaches the heat spreader 23b, and the bent portion 27a is provided on the heat spreader 23b. Electrical connection is made via solder 24.

図1(a)及び図3に示すように、正極用配線部25、負極用配線部26、U相用電極部27U、V相用電極部27V及びW相用電極部27Wは、1枚のリードフレーム28で形成されている。リードフレーム28には信号端子29が各パワー半導体素子21a〜21c,22a〜22cと対応する箇所にそれぞれ3個ずつ形成されており、図1(a)に示すように、各パワー半導体素子21a〜21c,22a〜22cと信号端子29とは信号配線30で電気的に接続されている。   As shown in FIG. 1A and FIG. 3, the positive electrode wiring portion 25, the negative electrode wiring portion 26, the U-phase electrode portion 27U, the V-phase electrode portion 27V, and the W-phase electrode portion 27W The lead frame 28 is formed. Three signal terminals 29 are formed on the lead frame 28 at locations corresponding to the power semiconductor elements 21a to 21c and 22a to 22c, respectively. As shown in FIG. 21c, 22a-22c and the signal terminal 29 are electrically connected by a signal wiring 30.

パワー半導体素子21a〜21c,22a〜22c、ヒートスプレッダ23a,23b、正極用配線部25、負極用配線部26、U相用電極部27U、V相用電極部27V及びW相用電極部27W及び信号配線30は、封止樹脂31でモールドされている。図4に示すように、封止樹脂31からは正極用配線部25及び負極用配線部26の端子部25b,26bと、U相用電極部27U、V相用電極部27V、W相用電極部27W及び信号端子29の一部とが突出している。また、図1(b),(c)に示すように、ヒートスプレッダ23a,23bのパワー半導体素子21a〜21c,22a〜22cが接続された面と反対側の面は封止樹脂31から露出している。   Power semiconductor elements 21a to 21c, 22a to 22c, heat spreaders 23a and 23b, positive electrode wiring part 25, negative electrode wiring part 26, U phase electrode part 27U, V phase electrode part 27V and W phase electrode part 27W and signals The wiring 30 is molded with a sealing resin 31. As shown in FIG. 4, from the sealing resin 31, the terminal portions 25b and 26b of the positive electrode wiring portion 25 and the negative electrode wiring portion 26, the U phase electrode portion 27U, the V phase electrode portion 27V, and the W phase electrode. The part 27W and a part of the signal terminal 29 protrude. Further, as shown in FIGS. 1B and 1C, the surface of the heat spreaders 23a and 23b opposite to the surface to which the power semiconductor elements 21a to 21c and 22a to 22c are connected is exposed from the sealing resin 31. Yes.

前記のように構成されたインバータ装置20の製造方法の一例を挙げると、先ず、位置決め治具を用いて位置決めしたヒートスプレッダ23a,23b上に、パワー半導体素子21a〜21c,22a〜22cをシート半田が介在する状態で配置し、その上にシート半田が介在する状態でリードフレーム28を載置する。そして、加熱炉内でシート半田を溶融させて、パワー半導体素子21a〜21c,22a〜22c、ヒートスプレッダ23a,23b及びリードフレーム28を位置決めされた所定の位置関係で半田24により電気的に接続する。   An example of a method of manufacturing the inverter device 20 configured as described above is as follows. First, the sheet semiconductors are placed on the power semiconductor elements 21a to 21c and 22a to 22c on the heat spreaders 23a and 23b positioned using a positioning jig. The lead frame 28 is placed with the sheet solder interposed therebetween. Then, the sheet solder is melted in the heating furnace, and the power semiconductor elements 21a to 21c, 22a to 22c, the heat spreaders 23a and 23b, and the lead frame 28 are electrically connected by the solder 24 in a predetermined positional relationship.

次にパワー半導体素子21a〜21c,22a〜22cと信号端子29とを信号配線30で接続する。この作業は、例えばワイヤボンディングで行われる。半田付けが完了した状態では、図1(a)に示すように、ヒートスプレッダ23a,23bの上にパワー半導体素子21a〜21c,22a〜22cが位置し、リードフレームが一番上に位置する状態にある。即ち、リードフレーム28上にパワー半導体素子21a〜21c,22a〜22c及びヒートスプレッダ23a,23bの順に載置した状態で半田付けを行う場合と異なり、半田付け後にヒートスプレッダ23a,23bが下側に位置するように裏返す作業を行わずに、各パワー半導体素子21a等と信号端子29とを信号配線30で接続することができる。   Next, the power semiconductor elements 21 a to 21 c and 22 a to 22 c and the signal terminal 29 are connected by the signal wiring 30. This operation is performed by wire bonding, for example. When the soldering is completed, as shown in FIG. 1A, the power semiconductor elements 21a to 21c and 22a to 22c are positioned on the heat spreaders 23a and 23b, and the lead frame is positioned on the top. is there. That is, unlike the case where soldering is performed in a state where the power semiconductor elements 21a to 21c, 22a to 22c and the heat spreaders 23a and 23b are placed in this order on the lead frame 28, the heat spreaders 23a and 23b are positioned on the lower side after soldering. Thus, the power semiconductor elements 21 a and the like and the signal terminals 29 can be connected by the signal wirings 30 without performing the work of turning them over.

次にパワー半導体素子21a〜21c,22a〜22c及びヒートスプレッダ23a,23bが半田付けされたリードフレーム28を樹脂モールド金型にセットして、樹脂モールドを行った後、リードフレーム28のタイバーをカットするとインバータ装置20が完成する。即ち、インバータ装置20は、各パワー半導体素子21a〜21c,22a〜22c間の配線接続を1枚のリードフレーム28で行うことにより形成され、各パワー半導体素子21a〜21c,22a〜22cは、リードフレーム28に接続される側の面と反対側の面が導電材製のヒートスプレッダ23a,23bに接続されている。   Next, the lead frame 28 to which the power semiconductor elements 21a to 21c, 22a to 22c and the heat spreaders 23a and 23b are soldered is set in a resin mold, and after resin molding, the tie bar of the lead frame 28 is cut. The inverter device 20 is completed. That is, the inverter device 20 is formed by performing wiring connection between the power semiconductor elements 21a to 21c and 22a to 22c with one lead frame 28, and the power semiconductor elements 21a to 21c and 22a to 22c are connected to leads. A surface opposite to the surface connected to the frame 28 is connected to heat spreaders 23a and 23b made of a conductive material.

次に前記のように構成されたインバータ装置20の作用を説明する。
インバータ装置20は、例えば、3相モータ駆動用電源装置の一部を構成するものとして使用される。インバータ装置20は、正極用配線部25の端子部25bが直流電源のプラス端子に、負極用配線部26の端子部26bが直流電源のマイナス端子にそれぞれ接続され、U相用電極部27U、V相用電極部27V及びW相用電極部27Wがモータに接続され、信号端子29が制御装置(図示せず)に接続された状態で使用される。
Next, the operation of the inverter device 20 configured as described above will be described.
The inverter device 20 is used, for example, as a part of a three-phase motor driving power supply device. In the inverter device 20, the terminal portion 25 b of the positive electrode wiring portion 25 is connected to the positive terminal of the DC power source, and the terminal portion 26 b of the negative electrode wiring portion 26 is connected to the negative terminal of the DC power source, respectively. The phase electrode unit 27V and the W phase electrode unit 27W are connected to the motor, and the signal terminal 29 is used in a state of being connected to a control device (not shown).

上アームのスイッチング素子Q1,Q3,Q5及び下アームのスイッチング素子Q2,Q4,Q6がそれぞれ所定周期でオン、オフ制御されることによりモータに交流が供給されてモータが駆動される。制御装置は負荷の要求に応じて電力を供給するように各スイッチング素子Q1〜Q6、即ちパワー半導体素子21a〜21c,22a〜22cを制御する。パワー半導体素子21a〜21c,22a〜22cがスイッチング駆動されると、パワー半導体素子21a〜21c,22a〜22cから熱が発生する。発生した熱は、主にヒートスプレッダ23a,23bを介して放熱される。   The upper arm switching elements Q1, Q3, and Q5 and the lower arm switching elements Q2, Q4, and Q6 are turned on and off at predetermined intervals, respectively, so that alternating current is supplied to the motor to drive the motor. The control device controls each of the switching elements Q1 to Q6, that is, the power semiconductor elements 21a to 21c and 22a to 22c so as to supply electric power according to the demand of the load. When the power semiconductor elements 21a to 21c and 22a to 22c are switched, heat is generated from the power semiconductor elements 21a to 21c and 22a to 22c. The generated heat is radiated mainly through the heat spreaders 23a and 23b.

この実施形態によれば、以下に示す効果を得ることができる。
(1)半導体装置としてのインバータ装置20は、3相インバータ回路を構成する6個のスイッチング素子としてのパワー半導体素子21a〜21c,22a〜22cがモジュール化されている。そして、各パワー半導体素子21a〜21c,22a〜22c間の配線接続は、1枚のリードフレーム28で行うことにより形成されている。したがって、パワー半導体素子21a〜21c,22a〜22c間の配線接続に必要な部品点数が少なくなり、実装工程が簡単になる。
According to this embodiment, the following effects can be obtained.
(1) In the inverter device 20 as a semiconductor device, power semiconductor elements 21a to 21c and 22a to 22c as six switching elements constituting a three-phase inverter circuit are modularized. The wiring connections between the power semiconductor elements 21 a to 21 c and 22 a to 22 c are formed by a single lead frame 28. Therefore, the number of parts required for wiring connection between the power semiconductor elements 21a to 21c and 22a to 22c is reduced, and the mounting process is simplified.

(2)各パワー半導体素子21a〜21c,22a〜22cはリードフレーム28に接続される側の面と反対側の面が導電材製のヒートスプレッダ23a,23bに接続されている。したがって、インバータ装置20(半導体装置)の放熱性能が高くなり、より高出力を図ることが可能になる。   (2) The power semiconductor elements 21a to 21c and 22a to 22c are connected to heat spreaders 23a and 23b made of a conductive material on the side opposite to the side connected to the lead frame 28. Therefore, the heat dissipation performance of the inverter device 20 (semiconductor device) is improved, and higher output can be achieved.

(3)リードフレーム28は、一部がパワー半導体素子21a〜21c,22a〜22cに接続され、一部がヒートスプレッダ23a,23bに接続され、パワー半導体素子21a〜21c,22a〜22cに対する接続部と、ヒートスプレッダ23a,23bに対する接続部とは同一平面上にない。しかし、リードフレーム28は、ヒートスプレッダ23a,23bに対する接続部となる正極用配線部25、U相用電極部27U、V相用電極部27V及びW相用電極部27Wの先端側にヒートスプレッダ23a,23bに近づくように屈曲形成された屈曲部25a,27aを有する。したがって、同一平面上にないパワー半導体素子21a〜21c,22a〜22c及びヒートスプレッダ23a,23bに対する半田付けを1回で容易に行うことができる。   (3) The lead frame 28 is partly connected to the power semiconductor elements 21a to 21c and 22a to 22c, partly connected to the heat spreaders 23a and 23b, and a connection portion for the power semiconductor elements 21a to 21c and 22a to 22c. The connection parts for the heat spreaders 23a and 23b are not on the same plane. However, the lead frame 28 is connected to the heat spreaders 23a, 23b on the front end side of the positive electrode wiring part 25, the U-phase electrode part 27U, the V-phase electrode part 27V, and the W-phase electrode part 27W, which are connection parts to the heat spreaders 23a, 23b. The bent portions 25a and 27a are formed so as to be closer to each other. Therefore, the power semiconductor elements 21a to 21c, 22a to 22c and the heat spreaders 23a and 23b that are not on the same plane can be easily soldered once.

(4)パワー半導体素子21a〜21c,22a〜22cは、それぞれ1個のスイッチング素子及び1個のダイオードが一つのデバイスとして組み込まれている。したがって、それぞれ独立した電子部品のスイッチング素子及びダイオードを使用する構成に比べて、半田付けの工数が少なくなり、インバータ装置20の小型化も可能となる。   (4) Each of the power semiconductor elements 21a to 21c and 22a to 22c includes one switching element and one diode as one device. Therefore, the number of soldering steps can be reduced and the inverter device 20 can be downsized as compared with a configuration using switching elements and diodes of independent electronic components.

(5)半導体装置(インバータ装置20)を製造する際、ヒートスプレッダ23a,23bの上にパワー半導体素子21a〜21c,22a〜22c及びリードフレーム28の順に載置した状態で、半田24を介してヒートスプレッダ23a,23b、パワー半導体素子21a〜21c,22a〜22c及びリードフレーム28を接続する。したがって、半田付け後に、その状態のまま、パワー半導体素子21a〜21c,22a〜22cと信号端子29とを信号配線30で接続することができ、リードフレーム28上にパワー半導体素子21a〜21c,22a〜22c及びヒートスプレッダ23a,23bの順に載置する場合に比べて工数が低減する。   (5) When manufacturing the semiconductor device (inverter device 20), the power semiconductor elements 21a to 21c, 22a to 22c and the lead frame 28 are placed in this order on the heat spreaders 23a and 23b, and the heat spreader is connected via the solder 24. 23a, 23b, power semiconductor elements 21a-21c, 22a-22c and lead frame 28 are connected. Therefore, after the soldering, the power semiconductor elements 21a to 21c and 22a to 22c and the signal terminal 29 can be connected to each other by the signal wiring 30 in the state, and the power semiconductor elements 21a to 21c and 22a are provided on the lead frame 28. The number of man-hours is reduced as compared with the case of mounting in the order of ˜22c and the heat spreaders 23a, 23b.

実施形態は前記に限定されるものではなく、例えば、次のように具体化してもよい。
○ 同一平面上にないパワー半導体素子21a〜21c,22a〜22cに対する接続部と、ヒートスプレッダ23a,23bに対する接続部とに対する半田付けを1回で行う構成は、正極用配線部25、U相用電極部27U、V相用電極部27V及びW相用電極部27Wの先端側に屈曲部25a,27aを形成するものに限らない。例えば、図5(a),(b)に示すように、正極用配線部25、U相用電極部27U、V相用電極部27V及びW相用電極部27Wの先端側に屈曲部を形成せずに、先端側とヒートスプレッダ23a,23bとの間に、パワー半導体素子21a〜21c,22a〜22cと同じ厚さの導電部材32を介在させて半田付けを行うようにしてもよい。この場合、リードフレーム28に屈曲加工を行う必要がなく、リードフレーム28の製造が簡単になる。
The embodiment is not limited to the above, and may be embodied as follows, for example.
The configuration in which soldering is performed once for the connecting portions to the power semiconductor elements 21a to 21c and 22a to 22c and the connecting portions to the heat spreaders 23a and 23b that are not on the same plane is the positive electrode wiring portion 25 and the U-phase electrode. It is not restricted to what forms bending part 25a, 27a in the front end side of the part 27U, the V-phase electrode part 27V, and the W-phase electrode part 27W. For example, as shown in FIGS. 5A and 5B, a bent portion is formed on the distal end side of the positive electrode wiring portion 25, the U-phase electrode portion 27U, the V-phase electrode portion 27V, and the W-phase electrode portion 27W. Instead, soldering may be performed by interposing a conductive member 32 having the same thickness as the power semiconductor elements 21a to 21c and 22a to 22c between the front end side and the heat spreaders 23a and 23b. In this case, there is no need to bend the lead frame 28, and the manufacture of the lead frame 28 is simplified.

○ パワー半導体素子21a〜21c,22a〜22cと、ヒートスプレッダ23a,23bと、リードフレーム28とを半田付けする工程で、リードフレーム28の上にシート半田、パワー半導体素子21a〜21c,22a〜22c、シート半田、ヒートスプレッダ23a,23bの順に配置した状態で、半田を溶融させてもよい。   In the process of soldering the power semiconductor elements 21a to 21c, 22a to 22c, the heat spreaders 23a and 23b, and the lead frame 28, sheet solder, power semiconductor elements 21a to 21c, 22a to 22c, The solder may be melted in a state where the sheet solder and the heat spreaders 23a and 23b are arranged in this order.

○ 半田付けは、シート半田を用いる方法に限らず、例えば、半田ペーストをヒートスプレッダ23a,23b及びリードフレーム28の半田付けを行う所定の位置に印刷したり、半田ペーストをパワー半導体素子21a〜21c,22a〜22cの所定位置に印刷したりしてもよい。   ○ Soldering is not limited to a method using sheet solder. For example, solder paste is printed at a predetermined position where the heat spreaders 23a and 23b and the lead frame 28 are soldered, or solder paste is applied to the power semiconductor elements 21a to 21c, You may print in the predetermined position of 22a-22c.

○ パワー半導体素子21a〜21c,22a〜22cとして、それぞれ1個のスイッチング素子及び1個のダイオードが一つのデバイスとして組み込まれているものに代えて、スイッチング素子及びダイオードが別体に形成されてそれぞれヒートスプレッダ23a,23b上に半田付けされた構成としてもよい。   ○ As the power semiconductor elements 21a to 21c and 22a to 22c, each switching element and diode are formed separately, instead of one switching element and one diode incorporated as one device, respectively. It is good also as a structure soldered on the heat spreader 23a, 23b.

○ スイッチング素子はIGBTに限らず、他のパワートランジスタ、例えば、MOSFETを使用してもよい。
以下の技術的思想(発明)は前記実施形態から把握できる。
The switching element is not limited to the IGBT, and another power transistor, for example, a MOSFET may be used.
The following technical idea (invention) can be understood from the embodiment.

(1)請求項1に記載の発明において、前記リードフレームは、前記ヒートスプレッダに対する接続部となる正極用配線部及び負極用配線部と、U相用電極部、V相用電極部及びW相用電極部とを有し、前記正極用配線部、U相用電極部、V相用電極部及びW相用電極部の先端側にヒートスプレッダに近づくように屈曲形成された屈曲部を有する。   (1) In the invention according to claim 1, the lead frame includes a positive electrode wiring portion and a negative electrode wiring portion, which are connection portions to the heat spreader, a U-phase electrode portion, a V-phase electrode portion, and a W-phase electrode. And a bent portion that is bent so as to approach the heat spreader at the tip side of the positive electrode wiring portion, the U-phase electrode portion, the V-phase electrode portion, and the W-phase electrode portion.

(2)請求項1又は前記技術的思想(1)に記載の発明において、前記パワー半導体素子は、それぞれ1個のスイッチング素子及び1個のダイオードが一つのデバイスとして組み込まれている。   (2) In the invention described in claim 1 or the technical idea (1), each of the power semiconductor elements includes one switching element and one diode as one device.

Q1,Q2,Q3,Q4,Q5,Q6…スイッチング素子、20…半導体装置としてのインバータ装置、21a,21b,21c,22a,22b,22c…パワー半導体素子、23a,23b…ヒートスプレッダ、28…リードフレーム。   Q1, Q2, Q3, Q4, Q5, Q6 ... switching elements, 20 ... inverter devices as semiconductor devices, 21a, 21b, 21c, 22a, 22b, 22c ... power semiconductor elements, 23a, 23b ... heat spreaders, 28 ... lead frames .

Claims (1)

3相インバータ回路を構成する6個のスイッチング素子としてのパワー半導体素子がモジュール化された半導体装置であって、
前記各パワー半導体素子間の配線接続を1枚のリードフレームで行うことにより形成され、前記各パワー半導体素子は前記リードフレームに接続される側の面と反対側の面が導電材製のヒートスプレッダに接続されていることを特徴とする半導体装置。
A semiconductor device in which power semiconductor elements as six switching elements constituting a three-phase inverter circuit are modularized,
Each power semiconductor element is formed by performing wiring connection between the power semiconductor elements with a single lead frame, and the power semiconductor element has a surface opposite to the side connected to the lead frame on a heat spreader made of a conductive material. A semiconductor device which is connected.
JP2010237488A 2010-10-22 2010-10-22 Semiconductor device Pending JP2012089794A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010237488A JP2012089794A (en) 2010-10-22 2010-10-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010237488A JP2012089794A (en) 2010-10-22 2010-10-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2012089794A true JP2012089794A (en) 2012-05-10

Family

ID=46261061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010237488A Pending JP2012089794A (en) 2010-10-22 2010-10-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2012089794A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014030458A1 (en) * 2012-08-20 2014-02-27 日立オートモティブシステムズ株式会社 Power semiconductor module
JP2014175652A (en) * 2013-03-07 2014-09-22 Internatl Rectifier Corp Open source power quad flat no-lead (pqfn) leadframe
EP3979319A4 (en) * 2019-05-31 2023-06-28 Aoi Electronics Co. Ltd. Semiconductor device and method for manufacture of semiconductor device
EP4290573A1 (en) * 2022-06-08 2023-12-13 Nexperia B.V. A semiconductor package assembly and a method of manufacturing such semiconductor package assembly

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014030458A1 (en) * 2012-08-20 2014-02-27 日立オートモティブシステムズ株式会社 Power semiconductor module
JP2014175652A (en) * 2013-03-07 2014-09-22 Internatl Rectifier Corp Open source power quad flat no-lead (pqfn) leadframe
EP3979319A4 (en) * 2019-05-31 2023-06-28 Aoi Electronics Co. Ltd. Semiconductor device and method for manufacture of semiconductor device
EP4290573A1 (en) * 2022-06-08 2023-12-13 Nexperia B.V. A semiconductor package assembly and a method of manufacturing such semiconductor package assembly

Similar Documents

Publication Publication Date Title
JP6272385B2 (en) Semiconductor device
JP4582161B2 (en) Power converter
US8129836B2 (en) Semiconductor device
KR100735852B1 (en) Semiconductor device
JP4640423B2 (en) Power converter
JP4640425B2 (en) Power converter
WO2012096066A1 (en) Power semiconductor module
CN110178304B (en) Semiconductor device with a plurality of semiconductor chips
JPWO2013121491A1 (en) Semiconductor device and manufacturing method thereof
JP2012089794A (en) Semiconductor device
KR101073286B1 (en) Power semiconductor module
JP5092892B2 (en) Semiconductor device
EP2099121B1 (en) Power converter apparatus
JP5062029B2 (en) Semiconductor device
JP5092804B2 (en) Power converter
JP2011054773A (en) Semiconductor device
JP2014154770A (en) Semiconductor device and semiconductor device manufacturing method
JP6648000B2 (en) Circuit body and method of manufacturing circuit body
JP4640424B2 (en) Power converter
JP3922698B2 (en) Semiconductor device
CN216849933U (en) Packaging structure of direct current single phase motor drive power device
JP2012209598A (en) Semiconductor device
JP2014017895A (en) Inverter device
JP2013038310A (en) Semiconductor module and manufacturing method of the same