JP5092804B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device.

  In a semiconductor device (power semiconductor module) that converts direct current into alternating current using a semiconductor circuit and a power conversion device (inverter device) that includes the power semiconductor module and a capacitor module that forms a direct current smoothing circuit, the inductance of the wiring is reduced. It is necessary to.

2. Description of the Related Art Conventionally, a structure and a configuration have been proposed that reduce the parasitic inductance in the internal wiring of a power semiconductor module, the internal wiring of a capacitor module, and the external wiring from the capacitor module to the semiconductor module (see, for example, Patent Document 1). In Patent Document 1, as shown in FIGS. 14A and 14B, a switching chip 73 and a diode chip 74 are provided on an insulating substrate 72 provided on a base 71, and a P side (positive side) conductor. A power semiconductor module is disclosed in which 75 and N-side (negative-side) conductors 76 are provided in a laminated form insulated from each other and housed in an insulating case (not shown). The P-side conductor 75 and the N-side conductor 76 include flat main conductors 75a and 76a, and strip-shaped subconductors 75b and 76b formed at the ends of the main conductors 75a and 76a and insulated from each other. The end portions of the sub conductors 75b and 76b are external connection terminals P2 and N2. In addition, an inverter device is described in which a capacitor module is disposed on an insulating case of a power semiconductor module. Further, a configuration is also disclosed in which branch conductors are erected on the main conductors 75a and 76a constituting the P-side conductor 75 and the N-side conductor 76, and a capacitor element is connected to each branch conductor.
JP 2005-347561 A

  In Patent Document 1, the P-side conductor 75 and the N-side conductor 76 of the power semiconductor module and the P-side conductor and the N-side conductor of the capacitor module are provided in a mutually insulated laminated form, A configuration for reducing the inductance of the internal wiring of the capacitor module is disclosed. In addition, a configuration is disclosed in which the external connection terminal is configured by the end portions of the strip-shaped sub conductors 75b and 76b, and a part of the sub conductors 75b and 76b are arranged close to each other in parallel to reduce inductance.

  In the case of a power semiconductor module, when the amount of current flowing through the switching element is large, a plurality of switching elements may be connected in parallel instead of using one switching element. In that case, in order to reduce the inductance of the entire internal wiring of the power semiconductor module, connection conductors 75u, 75v, 75w, 76u, 76v, and 76w that supply the current of the main conductors 75a and 76a to the circuit pattern on the insulating substrate 72; It is necessary to consider the relationship between the connection point with the circuit pattern and the switching chip 73. However, Patent Document 1 has no description regarding the case of using a plurality of switching elements connected in parallel instead of using one switching element.

  The present invention has been made in view of the above problems, and its object is to reduce the wiring inductance between the connection portion of the wiring member electrically connected to the capacitor to the circuit pattern and each switching element. It is providing the power converter device which can aim at.

  In order to achieve the above-mentioned object, the invention according to claim 1 is a flat positive electrode disposed in parallel with a substrate on which a plurality of switching elements are mounted, in a state of being electrically insulated from each other. A power conversion device comprising: a wiring member for a negative electrode; a wiring member for a negative electrode; and a capacitor having a positive electrode terminal electrically connected to the positive electrode wiring member and a negative electrode terminal electrically connected to the negative electrode wiring member. . The substrate has a first pattern in which a drain or a collector of the switching element is electrically connected as a circuit pattern on which the switching element is mounted, and a source or an emitter of the switching element is electrically connected. And a second region. A region where at least a joint portion of the positive electrode wiring member or a joint portion of the output electrode member is joined in the first region and a joint portion of at least the output electrode member in the second region corresponding to the first region are joined. The region or the region where the joint portion of the negative electrode wiring member is joined is provided so as to be adjacent in parallel.

The positive electrode wiring member and the negative electrode wiring member are arranged so as to overlap in parallel with the substrate, and terminal portions are provided on both sides of the substrate from both ends in the width direction. The joint portion is formed by being bent so that the tip portion extends in parallel with the substrate. The capacitor is arranged on one of the positive wiring member and the negative wiring member that does not face the substrate so that the positive terminal and the negative terminal are on the wiring member side. ing.
In the present invention, since the flat positive electrode wiring member and the negative electrode wiring member are arranged in close proximity and in parallel with each other, the wiring inductance during driving of the power converter is reduced. The circuit pattern on which each switching element is mounted includes at least a first region where the drain or collector of the switching element is electrically connected and a second region where the source or emitter of the switching element is electrically connected. A region where the joint portions of the wiring member for negative electrode, the wiring member for negative electrode, and the output electrode member are joined is provided to be adjacent in parallel. Therefore, when each switching element is driven, the direction of the current flowing in the first region and the second region is reversed, and the wiring inductance is further reduced by the mutual inductance effect.
In the present invention, since the positive electrode wiring member and the negative electrode wiring member are arranged so as to overlap in parallel with the substrate, the case where the substrate is used on the lower side as compared with the case of being arranged vertically is used. The overall height of the power conversion device can be reduced. In addition, since the terminal portions are provided on both sides in the width direction of the positive electrode wiring member and the negative electrode wiring member, when the number of switching elements increases, the wiring inductance is reduced as a whole power conversion device, and each switching element and the wiring It is easy to level the wiring inductance between the members.

  According to a second aspect of the present invention, in the first aspect of the invention, the first region and the second region are formed in a strip shape, and a plurality of the switching elements are mounted in each first region. The source or emitter of the switching element is connected to the second region by wire bonding. In the present invention, since the first region and the second region are formed in a strip shape, the length of the adjacent portion is longer than in the case where the first region and the second region are formed in a block shape instead of a strip shape. Thus, the mutual inductance effect is increased and the wiring inductance is further reduced.

  The invention according to claim 3 is the invention according to claim 2, wherein the power conversion device is an inverter device, each arm is provided with 4N (N is a natural number) switching elements, and the positive electrode wiring Two joining portions of the member, the joining portion of the negative electrode wiring member and the joining portion of the output electrode member are provided for each arm, and 2N switching elements correspond to each joining portion of the positive wiring member. It is mounted on the first area. Here, “corresponding to each junction of the positive electrode wiring member by 2N pieces” means that 2N switching elements out of 4N are close to the junction of one positive electrode wiring member, and the remaining 2N pieces. This means that the switching element is close to the joint of the other positive electrode wiring member. In the present invention, in addition to the reduction of the wiring inductance, the wiring inductance between each switching element and each junction can be leveled even when the number of switching elements increases.

  ADVANTAGE OF THE INVENTION According to this invention, the power converter device which can aim at reduction of the wiring inductance between the junction part to the circuit pattern of the wiring member electrically connected to the capacitor | condenser and each switching element can be provided.

Hereinafter, an embodiment in which the present invention is embodied in a three-phase inverter device will be described with reference to FIGS.
First, the circuit configuration of the inverter device will be described. As shown in FIG. 1A, the inverter device 11 includes an inverter circuit 12 having six switching elements Q1 to Q6. MOSFETs (metal oxide semiconductor field effect transistors) are used for the switching elements Q1 to Q6. In the inverter circuit 12, first and second switching elements Q1 and Q2, third and fourth switching elements Q3 and Q4, and fifth and sixth switching elements Q5 and Q6 are connected in series, respectively. Diodes D1 to D6 are connected in antiparallel between the drains and sources of the switching elements Q1 to Q6. The first, third and fifth switching elements Q1, Q3 and Q5 and the diodes D1, D3 and D5 connected to the first, third and fifth switching elements Q1, Q3 and Q5 are respectively upper arms. Called. The second, fourth and sixth switching elements Q2, Q4 and Q6 and the diodes D2, D4 and D6 connected to the second, fourth and sixth switching elements Q2, Q4 and Q6 are respectively lower pairs. Called the arm.

  The drains of the first, third and fifth switching elements Q1, Q3 and Q5 are connected to the positive input terminal 14 for power supply input via the wiring 13, and the second, fourth and sixth switching elements Q2, Q4 and Q6 are connected to a negative input terminal 16 for power supply input via a wiring 15. A plurality of capacitors 17 are connected in parallel between the wiring 13 and the wiring 15. In this embodiment, an electrolytic capacitor is used as the capacitor 17, the positive electrode (plus) terminal of the capacitor 17 is connected to the wiring 13, and the negative electrode (minus) terminal of the capacitor 17 is connected to the wiring 15.

  The junction between switching elements Q1 and Q2 is at U-phase terminal U, the junction between switching elements Q3 and Q4 is at V-phase terminal V, and the junction between switching elements Q5 and Q6 is at W-phase terminal W. , Each connected. The gates of the switching elements Q1 to Q6 are connected to the drive signal input terminals G1 to G6. The sources of the switching elements Q1 to Q6 are connected to the signal terminals S1 to S6.

  In FIG. 1 (a), each upper arm and each lower arm are shown as one switching element and one diode, but each arm has a switching element Q as shown in FIG. 1 (b). And a plurality of pairs of diodes D are connected in parallel. In this embodiment, each arm is composed of four sets of switching elements Q and diodes D. That is, each arm consists of a plurality of switching elements for performing the same role as the function of one switching element.

Next, the structure of the inverter device 11 will be described.
As shown in FIGS. 2 and 3, in the inverter device 11, a semiconductor chip 23 is mounted on a substrate 22 composed of a copper metal base 20 and a ceramic substrate 21 as an insulating substrate. In the semiconductor chip 23, one switching element (MOSFET) and one diode are incorporated as one device. That is, the semiconductor chip 23 is a device including one switching element Q and one diode D shown in FIG.

  The ceramic substrate 21 is composed of a ceramic plate 26 having circuit patterns 24a, 24b, 24c, and 24d on the front surface and a metal plate 25 that functions as a bonding layer for bonding the ceramic substrate 21 and the metal base 20 to the back surface. Yes. The ceramic plate 26 is made of, for example, aluminum nitride, alumina, silicon nitride, or the like, and the circuit patterns 24a, 24b, 24c, 24d and the metal plate 25 are made of, for example, aluminum or copper. The ceramic substrate 21 is joined to the metal base 20 with solder (not shown) through the metal plate 25. Hereinafter, in this specification, the metal base 20 is described as the bottom (lower part) of the inverter device 11.

  The circuit pattern 24a is a circuit pattern for a gate signal, the circuit pattern 24b is a circuit pattern for a drain, the circuit pattern 24c is a circuit pattern for a source, and the circuit pattern 24d is a circuit pattern for a source signal. Each circuit pattern 24a, 24b, 24c, 24d is formed in a strip shape. The circuit pattern 24b for drain and the circuit pattern 24c for source are formed so as to extend in parallel adjacent to each other, and the circuit pattern 24a for gate signal and the circuit pattern 24d for source signal are opposite to the circuit pattern 24c. It is formed to extend in parallel with the circuit pattern 24b on the side. The semiconductor chip 23 is joined to the drain circuit pattern 24b by solder. That is, the substrate 22 has a circuit pattern 24b as a first region in which the drain of the switching element is electrically connected as a circuit pattern on which the switching element is mounted, and a second in which the source of the switching element is electrically connected. And a circuit pattern 24c as a region. As shown in FIG. 5, the semiconductor chip 23 includes a gate and a circuit pattern 24a for a gate signal, a circuit pattern 24c for a source and a source, and a circuit pattern 24d for a source and a source signal. They are electrically connected by wire bonding.

  The metal base 20 is formed in a substantially rectangular shape, and the ceramic substrate 21 is also formed in a rectangular shape. Twelve ceramic substrates 21 are provided and arranged in two columns and six rows so that the longitudinal direction is six in each column in a state perpendicular to the longitudinal direction of the metal base 20. The semiconductor chips 23 arranged on the two ceramic substrates 21 in each row constitute each arm of the inverter circuit 12. In this embodiment, two semiconductor chips 23 are mounted on each ceramic substrate 21, and each of the four semiconductor chips 23 constitutes one arm. That is, a plurality of sets of switching elements composed of a plurality of switching elements (semiconductor chips 23) for performing the same role as the function of one switching element are mounted on the substrate 22. The semiconductor chip 23 has a space in the center in the longitudinal direction of the circuit pattern 24b, and is arranged so that one semiconductor chip 23 is located on each side of the space.

  Above the substrate 22, a flat plate-like positive electrode wiring member 27 and a negative electrode wiring member 28 are arranged in parallel with the substrate 22 so as to overlap each other while being insulated from each other. In this embodiment, a negative electrode wiring member 28 is disposed above the positive electrode wiring member 27. The positive wiring member 27 constitutes the wiring 13 in FIG. 1A, and the negative wiring member 28 constitutes the wiring 15 in FIG. 1A. The positive electrode wiring member 27 includes a plurality of (three to six in this embodiment) terminal portions 27 a provided so as to extend from the end in the width direction toward the substrate 22, and the ceramic substrate 21 constituting the upper arm. It is ultrasonically bonded to the central portion of the upper circuit pattern 24b for drain. The negative electrode wiring member 28 includes a plurality of (three to six in this embodiment) terminal portions 28 a provided so as to extend from the end in the width direction toward the substrate 22, and the ceramic substrate 21 constituting the lower arm. It is ultrasonically bonded to the center of the upper circuit pattern 24c for the source. That is, two joining portions 27b of the positive electrode wiring member 27 and two joining portions 28b of the negative electrode wiring member 28 are provided for each pair of arms, and two semiconductor chips (switching elements) 23 are provided for each of the positive electrode wiring members 27. It is mounted on the circuit pattern 24b corresponding to each joint portion 27b.

  More specifically, as shown in FIG. 4B, the terminal portions 27a and 28a are respectively located on both sides of the width direction end portions of the positive electrode wiring member 27 and the negative electrode wiring member 28 with respect to the center line in the width direction. Are line symmetrical. Each terminal portion 27a, 28a is bent toward the substrate 22 side from the end in the width direction of the positive electrode wiring member 27 and the negative electrode wiring member 28, and is further joined to the substrate 22 by ultrasonic bonding. 28b is bent so as to extend in parallel with the wiring members 27 and 28. And each junction part 27b, 28b is provided so that the ultrasonic junction location of each terminal part 27a, 28a arrange | positioned on the same side of the wiring members 27, 28 may be located on a straight line, and each circuit pattern 24b, 24c is ultrasonically bonded.

  As shown in FIGS. 6A and 6B, the positive electrode wiring member 27 and the negative electrode wiring member 28 are connected to both ends of the width direction from the joint portions 27b and 28b of the terminal portions 27a and 28a. On the upper side, drooping portions 27c and 28c are formed which are continuous with the respective terminal portions 27a and 28a and arranged so as to overlap each other. The hanging portions 27c and 28c do not extend over the entire length of the positive electrode wiring member 27 and the negative electrode wiring member 28, but are provided so that a plurality of cutout portions 27d and 28d face each other. Between the positive electrode wiring member 27 and the negative electrode wiring member 28, an insulating member 29 (shown in FIG. 4B) is disposed to ensure electrical insulation between them. The positive wiring member 27, the negative wiring member 28, and the insulating member 29 are formed with long holes through which the positive terminal 17a and the negative terminal 17b of the capacitor 17 can be inserted.

  An electrically insulating support frame 30 is fixed to the metal base 20 so as to accommodate all the ceramic substrates 21 in the frame along the periphery thereof. A positive input terminal 14 for inputting an external power source is formed at one end portion in the longitudinal direction of the positive electrode wiring member 27. The plus input terminal 14 is arranged so that a part thereof is located outside the support frame 30. The negative wiring member 28 is formed with a negative input terminal 16 for external power input at the end of the positive wiring member 27 in the longitudinal direction opposite to the side where the positive input terminal 14 is formed. The minus input terminal 16 is also arranged so that a part thereof is located outside the support frame 30.

  A plurality of (four in this embodiment) capacitors 17 are connected to the positive electrode terminal 17a on the negative electrode wiring member 28, that is, on one of the positive electrode wiring member 27 and the negative electrode wiring member 28 that does not face the substrate 22. And the negative electrode terminal 17b is disposed through an electrical insulating member (not shown) in a state of facing downward. Each capacitor 17 has a positive electrode terminal 17 a and a negative electrode terminal 17 b provided on one side of the capacitor body, the positive electrode terminal 17 a is connected to the positive electrode wiring member 27, and the negative electrode terminal 17 b is connected to the negative electrode wiring member 28. .

  As shown in FIGS. 2 and 3, the three output electrode members 32 </ b> U, 32 </ b> V, and 32 </ b> W of the inverter device 11 are formed in a substantially L-shaped side surface, and a portion extending upward is close to the support frame 30. The portion extending in the horizontal direction is disposed below the positive electrode wiring member 27 in a state orthogonal to the longitudinal direction. The positive electrode wiring member 27 and the output electrode members 32U, 32V, 32W are insulated by a silicone gel 36 (shown in FIG. 4A). The output electrode member 32U includes a circuit pattern 24c for the source of the upper arm constituted by the first switching element Q1 and the diode D1, and a circuit for the drain of the lower arm constituted by the second switching element Q2 and the diode D2. It is ultrasonically bonded to the pattern 24b. The output electrode member 32V includes an upper arm source circuit pattern 24c composed of the third switching element Q3 and the diode D3, and a lower arm drain circuit composed of the fourth switching element Q4 and the diode D4. It is ultrasonically bonded to the pattern 24b. The output electrode member 32W includes an upper arm source circuit pattern 24c composed of a fifth switching element Q5 and a diode D5, and a lower arm drain circuit composed of a sixth switching element Q6 and a diode D6. It is ultrasonically bonded to the pattern 24b.

  Each of the output electrode members 32U, 32V, and 32W is formed by pressing a copper plate having substantially the same width as the ceramic substrate 21. As shown in FIG. 8B and the like, each output electrode member 32U, 32V, 32W has a substantially central portion of the circuit pattern 24b of the two ceramic substrates 21 constituting the upper arm, and 2 constituting the lower arm. A total of four joint portions 35 that are respectively joined to substantially the center portions of the circuit patterns 24c of the individual ceramic substrates 21 are provided. Each of the output electrode members 32U, 32V, and 32W is bent substantially in an L shape, and the two joint portions 35 are disposed on both sides of the tip of the horizontally extending portion, and the two joint portions 35 are close to the bent portion. It is formed so as to protrude. Each output electrode member 32U, 32V, 32W is provided with a space in which the terminal portion 28a and the joint portion 28b of the negative electrode wiring member 28 can be disposed between the two joint portions 35. Then, as shown in FIG. 3, each of the two joining portions 35 is arranged on the circuit patterns 24b and 24c so as to be aligned with the joining portions 27b and 28b of the positive electrode wiring member 27 and the negative electrode wiring member 28. It is joined.

  That is, in this embodiment, the drain circuit pattern 24b (first region) and the source circuit pattern 24c (second region) include at least the joint portion 27b of the positive electrode wiring member 27 and the negative electrode wiring member 28. The regions where the joint portions 28b and the joint portions 35 of the output electrode members 32U, 32V, and 32W are joined are provided adjacent to each other in a parallel state. The relationship between the semiconductor chip 23 and the joint portion 27b of the positive electrode wiring member 27, the joint portion 28b of the negative electrode wiring member 28, the output electrode member 32U, and the like corresponding to the pair of upper and lower arms is described in detail. This is as shown in FIG. That is, in the circuit pattern 24b on the ceramic substrate 21 constituting the upper arm, the joint portion 27b of the positive electrode wiring member 27 is joined to the center portion of the circuit pattern 24b, and the semiconductor chip 23 is sandwiched on both sides of the joint portion 27b. Is arranged. In the circuit pattern 24c, the joint 35 such as the output electrode member 32U is joined to the center of the circuit pattern 24c. On the other hand, in the circuit pattern 24b on the ceramic substrate 21 constituting the lower arm, the joint portion 35 such as the output electrode member 32U is joined to the center portion of the circuit pattern 24b, and the semiconductor chip 23 is sandwiched on both sides of the joint portion 35. Is arranged. In the circuit pattern 24c, the joint portion 28b of the negative electrode wiring member 28 is joined to the center portion of the circuit pattern 24c. However, FIG. 5 shows a portion corresponding to the output electrode member 32V.

  Of the two ceramic substrates 21 corresponding to each arm, the circuit pattern 24a for the gate signal of the ceramic substrate 21 corresponding to the distal end side of the output electrode members 32U, 32V, 32W has drive signal input terminals G1 to G6. The first ends of the signal terminals S1 to S6 are joined to the circuit pattern 24d for the source signal, respectively. Each of the terminals G1 to G6 and S1 to S6 is integrally formed with the support frame 30 so as to penetrate the support frame 30 so that the second end portion protrudes from the support frame 30. The circuit patterns 24a and the circuit patterns 24d formed on the two ceramic substrates 21 constituting each arm are electrically connected to each other by wire bonding.

  The support frame 30 is filled and cured with a silicone gel 36 for securing and protecting the insulation of the semiconductor chip 23. On the metal base 20, the semiconductor chip 23 of the substrate 22, that is, the surface on which the switching elements Q1 to Q6 are mounted, the positive electrode wiring member 27, the negative electrode wiring member 28, the capacitor 17, the output electrode member 32U, The cover 37 surrounding the 32V and 32W and the support frame 30 is fixed by bolts.

Next, a method for manufacturing the inverter device 11 configured as described above will be described.
First, the mounting process of the semiconductor chip 23 on the ceramic substrate 21 is performed. In this step, as shown in FIG. 7A, the two semiconductor chips 23 are placed on the circuit pattern 24b for the drain of the ceramic substrate 21 so that a space exists in the center in the longitudinal direction of the circuit pattern 24b. Join by soldering. Next, between the gate of the semiconductor chip 23 and the circuit pattern 24a for gate signal, between the source and source circuit pattern 24c of the semiconductor chip 23, and between the source and source signal circuit pattern 24d of the semiconductor chip 23. They are electrically connected by wire bonding.

  Next, a step of bonding the ceramic substrate 21 onto the metal base 20 is performed. In this step, as shown in FIG. 7B, the ceramic substrate 21 on which the semiconductor chip 23 is mounted is joined on the metal base 20 by soldering in 6 rows and 2 columns, and each of the two constituting the same arm. The circuit patterns 24a for gate signals and the circuit patterns 24d for source signals of the ceramic substrate 21 are electrically connected by wire bonding (not shown).

  Next, a step of joining the output electrode members 32U, 32V, 32W to the ceramic substrate 21 is performed. In this step, as shown in FIG. 8A, first, the support frame 30 equipped with the drive signal input terminals G1 to G6 and the signal terminals S1 to S6 is fixed on the metal base 20 so as to surround the ceramic substrate 21. To do. The support frame 30 is fixed using an adhesive or a screw. Next, as shown in FIG. 8B, the output electrode members 32U, 32V, and 32W are arranged so that each joint portion 35 is in contact with the substantially central portion of the drain circuit pattern 24b and the source circuit pattern 24c. To do. And each joining part 35 is joined to the circuit pattern 24b and the circuit pattern 24c sequentially by ultrasonic bonding. Further, the first ends of the drive signal input terminals G1 to G6 are joined to the circuit pattern 24a, and the first ends of the signal terminals S1 to S6 are joined to the circuit pattern 24d by ultrasonic bonding.

  Next, a process of assembling a capacitor assembly (assembly) is performed. In this step, the four capacitors 17 are fixed with a jig in a row at a predetermined interval in a state where the positive electrode terminal 17a and the negative electrode terminal 17b face upward. In this state, the negative electrode wiring member 28 is fixed to the negative electrode terminal 17b of each capacitor 17 with a screw through an insulating material. Next, the positive electrode wiring member 27 is fixed to the positive electrode terminal 17 a of the capacitor 17 with a screw in a state where the insulating member 29 is disposed between the negative electrode wiring member 28. As described above, with the insulation between the positive electrode wiring member 27 and the negative electrode wiring member 28 secured, the positive electrode wiring member 27 is electrically connected to the positive electrode terminal 17a of the capacitor 17, and the negative electrode wiring member 28 is electrically connected to the negative electrode terminal 17b. In general, the capacitor assembly 38 is assembled.

  Next, a step of ultrasonically bonding the capacitor assembly 38 to the ceramic substrate 21 is performed. In this step, first, the capacitor assembly 38 is placed on the ceramic substrate 21. As shown in FIG. 9, the capacitor assembly 38 is disposed at a predetermined position in the support frame 30 from above the ceramic substrate 21. In this state, as shown in FIG. 3, the joint portions 27b and 28b arranged on the same side in the width direction of the positive electrode wiring member 27 and the negative electrode wiring member 28 are positioned on a straight line.

  In this state, the joining portions 27b and 28b are joined to the circuit patterns 24b and 24c in order by ultrasonic joining. Since the joint portions 27b and 28b and the capacitor 17 are close to each other, if soldering is used for joining the terminal portions 27a and 28a, if a capacitor that does not particularly consider general heat resistance is used, the capacitor is heated by the soldering. 17 may be adversely affected. However, since the joining portions 27b and 28b are joined by ultrasonic joining, the amount of heat applied to the capacitor 17 is reduced, and it is not necessary to use a special capacitor having high heat resistance.

  Next, in order to electrically insulate and protect the semiconductor chip 23 and each part such as each joint that does not like moisture and oxidation, the silicone gel 36 is injected into the support frame 30 and cured, and the silicone gel 36 is filled and cured. Is done. Since the notched portions 27d and 28d are formed in the hanging portions 27c and 28c of the positive electrode wiring member 27 and the negative electrode wiring member 28, compared with the case where the notched portions 27d and 28d are not present, the silicone gel is injected. Silicone gel easily flows between the positive electrode wiring member 27 and the negative electrode wiring member 28. Finally, the cover 37 is fixed to the metal base 20 with bolts, and the inverter device 11 is completed.

Next, the operation of the inverter device 11 configured as described above will be described.
The inverter device 11 is used, for example, as a part of a vehicle power supply device. The inverter device 11 has a positive input terminal 14 and a negative input terminal 16 connected to a DC power source (not shown), and a U-phase terminal U, a V-phase terminal V, and a W-phase terminal W connected to a motor (not shown). The drive signal input terminals G1 to G6 and the signal terminals S1 to S6 are used in a state of being connected to a control device (not shown).

  The first, third, and fifth switching elements Q1, Q3, and Q5 of the upper arm and the second, fourth, and sixth switching elements Q2, Q4, and Q6 of the lower arm are turned on and off at predetermined intervals, respectively. As a result, alternating current is supplied to the motor to drive the motor.

  The positive wiring member 27 and the negative wiring member 28 are supplied with a current that suddenly rises or falls during switching of the switching elements Q1 to Q6. The current flows in the reverse direction in the positive wiring member 27 and the negative wiring member 28. It becomes. Since the positive electrode wiring member 27 and the negative electrode wiring member 28 are formed in parallel flat plate shapes and are arranged close to each other, the wiring inductance is reduced by the effect of mutual inductance. Further, since the hanging portions 27c and 28c are also arranged close to each other in parallel, the wiring inductance is further reduced as compared with the case where the hanging portions 27c and 28c do not exist.

  A circuit pattern 24b in which the drain of the semiconductor chip 23 (switching element) constituting each arm is electrically connected, and a circuit pattern 24c in which the source of the semiconductor chip 23 (switching element) constituting each arm is electrically connected. Are provided adjacent to each other in a parallel state. Then, the junction 27b of the positive electrode wiring member 27 or the junction 35 of the output electrode members 32U, 32V, 32W is joined to the circuit pattern 24b, and the junction 35 of the output electrode members 32U, 32V, 32W to the circuit pattern 24c. Alternatively, 28b of the negative electrode wiring member 28 is joined. Therefore, when the inverter device 11 is driven, that is, when each switching element is driven, the direction of the current flowing through the circuit pattern 24b and the circuit pattern 24c is reversed, and the wiring inductance is reduced by the mutual inductance effect. .

Therefore, according to this embodiment, the following effects can be obtained.
(1) The inverter device 11 is a flat plate arranged so as to be adjacent to and overlapped with a substrate 22 on which a plurality of switching elements for performing the same function as one switching element are mounted. And the capacitor 17 connected to the positive electrode wiring member 27 and the negative electrode wiring member 28. On the substrate 22, a circuit pattern 24b to which the drain of the switching element is electrically connected and a circuit pattern 24c to which the source is electrically connected are provided. Then, at least the joint portion 27b of the positive electrode wiring member 27 or the joint portion 35 such as the output electrode member 32U of the circuit pattern 24b and the joint portion 35 of the circuit pattern 24c such as the output electrode member 32U are joined. Or a region to which the bonding portion 28b of the negative electrode wiring member 28 is bonded is provided in parallel. Therefore, when the inverter device 11 is driven, that is, when each switching element is driven, the direction of the current flowing in the adjacent circuit pattern 24b and the circuit pattern 24c is reversed, and the wiring inductance is reduced by the mutual inductance effect. Is done.

  (2) The circuit pattern 24b and the circuit pattern 24c are formed in a band shape, and a plurality of semiconductor chips 23 are mounted on the circuit pattern 24b, and the sources of these semiconductor chips 23 are connected to the circuit pattern 24c by wire bonding. Therefore, as compared with the case where the circuit patterns 24b and 24c are formed in a block shape instead of a belt shape, the length of adjacent portions is increased, the mutual inductance effect is increased, and the wiring inductance is further reduced.

  (3) The power conversion device is an inverter device, and each arm includes four switching elements, such as a joint portion 27b of the positive electrode wiring member 27, a joint portion 28b of the negative electrode wiring member 28, and an output electrode member 32U. The two joint portions 35 are provided for each arm. Two semiconductor chips 23 correspond to the joint 27b, that is, two of the four semiconductor chips 23 are close to the joint 27b of one positive electrode wiring member 27, and the remaining two semiconductor chips 23 are It is mounted on the circuit pattern 24 b in a state close to the joint portion 27 b of the other positive electrode wiring member 27. Therefore, in addition to reducing the wiring inductance, the wiring inductance between each semiconductor chip 23 and each junction can be leveled even if the number of semiconductor chips 23 (switching elements) increases.

  (4) The positive electrode wiring member 27 and the negative electrode wiring member 28 are arranged so as to overlap in parallel with the substrate 22, and the terminal portions 27 a and 28 a extend from both ends in the width direction toward the substrate 22 side. Further, the joint portions 27 b and 28 b are formed by bending the tip portion so as to extend in parallel with the substrate 22. The capacitor 17 has a positive electrode terminal 17a and a negative electrode terminal 17b on the wiring member side on one of the positive electrode wiring member 27 and the negative electrode wiring member 28 that are not opposed to the substrate 22 (positive electrode wiring member 27). It is arranged to become. Therefore, when using it with a board | substrate down, the height of the whole power converter device can be made low. Further, since the terminal portions 27a and 28a are provided on both sides in the width direction of the positive electrode wiring member 27 and the negative electrode wiring member 28, when the number of semiconductor chips 23 (switching elements) increases, the entire power conversion device It is easy to reduce the wiring inductance and level the wiring inductance between each semiconductor chip 23 and the wiring member.

  (5) When the inverter device 11 is manufactured, after the positive electrode wiring member 27 and the negative electrode wiring member 28 and the capacitor 17 are bonded, the terminal portions 27a and 28a of the positive electrode wiring member 27 and the negative electrode wiring member 28 are bonded. The portions 27b and 28b are electrically bonded to the circuit patterns 24b and 24c of the substrate 22 by ultrasonic bonding. Therefore, unlike the case where soldering is used for joining the joint portions 27b and 28b, it is not necessary to use a special capacitor having high heat resistance.

  (6) Each output electrode member 32U, 32V, 32W is formed in an arrangement in which four joint portions 35 correspond to four corners of a virtual rectangle. Therefore, when each of the output electrode members 32U, 32V, and 32W is ultrasonically bonded to the ceramic substrate 21, the output electrode members 32U, 32V, and 32W are held because they are stably placed on the ceramic substrate 21 in a self-supporting state. Even if there is no jig to perform, ultrasonic bonding can be performed.

The embodiment is not limited to the above, and may be embodied as follows, for example.
○ Capacitor 17 has positive electrode terminal 17a connected to positive electrode wiring member 27 with respect to flat plate-like positive electrode wiring member 27 and negative electrode wiring member 28 arranged in close proximity and in parallel while being electrically insulated from each other. In addition, the negative terminal 17b may be electrically connected to the negative electrode wiring member 28, respectively. That is, the configuration is not limited to the configuration in which the positive electrode wiring member 27 and the negative electrode wiring member 28 exist between the capacitor 17 and the substrate 22. For example, as shown in FIG. 10, the insulating plate 40 is disposed on the output electrode members 32U, 32V, 32W in a state orthogonal to the output electrode members 32U, 32V, 32W, and the capacitor 17 is connected to the positive electrode terminal 17a on the insulating plate 40. The negative electrode terminal 17b is assembled in a state where it is placed so as to be opposite to the substrate 22 with respect to the capacitor body. The positive electrode wiring member 27 and the negative electrode wiring member 28 are fixed to the positive electrode terminal 17a and the negative electrode terminal 17b with screws. In this case, as shown in FIG. 10, the lengths of the terminal portions 27a and 28a and the hanging portions 27c and 28c of the positive electrode wiring member 27 and the negative electrode wiring member 28 are increased. However, compared to the case where the capacitor 17 is disposed outside the cover 37, the wiring inductance is reduced. Note that FIG. 10 is different from FIG.

  The arrangement of the circuit patterns 24a, 24b, 24c, and 24d on the ceramic substrate 21 does not need to be targeted by the ceramic substrate 21 that constitutes the upper arm and the ceramic substrate 21 that constitutes the lower arm. For example, FIG. As shown in FIG. Even in this case, the same effect can be obtained.

  Each arm may be composed of one ceramic substrate 21 instead of two ceramic substrates 21. In this case, between the gate signal circuit patterns 24a and between the source signal circuit patterns 24d. Wire bonding for electrical connection is not required. Also, the drain circuit pattern 24b and the source circuit pattern 24c of each arm, the positive electrode wiring member 27, the negative electrode wiring member 28, and the joint portions 27b, 28b, and 35 of the output electrode members 32U, 32V, and 32W, However, the number of joints is not two but one. However, if the joining locations are one by one, a jig for holding the capacitor assembly 38 and a jig for holding the output electrode members 32U, 32V, and 32W are required during ultrasonic bonding.

In order to make the output electrode members 32U, 32V, and 32W self-supporting, it is only necessary to include at least three joint portions 35.
It is not essential that the circuit patterns 24a, 24b, 24c, and 24d are formed in an elongated pattern and arranged in parallel. However, when the circuit patterns 24b and 24c are formed in a block shape, a plurality of semiconductor chips 23 are mounted, the joint portions 27b and 28b of the positive electrode wiring member 27 and the negative electrode wiring member 28, and the output electrode members 32U, 32V, The area of the ceramic substrate 21 necessary for securing a space for joining the 32W joint 35 is increased. Further, when the interval between the circuit patterns 24b and 24c is narrowed, it becomes difficult to ultrasonically bond the joint portions 35 in a state where the output electrode members 32U, 32V, and 32W are in a self-standing state.

  In the case where each arm is composed of one ceramic substrate 21, the circuit patterns 24a, 24b, 24c, 24d are not arranged in parallel, and for example, as shown in FIG. May be arranged in a substantially L shape so as to face the peripheral half of the circuit pattern 24c for source. Also in this case, the first region (circuit pattern 24b) to which the drain of the semiconductor chip 23 is electrically connected and the second region (circuit pattern 24c) to which the source of the semiconductor chip 23 is electrically connected are parallel to each other. It becomes the arrangement which adjoins.

  The arrangement of the capacitor 17 is not limited to the position corresponding to the substrate 22, that is, above the metal base 20. For example, as shown in FIGS. 12 and 13, the metal base 20 may be disposed on the side. The positive wiring member 27 and the negative wiring member 28 are arranged in parallel so that the negative wiring member 28 is on the capacitor 17 side, that is, the lower side, and the terminal portions 27a and 28a are the positive wiring member 27 and the negative electrode. The wiring member 28 is bent downward from the front end. Then, the joint portion 27 b of the positive electrode wiring member 27 is joined to the drain circuit pattern 24 b on the ceramic substrate 21, and the joint portion 28 b of the negative electrode wiring member 28 is joined to the source circuit pattern 24 c on the ceramic substrate 21. Has been. In this embodiment, each arm is constituted by one semiconductor chip 23 (switching element), and one set of upper arm and lower arm is constituted by one ceramic substrate 21. As shown in FIG. 12, two circuit patterns 24b and one circuit pattern 24c are formed on each ceramic substrate 21, and a semiconductor chip 23 is bonded to each circuit pattern 24b with solder H. The circuit pattern 24c is formed so as to extend along both circuit patterns 24b. The positive wiring member 27 has a joint portion 27b joined to one circuit pattern 24b on each ceramic substrate 21, and the negative wiring member 28 has a joint portion 28b joined to a circuit pattern 24c on each ceramic substrate 21. Yes.

The source of the semiconductor chip 23 bonded on the circuit pattern 24b to which the bonding portion 27b is bonded is electrically bonded to the circuit pattern 24b to which the bonding portion 27b is not bonded by wire bonding. Further, the source of the semiconductor chip 23 bonded on the circuit pattern 24b to which the bonding portion 27b is not bonded is electrically bonded to the circuit pattern 24c by wire bonding. And the junction part of the output electrode members 32U, 32V, 32W which are not shown in figure is joined on the circuit pattern 24b to which the junction part 27b is not joined. In this configuration, the semiconductor chip 23 bonded onto the circuit pattern 24b to which the bonding portion 27b is bonded constitutes the upper arm, and the semiconductor chip 23 bonded to the circuit pattern 24b to which the bonding portion 27b is not bonded corresponds to the lower arm. Configure. Also in this configuration, the substrate 22 includes, as a circuit pattern on which the switching element is mounted, a first region in which the drain of the switching element is electrically connected and a second region in which the source of the switching element is electrically connected. It has. And the area | region where the junction part 27b of the wiring member 27 for positive electrodes of at least 1st area | region is joined, The area | region where the junction part 28b of the wiring member 28 for negative electrodes of the 2nd area | region corresponding to the 1st area | region is joined Are adjacent to each other in a parallel state. Therefore, the inverter device 11
The wiring inductance as a whole is reduced. Further, in this embodiment, since the capacitor 17 is separated from the bonding positions of the bonding portions 27b and 28b of the positive electrode wiring member 27 and the negative electrode wiring member 28 with the circuit patterns 24b and 24c, bonding is limited to ultrasonic bonding. For example, you may join by soldering. In FIG. 12 and FIG. 13, circuit patterns other than the circuit patterns 24b and 24c, the output electrode member 32U, etc., and hatching are not shown.

  In the configuration in which the capacitor 17 is disposed on the side of the metal base 20, six ceramic substrates 21 constituting each arm are arranged in parallel on the metal base 20 along the positive electrode wiring member 27 and the negative electrode wiring member 28. You may arrange.

  The positive electrode wiring member 27 and the negative electrode wiring member 28 need only be arranged so as to overlap in parallel with the substrate 22 and in a state of being insulated from each other. Not only the structure arrange | positioned on the side which does not oppose the board | substrate 22, but it is good also as a structure by which the wiring member 27 for positive electrodes is arrange | positioned on the upper side. However, in the case of an electrolytic capacitor, since the outer side is ground, it is preferable that the negative electrode wiring member 28 is disposed on the upper side.

  A DBA (Direct Brazing Aluminum) substrate in which the metal base 20 is formed of an aluminum-based metal and an aluminum layer is formed on both sides is used as the ceramic substrate 21, and circuit patterns 24a, 24b, 24c, and 24d are formed on the surface of the DBA substrate. The back surface may be formed and brazed to the metal base 20 with an aluminum-based brazing material.

  O Instead of the ceramic substrate 21, an insulating substrate may be used in which an insulating layer is formed on the surface of a metal substrate, and circuit patterns 24a, 24b, 24c, and 24d are formed on the insulating layer.

  ○ Instead of joining the insulating substrate on the metal base 20 by soldering or brazing, an insulating layer is formed on the metal base 20 and circuit patterns 24a, 24b, 24c, 24d are formed on the insulating layer. Good. In this case, the number of parts is reduced, and the step of bonding the insulating substrate onto the metal base 20 is not necessary.

The number of capacitors 17 is not limited to four, and is determined by the rated current value of the inverter device 11 and the capacity of the capacitors used, and may be three or less or five or more.
The capacitor 17 is not limited to an electrolytic capacitor, and may be an electric double layer capacitor, for example.

The switching elements Q, Q1 to Q6 are not limited to MOSFETs, and other power transistors, for example, IGBTs (insulated gate bipolar transistors) may be used.
The group of switching elements Q and diodes D constituting each arm is not limited to four, and may be three or less or five or more depending on the amount of current flowing through each arm. Moreover, it is not limited to a plurality of sets, and may be configured by a set of a switching element Q and a diode D.

  (Circle) the inverter apparatus 11 is good also as a structure which outputs not only the structure which outputs 3 phase alternating current but single phase alternating current. In the configuration that outputs a single-phase alternating current, there are two sets of upper and lower arms.

  The pair of switching elements and diodes is not limited to the configuration packaged as one semiconductor chip 23, and the switching elements and the diodes may be mounted on the circuit pattern.

  O Each process which manufactures the inverter apparatus 11 does not need to be performed in the order demonstrated in the said embodiment. For example, the process of mounting the semiconductor chip 23 on the ceramic substrate 21 and the process of assembling the capacitor assembly 38 are separate processes, and a plurality of ceramic substrates 21 and capacitor assemblies 38 on which the semiconductor chip 23 is mounted are manufactured. May be used to manufacture the inverter device 11.

  The step of ultrasonically bonding the output electrode members 32U, 32V, 32W to the ceramic substrate 21 and the step of ultrasonically bonding the capacitor assembly 38 to the ceramic substrate 21 may be the same step. For example, a holding portion that can hold the output electrode members 32U, 32V, and 32W in a state of being positioned on the support frame 30 is provided. Then, after the output electrode members 32U, 32V, and 32W are fixed to the metal base 20 while being held by the holding portion, the ultrasonic bonding is not performed immediately, but is performed at the time of ultrasonic bonding of the capacitor assembly 38 to the ceramic substrate 21. To. Since the joint portions 35 of the output electrode members 32U, 32V, and 32W are arranged in line with the joint portions 27b and 28b of the positive electrode wiring member 27 and the negative electrode wiring member 28, a tool for ultrasonic bonding is used as the wiring member 27. , 28, the tool is in a state of facing the joints 27b, 28b, 35 in order, and ultrasonic joining can be performed efficiently.

  When the ultrasonic bonding of the output electrode members 32U, 32V, 32W to the ceramic substrate 21 is performed prior to the ultrasonic bonding of the capacitor assembly 38 to the ceramic substrate 21, the bonding portion 35 of the output electrode members 32U, 32V, 32W is positive. The wiring member 27 and the negative electrode wiring member 28 may not be arranged in line with the joint portions 27b and 28b.

  ○ Ultrasonic bonding is not limited to a method of sequentially performing each bonding point (bonding point) one by one, but may be performed by a plurality of points. In this case, it is possible to shorten the time until ultrasonic bonding of all the bonding points is completed as compared with the case where one point is performed. In particular, when performing two points at a time, the size of the ultrasonic bonding tool is not increased so much, and the number of bonding points is an even number, so that it can be performed efficiently.

(Circle) not only the inverter apparatus 11 but a power converter device may be applied to a DC-DC converter, for example.
○ When the first ends of the drive signal input terminals G1 to G6 are joined to the circuit pattern 24a and the first ends of the signal terminals S1 to S6 are joined to the circuit pattern 24d, the capacitor assembly 38 is ultrasonically applied to the ceramic substrate 21. Not only before joining, but also after the support frame 30 is fixed to the metal base 20, the support frame 30 may be filled with silicone gel.

  The joining of the positive electrode terminal 17a of the capacitor 17 and the positive electrode wiring member 27 and the bonding of the negative electrode terminal 17b and the negative electrode wiring member 28 are not limited to tightening with screws, but the influence of heat on the capacitor 17 is compared to soldering. Then, a small joining method such as precision resistance welding or laser beam welding may be used.

The following technical idea (invention) can be understood from the embodiment.
(1) pre-Symbol junction are joined by ultrasonic bonding.

(A) is a circuit diagram of an inverter, (b) is a circuit diagram of one arm. The schematic perspective view which abbreviate | omitted the cover of the inverter apparatus. FIG. (A) is the sectional view on the AA line of FIG. 3, (b) is a partially omitted partial enlarged view of (a). The partial schematic diagram which shows the state of the wire bonding of the source and gate of a semiconductor chip, and each circuit pattern. (A) is the BB sectional drawing of FIG. 3, (b) is the elements on larger scale of (a). (A) is a schematic perspective view of a ceramic substrate on which chip components are mounted, and (b) is a schematic perspective view of a metal base on which the ceramic substrate is mounted. (A) is a schematic perspective view of a state in which a support frame is attached to a metal base, and (b) is a schematic perspective view of a state in which an output electrode member is attached. The model perspective view which shows the relationship between a capacitor | condenser assembly, a metal base, a support frame, and an output electrode member. Sectional drawing of another embodiment. (A), (b) is a schematic diagram which shows the arrangement | positioning of the circuit pattern on the ceramic substrate in another embodiment, respectively. The schematic plan view of another embodiment. Similarly a schematic side view. (A) is a perspective view of a prior art, (b) is an exploded perspective view.

Explanation of symbols

  Q, Q1, Q2, Q3, Q4, Q5, Q6 ... switching element, 11 ... inverter device, 17 ... capacitor, 17a ... positive electrode terminal, 17b ... negative electrode terminal, 22 ... substrate, 23 ... semiconductor chip as switching element, 24b ... Circuit pattern as first region, 24c ... Circuit pattern as second region, 27 ... Wiring member for positive electrode, 27a, 28a ... Terminal portion, 27b, 28b, 35 ... Junction portion, 28 ... Wiring member for negative electrode, 32U , 32V, 32W ... output electrode members.

Claims (3)

A substrate on which a plurality of switching elements are mounted;
A flat plate-like positive electrode wiring member and a negative electrode wiring member which are arranged in close proximity and in parallel while being electrically insulated from each other;
A power conversion device including a capacitor having a positive electrode terminal electrically connected to the positive electrode wiring member and a negative electrode terminal electrically connected to the negative electrode wiring member;
The substrate has a first pattern in which a drain or a collector of the switching element is electrically connected and a second pattern in which a source or an emitter of the switching element is electrically connected as a circuit pattern on which the switching element is mounted. A region where at least a joint portion of the positive electrode wiring member or a joint portion of the output electrode member is joined to the first region, and a joint of at least the output electrode member of the second region corresponding to the first region A region where the portion is bonded or a region where the bonding portion of the negative electrode wiring member is bonded is adjacent in a parallel state ,
The positive electrode wiring member and the negative electrode wiring member are arranged so as to overlap in parallel with the substrate, the terminal portions extend from both ends in the width direction toward the substrate side, and the tip portion is a substrate. The capacitor is bent so as to extend in parallel with the capacitor, and the capacitor is formed on one of the positive electrode wiring member and the negative electrode wiring member that does not face the substrate. The power conversion device, wherein the negative electrode terminal is disposed on the wiring member side .   The first region and the second region are formed in a strip shape, and a plurality of the switching elements are mounted in each first region, and the source or emitter of the switching elements is connected to the second region by wire bonding. The power conversion device according to claim 1.   The power conversion device is an inverter device, and each arm includes 4N (N is a natural number) switching elements, a joint portion of the positive wiring member, a joint portion of the negative wiring member, and the output electrode member 3. The power converter according to claim 2, wherein two joint portions are provided for each arm, and 2N switching elements are mounted on the first region corresponding to each joint portion of the positive electrode wiring member. .

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