JP4346504B2 - Power conversion device with power semiconductor module - Google Patents

Description

The present invention relates to a power semiconductor module that converts alternating current into direct current or direct current into alternating current using a semiconductor circuit, and a power conversion device that includes a capacitor module that forms a direct current smoothing circuit together with the power semiconductor module. The present invention relates to a power conversion device including a power semiconductor module that is required to have a relatively small device capacity, a small size, and high reliability.

  In recent years, in order to effectively use energy resources and protect the global environment, the importance of inverter power converters has increased, and the need for smaller and more reliable inverter devices has also increased. In order to reduce the size and increase the reliability of the inverter device, it is essential to operate the power semiconductor module of the main converter efficiently. That is, it is desirable that the power semiconductor module can be energized to a value as close as possible to the allowable upper limit value of the energization rating such as the voltage and current of the power semiconductor module.

  However, in reality, due to manufacturing variations of semiconductor chips built in the power semiconductor module and external circuit factors, it is necessary to have a device configuration in which a safety margin is added to the energized current / voltage. As an external circuit factor, there is a switching surge voltage generated by circuit inductance. Since the value obtained by subtracting the surge voltage from the maximum voltage that can be applied to the semiconductor chip is the voltage that can be actually energized, the voltage that can actually be energized increases if the generated surge voltage is suppressed to a small value.

The switching surge voltage ΔV (unit V) when the switching element is turned off is expressed as follows: circuit inductance is L (unit H) and current change rate is di / dt (unit A / s).
ΔV = −L · di / dt
It is represented by

  Since the switching element is aimed at improving the switching speed and it is not preferable to suppress the current change rate, it is necessary to reduce the inductance L of the wiring. In order to reduce circuit inductance, it is necessary to reduce inductance parasitic to the internal wiring of the power semiconductor module, the internal wiring of the capacitor module, and the external wiring from the capacitor module to the semiconductor module. For this purpose, the internal wiring shape of the semiconductor module and the capacitor module, mutual positional relationship, and the shape of the external wiring are important elements, and various configurations and structures have been proposed.

  For example, a power semiconductor module is known that has a flat portion facing two conductors in parallel with each other in a housing to reduce inductance (see Patent Document 1). Similarly, there is known a power conversion device that reduces inductance by forming a laminated structure in which an insulator is sandwiched between + side terminals and − side terminals (see Patent Document 2).

The structure of the conventional power semiconductor module and inverter apparatus is demonstrated using FIGS.
FIG. 10 is a main circuit diagram of the inverter device. Here, the three-phase inverter device is targeted, and the main part from the DC input unit to the AC output unit is shown. Basically, it comprises a capacitor module 1 of a DC smoothing circuit and a power semiconductor module 2 of an orthogonal transformation circuit.

  As described above, the method for reducing the circuit inductance is to reduce the parasitic inductance in the internal wiring of the power semiconductor module, the internal wiring of the capacitor module, and the external wiring from the capacitor module to the semiconductor module.

  In FIG. 10, the inductance parasitic to the internal wiring of the power semiconductor module 2 is, for the U-phase, P side (positive side) terminal P2 to intermediate connection portion P2u to intermediate connection portion N2u to N side (negative side). This is the wiring inductance of the route of the terminal N2. Similarly, the V phase is the wiring inductance of the route of P2 to P2v to N2v to N2, and the W phase is the wiring inductance of the route of P2 to P2w to N2w to N2. It is necessary to reduce the wiring inductance of these three routes without loss.

  Moreover, the inductance parasitic to the internal wiring of the capacitor module 1 is the wiring inductance of the route from the P-side terminal P1 to the intermediate connection portion P1a to the intermediate connection portion N1a to the N-side terminal N1 when the capacitor element 1a is targeted. If the capacitor element 1b is targeted, it is the wiring inductance of the route from the P side terminal P1 to the intermediate connection portion P1b to the intermediate connection portion N1b to the N side terminal N1, and if the capacitor element 1c is targeted, the P side terminals P1 to P1. This is the wiring inductance of the route from the intermediate connection portion P1c to the intermediate connection portion N1c to the N-side terminal N1. It is necessary to reduce the wiring inductance of these three routes without loss. Here, the case where three capacitor elements are arranged in parallel is illustrated, but the concept is the same even if the number of parallel elements is four or more.

  Furthermore, the inductance parasitic to the external wiring from the capacitor module 1 to the power semiconductor module 2 is the inductance parasitic to the wiring P1 to P2 on the P side and N1 to N2 on the N side.

  As shown in FIG. 11, the overall shape of the power semiconductor module 2 is composed of a base 3 and an insulating case 4. On the insulating case 4, a P-side terminal P2, an N-side terminal N2, and output terminals u, v , W are arranged.

  As shown in FIG. 12, the inside of the insulating case 4 of the power semiconductor module 2 is arranged with a P-side conductor 5, an N-side conductor 6, and output conductors 7u, 7v, 7w as shown in the figure. Are terminals P2, N2, u, v, and w. The P-side conductor 5 and the N-side conductor 6 are provided in a laminated form insulated from each other to reduce the inductance of the DC circuit.

  FIG. 13 shows an exploded view of the P-side conductor 5, the N-side conductor 6, and the output conductors 7u, 7v, and 7w. The P-side conductor 5 and the N-side conductor 6 are configured as shown in the figure. The P-side conductor 5 is connected to the insulating substrate 40 at three locations, and the N-side conductor 6 is also connected to the insulating substrate 40 at three locations. ing.

  FIG. 14 is a trihedral view showing the shapes of the P-side conductor 5 and the N-side conductor 6. The current flows as indicated by arrows a, b, c, d, e, f, g, and h.

  The configuration on the base 3 is as shown in FIG. A collector pattern 41 and an emitter pattern 42 are provided on the insulating substrate 40, a switching chip 43 and a diode chip 44 are mounted on the collector pattern 41, and wiring between the switching chip 43 and the diode chip 44 and the emitter pattern 42 is performed by bonding wires 45. is doing. Six sets of the insulating substrates 40 are mounted on the base 3. For simplicity, FIG. 15 shows a case where one switching chip 43, two diode chips 44, and three bonding wires 45 are provided for one set of insulating substrates 40. There can be various combinations of the number of parallel installations.

  FIG. 16 is a perspective view showing a combination of the power semiconductor module 2 and the capacitor module 1. The capacitor module 1 is provided on the insulating case 4 of the power semiconductor module 2, and the capacitor module 1 includes five capacitor elements 1 a, 1 b, 1 c, 1 d, and 1 e in parallel with a P-side conductor 51 and an N-side conductor 52. It is connected and stored in the insulating case 4a. The end portion of the P-side conductor 51 constitutes a P-side terminal P1, and the end portion of the N-side conductor 52 constitutes an N-side terminal N1. Although FIG. 16 shows the case where five capacitor elements are provided, there can be various numbers of parallel installations corresponding to the energization conditions.

The shapes of the P-side conductor 51 and the N-side conductor 52 of the capacitor module 1 are so-called different shapes as shown in the exploded view of FIG. 17, and are in a common shape in the unfolded state.
JP 2000-216331 A JP 2003-197858 A

The above-described conventional power semiconductor module and inverter device have the following problems.
That is, first, it is necessary to reduce the wiring inductances of the three routes of the U phase, the V phase, and the W phase without loss. However, since there are six insulating substrates 40 in terms of circuit configuration, there is one P-side terminal P2 and one N-side terminal N2, so it is difficult to make the inductances of the three routes equal. Considering the P-side terminal P2 and the N-side terminal N2 as a reference, the inductance of the route via the U phase arranged at a close position is small, and conversely, the inductance of the route via the W phase arranged at a distant position is large.

  The power semiconductor module shown in FIGS. 11 to 15 has a structure in which inductance is reduced in consideration of such characteristics. As shown in FIGS. 12, 13, and 14, a part of the P-side conductor 5 and the N-side conductor 6 are laminated while being insulated to reduce the inductance of the DC circuit. If two conductors in which currents flowing in opposite directions flow are insulated and laminated, negative mutual inductance is generated and self-inductance can be offset. With the expectation of this effect, the conductors of P side conductor 5 and N side conductor 6 and the arrangement method are set.

  The path of current flowing through the P-side conductor 5 and the N-side conductor 6 will be described with reference to FIG. In the P-side conductor 5, the current flow from the P-side terminal P <b> 2 to the W-phase insulating substrate 40 can be indicated by a path connecting the shortest distances of approximately a → b → c → d. Similarly, in the N-side conductor 6, the current flow from the W-phase insulating substrate 40 to the N-side terminal N <b> 2 can be indicated by a path connecting the shortest distances, e → f → g → h.

  It should be noted here that firstly, the conductors in the vicinity of the P-side terminal P2 and the N-side terminal N2 corresponding to the current paths a, b, g, and h are not in a laminated structure, and the inductance of that portion is It is not to get smaller. When the P-side terminal P2 and the N-side terminal N2 are installed outside the insulating case and the current capacity as a terminal is taken into consideration, the terminal connection portion requires a certain large area and is difficult to stack.

  Secondly, considering the state in which the P-side conductor 5 and the N-side conductor 6 are laminated, the current paths c and f are separated. The P-side conductor 5 and the N-side conductor 6 are laminated in a major part, and seem to have a small inductance. However, when the current paths connecting the shortest distances are separated as shown in FIG. 14, the inductance is not reduced so much. This is because although the current density is large in the vicinity of the shortest path indicated by the arrow, the current density decreases as the distance from the shortest path increases.

  Targeting a power semiconductor module with a base 3 size of 190 mm × 150 mm, the inductance of the route from the P-side terminal P2 to the N-side terminal N2 via the W-phase insulating substrate was analytically calculated and found to be a considerably large value of 88 nH. .

  As shown in FIG. 17, in the capacitor module 1, the five capacitor elements 1 a, 1 b, 1 c, 1 d, and 1 e are connected in parallel by the P-side conductor 51 and the N-side conductor 52. The five capacitor elements are relatively large in size. For example, the P-side conductor 51 and the N-side conductor 52 are connected to the P-side conductor 51 and the N-side conductor 52 by using both ends of an oval as electrodes. , And the inductance of the wiring increases.

  As shown in FIG. 16, since the capacitor module 1 is directly mounted on the power semiconductor module 2, external wiring from the capacitor module 1 to the semiconductor module 2 (corresponding to between P1-P2 and between N1-N2 in FIG. 10). ) Does not exist in this case.

  As described above, in the conventional power semiconductor module and inverter device, since the inductance of the internal wiring of the power semiconductor module and the inductance of the internal wiring of the capacitor module are both large, the total circuit inductance is also large. . For this reason, the generated surge voltage proportional to the inductance increases, and as a result, the voltage that can be actually energized decreases. The restriction on the energizable voltage relatively increases the size of the apparatus. In addition, the repetition of a large surge voltage results in electrical stress accumulation in the element, which reduces reliability. The technical matters described above apply to the converter device in substantially the same manner.

Accordingly, an object of the present invention is to provide a power conversion device including a small and highly reliable power semiconductor module that has a small inductance parasitic on wiring, a low generated surge voltage, a high energizable voltage, and the like.

The invention of claim 1 is provided with a switching chip and diode chip on an insulating substrate, and a bridge constituted by housing a plurality of said insulating substrate in a common case, before Symbol P side wiring and N that connects the insulating substrate The side wiring is provided with a flat main conductor that is insulated from each other and provided in a laminated form, and a strip-shaped subconductor that is formed at the ends of the two main conductors and insulated from each other and provided in a laminated form, a power semiconductor module the end portions of the sub-conductors and the external connection terminal, and a capacitor element connected to a plurality of branch conductor pairs formed on the both main conductor of the power semiconductor module, and characterized in that it consists To do .

The invention according to claim 2 is characterized in that the branch conductor pair connects the main conductor and the insulating substrate .
The invention of claim 3, and the power semiconductor module, the power converter and a capacitor module that is connected to the power semiconductor module by connecting in parallel a plurality of capacitor elements, and the P-side wiring for connecting the pre-Symbol capacitor element N-side wiring is provided with mutually insulated main conductors of flat plate provided in layers, and said strip-like sub-conductors provided on the insulated laminated to each other are formed at both end portions of the main conductor , characterized in that the ends of the two sub-conductors and the external connection terminal.

ADVANTAGE OF THE INVENTION According to this invention, the power converter device provided with the small and highly reliable power semiconductor module with a small inductance parasitic on wiring, a low generated surge voltage, a high energizable voltage, can be provided.

Hereinafter, first to sixth embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
A first embodiment of the present invention will be described with reference to FIG. 1, FIG. 2, FIG. 3, and FIG.

  FIG. 1 is a perspective view showing the overall shape of the power semiconductor module 12 according to the first embodiment of the present invention, and a three-view drawing showing an internal wiring structure. FIG. 11 and FIG. 12 is supported. FIG. 2 is a perspective view and an exploded view showing a wiring conductor portion of the internal DC portion and the AC portion. These correspond to FIG. 13 of the conventional structure. FIG. 3 is a three-sided view of the DC part conductor and corresponds to FIG. 14 of the conventional structure. Further, FIG. 4 is a three-sided view showing the arrangement of the insulating substrate by removing the direct current portion and the wiring conductor portion of the alternating current portion, and corresponds to FIG. 15 of the conventional structure.

  As shown in FIGS. 1 and 2, the P-side conductor 5 and the N-side conductor 6 are composed of flat main conductors 5a and 6a that are insulated from each other and provided in a laminated manner. Band-shaped subconductors 5b and 6b are raised at the ends to be insulated and laminated, and the ends of both subconductors 5b and 6b serve as a P-side terminal P2 and an N-side terminal N2 for external connection.

  Connection conductors 5u, 5v, 5w and 6u, 6v, 6w connected to the insulating substrate 40 provided with the semiconductor elements protrude from the back surfaces of the main conductors 5a, 6a. The main conductor 6a is provided with holes 6X, 6Y, 6Z through which the connection conductors 5u, 5v, 5w of the main conductor 5a are inserted in close proximity to the connection conductors 6u, 6v, 6w.

  A current path inside the P-side conductor 5 and the N-side conductor 6 in the power semiconductor module configured as described above will be described with reference to FIG. In the P-side conductor 5, the current flow from the P-side terminal P <b> 2 to the W-phase insulating substrate 40 is a path connecting almost the shortest distance of a → b → c → d. Similarly, in the N-side conductor 6, the current flow from the W-phase insulating substrate 40 to the N-side terminal N <b> 2 is a path that connects the shortest distances, e → f → g → h.

  According to the present embodiment, the sub-conductors 5b and 6b corresponding to the currents b and g flowing in opposite directions have a laminated structure, so that the inductance in this portion can be reduced. Further, the P-side conductor 5 and the N-side conductor 6 are laminated and the currents c and f of the main conductors 5a and 6a are close to each other. As a result, a reverse current flows close to the inside of the main conductors 5a and 6a, so that the inductance in the main conductors 5a and 6a is also reduced.

  By the way, when the size of the base 3 is 190 mm × 150 mm, the inductance of the route from the P-side terminal P2 to the N-side terminal N2 via the W-phase insulating substrate 40 is analyzed and calculated to be 49 nH. It was found that the inductance can be reduced by 44% as compared with the conventional structure.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a perspective view showing the internal wiring structure of the power semiconductor module according to the second embodiment and an exploded view showing the wiring conductor portions of the direct current section and the alternating current section.

  In the present embodiment, an insulating plate 8 made of an insulating material having a high relative dielectric constant such as ceramic is provided between the main conductor 5a of the P-side conductor 5 and the main conductor 6a of the N-side conductor 6. The insulating plate 8 is provided with holes 8X, 8Y, and 8Z through which connection conductors 5u, 5v, and 5w provided in the main conductor 5a are inserted. The insulating plate 8 provided between the P-side conductor 5 and the N-side conductor 6 acts as a capacitor, and a capacitor component is provided at a position close to the switching chip 43, so that the surge voltage reduction effect is great.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a perspective view and an exploded view showing an inverter device in which the power semiconductor module 12 and the capacitor module 1 are combined, and corresponds to the conventional FIG. In the present embodiment, flat main conductors 51a and 52a in which a P-side conductor 51 and an N-side conductor 52 that connect capacitor elements 1a to 1e are provided in an insulating and laminated manner, and ends of the main conductors 51a and 52a. This is configured by strip-shaped sub-conductors 51b and 52b provided in an insulating and laminated manner, and the end portions of the sub-conductors 51b and 52b are external connection terminals P1 and N1.

  In the inverter device of the present embodiment, the main conductors 51a and 52a and the sub conductors 51b and 52b connecting the capacitor elements 1a to 1e have a laminated structure, so that the inductance of the internal wiring of the capacitor module 1 can be reduced.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a perspective view and an exploded view showing an inverter device in which the power semiconductor module 12 and the capacitor module 1 are combined, and corresponds to FIG. In the present embodiment, flat main conductors 51a and 52a in which a P-side conductor 51 and an N-side conductor 52 that connect capacitor elements 1a to 1e are provided in an insulating and laminated manner, and both ends of the main conductors 51a and 52a. In this configuration, two sets of strip-like subconductors 51b and 52b provided in an insulating and laminated manner are provided, and the end portions of the subconductors 51b and 52b at both ends are external connection terminals P1 and N1.

  Corresponding to the configuration of the capacitor module 1, two sets of sub-conductors 5 b and 6 b are formed on both ends of the P-side conductor 5 and the N-side conductor 6 of the power semiconductor module 12. The ends of the conductors 5b and 6b are two sets of external connection terminals P2 and N2. Then, two sets of external connection terminals P1, N1 of the capacitor module 1 are connected to both connection terminals P2, N2.

  The inverter device of the present embodiment has a configuration in which a capacitor wiring path is added to the W-phase insulating board 40 side together with the U-phase insulating board 40 of the power semiconductor module 12, and the wiring path for the W-phase is shortened. Compared with the embodiment, the inductance can be further reduced. Further, since the capacitor module 1 is fastened and fixed to the power semiconductor module 12 at four points on both ends, the vibration resistance strength is improved.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a perspective view showing the P-side conductor 5 and the N-side conductor 6 extracted from the power semiconductor module 12 constituting the inverter device of the present embodiment. That is, branching conductors 5c, 5d, 5e, 5f, 5g and 6c, 6d, 6e, 6f, 6g are erected on the main conductors 5a, 6a constituting the P-side conductor 5 and the N-side conductor 6, and each branch The capacitor elements 1a, 1b, 1c, 1d, and 1e are connected to the conductor.

  In the inverter device of the present embodiment, the capacitor module 1 and the power semiconductor module 12 can be integrated, the total wiring path length becomes shorter, and the inductance is further reduced as compared with the fourth embodiment. be able to.

(Sixth embodiment)
Next, a sixth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a perspective view showing the P-side conductor 5 and the N-side conductor 6 of the power semiconductor module 12 constituting the inverter device of the present embodiment. That is, three sets of branch conductors 5h, 5i, 5j and 6h, 6i connecting the main conductors 5a, 6a and the insulating substrate 40 to the lower surfaces of the main conductors 5a, 6a constituting the P-side conductor 5 and the N-side conductor 6; 6j is formed, and capacitor elements 1f, 1g, and 1h are connected to these branch conductors.

  In the inverter device according to the present embodiment, the capacitor elements 1f, 1g, and 1h can be arranged at positions closer to the switching chip 43, and a capacitor component can be applied, so that the surge voltage reduction effect is further increased.

  As mentioned above, although the 3rd to 6th embodiment demonstrated the inverter apparatus, it can be demonstrated about the converter apparatus substantially similarly.

The power semiconductor module of the 1st Embodiment of this invention is shown, (a) is a perspective view which shows the whole shape, (b) is a top view which shows an internal wiring structure, (c) is a right view of (b). , (D) is a front view of (b). The internal wiring structure of the power semiconductor module of the 1st Embodiment of this invention is shown, (a) is a perspective view, (b) is an exploded view. The direct current conductor with which the power semiconductor module of the 1st Embodiment of this invention is equipped is shown, (a), (b), (c) is a top view of a P side conductor, a right view, and a front view, (d) , (E) and (f) are a plan view, a right side view and a front view of the N-side conductor. The structure on the base with which the power semiconductor module of the 1st Embodiment of this invention is equipped is shown, (a) is a top view, (b) is a right view, (c) is a front view. The internal wiring structure of the power semiconductor module of the 2nd Embodiment of this invention is shown, (a) is a perspective view, (b) is an exploded view. The inverter apparatus of the 3rd Embodiment of this invention is shown, (a) is a perspective view of the whole, (b) is an exploded view of a capacitor module, (c) is the figure which further decomposed | disassembled (b). The inverter apparatus of the 4th Embodiment of this invention is shown, (a) is a whole perspective view, (b) is a figure which shows the state which isolate | separated the power semiconductor module and the capacitor module, (c) is the decomposition | disassembly of a capacitor module Figure. The capacitor | condenser module with which the inverter apparatus of the 5th Embodiment of this invention is equipped is shown, (a) is a whole perspective view, (b) is an exploded view. The capacitor | condenser module with which the inverter apparatus of the 6th Embodiment of this invention is provided is shown, (a) is a perspective view of the whole, (b) is an exploded view. The circuit diagram of the inverter apparatus provided with the conventional power semiconductor module. The conventional power semiconductor module is shown, (a) is a perspective view which shows the whole shape, (b) is a top view, (c) is a right view, (d) is a front view. The wiring structure inside the conventional power semiconductor module is shown, (a) is a perspective view, (b) is a plan view, (c) is a right side view, and (d) is a front view. An exploded wiring structure of a conventional power semiconductor module is shown, (a) and (e) are P-side conductors, (b) and (f) are N-side conductors, (c) is an output conductor, (d) Is a diagram showing a base. The DC conductor with which the conventional power semiconductor module is equipped is shown, (a), (b), (c) is a top view of a P side conductor, a right side view, and a front view, (d), (e), (f) These are a plan view, a right side view, and a front view of the N-side conductor. The structure on the base with which the conventional power semiconductor module is equipped is shown, (a) is a top view, (b) is a right view, (c) is a front view. The conventional inverter apparatus is shown, (a) is a perspective view which shows the whole shape, (b) is a perspective view which shows the state which removed the insulation case of the capacitor | condenser module. The disassembled perspective view of the capacitor | condenser module with which the conventional inverter apparatus is equipped.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Capacitor module, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h ... Capacitor element, 2 ... Power semiconductor module (conventional), 3 ... Base, 4, 4a ... Insulation case, 5 ... P side conductor, 6 ... N-side conductor, 5a, 6a ... main conductor, 5b, 6b ... sub conductor, 5c, 5d, 5e, 5f, 5g, 5h, 5i, 5j, 6c, 6d, 6e, 6f, 6g, 6h, 6i, 6j: Branch conductor, 5u, 5v, 5w, 6u, 6v, 6w ... Connection conductor, 6X, 6Y, 6Z ... Connection conductor insertion hole, 7u, 7v, 7w ... Output conductor, 8 ... Insulating plate, 8X, 8Y, 8Z Connection conductor insertion hole, 12 Power semiconductor module (present invention), 40 Insulating substrate, 41 Collector pattern, 42 Emitter pattern, 43 Switching chip, 44 Diode chip, 45 Bonding 51, P side conductor, 52 ... N side conductor, 51a, 52a ... main conductor, 51b, 52b ... sub conductor, P1, P2 ... P side terminal, N1, N2 ... N side terminal, P1a, P1b, P1c, P2u, P2v, P2w ... intermediate connection, N1a, N1b, N1c, N2u, N2v, N2w ... intermediate connection, u, v, w ... output terminals, a, b, c, d, e, f, g, h ... current path.

Claims (3)

Provided a switching chip and diode chip on an insulating substrate, and a bridge constituted by housing a plurality of said insulating substrate in a common case, before Symbol P side wiring and N-side wiring for connecting the insulating substrate are mutually insulated A flat plate-shaped main conductor provided in a laminated form, and a strip-shaped subconductor formed on the ends of the two main conductors and insulated from each other. a power semiconductor module with an external connection terminal,
A capacitor element connected to a plurality of branch conductor pairs formed on the two main conductors of the power semiconductor module;
A power conversion device comprising: The power converter according to claim 1, wherein the branch conductor pair connects the main conductor and the insulating substrate. In a power conversion device comprising a power semiconductor module and a capacitor module connected in parallel to a plurality of capacitor elements connected to the power semiconductor module,
P-side wiring and the N-side wiring for connecting the pre-Symbol capacitor element, and mutually insulated are laminated to provided a plate-shaped main body, the mutually insulated formed on both end portions of the main conductor laminated A power conversion device comprising: a strip-like sub-conductor provided on an end portion of the sub-conductor, wherein the end portions of both sub-conductors serve as external connection terminals.

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