WO2012096066A1 - Power semiconductor module - Google Patents

Power semiconductor module Download PDF

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Publication number
WO2012096066A1
WO2012096066A1 PCT/JP2011/077747 JP2011077747W WO2012096066A1 WO 2012096066 A1 WO2012096066 A1 WO 2012096066A1 JP 2011077747 W JP2011077747 W JP 2011077747W WO 2012096066 A1 WO2012096066 A1 WO 2012096066A1
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WO
WIPO (PCT)
Prior art keywords
ceramic wiring
power semiconductor
pattern
wiring board
semiconductor module
Prior art date
Application number
PCT/JP2011/077747
Other languages
French (fr)
Japanese (ja)
Inventor
佐藤　豊
大基 安田
健一 孝井
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カルソニックカンセイ株式会社
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Publication of WO2012096066A1 publication Critical patent/WO2012096066A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a power semiconductor module.
  • An object of the present invention is to provide a power semiconductor module that can reduce the number of components.
  • an external connection terminal for electrically connecting the power semiconductor device and the outside is interposed between the upper insulating substrate and the lower insulating substrate.
  • the external connection terminals necessary for conduction are given the function of ensuring the stress resistance performance by maintaining the distance between the upper insulating substrate and the lower insulating substrate. Can be reduced.
  • FIG. 1 is a plan view of a power semiconductor module of Example 1.
  • FIG. FIG. 2 is an arrow view taken along line S2-S2 of FIG. It is the arrow line view seen along the S3-S3 line of FIG.
  • FIG. 3 is an enlarged view of main parts of FIG. 2. It is a principal part enlarged view of FIG.
  • FIG. 2A is an exploded perspective view of a power semiconductor module before resin sealing
  • FIG. 2B is a perspective view of a lower ceramic wiring board.
  • 1 is a circuit configuration diagram of a power semiconductor module according to Embodiment 1.
  • FIG. 1 is a circuit configuration diagram of a power semiconductor module according to Embodiment 1.
  • FIG. 1 is a plan view of the power semiconductor module 1 according to the first embodiment
  • FIG. 2 is a view taken along the arrow S2-S2 in FIG. 1
  • FIG. 3 is a view taken along the arrow S3-S3 in FIG.
  • FIG. 5 is an enlarged view of the main part of FIG. 3
  • FIG. 6 is (a) an exploded perspective view of the power semiconductor module 1 before resin sealing, and (b) a perspective view of the lower ceramic wiring board.
  • the power semiconductor module 1 incorporates an upper arm and a lower arm corresponding to each phase (U phase, V phase, and W phase) of an inverter that performs PWM drive control of a three-phase AC motor for vehicle travel as the same module. It is a thing. That is, the power semiconductor module 1 forms an upper and lower arm series circuit of an inverter circuit, and a three-phase inverter circuit is formed by combining the three power semiconductor modules 1.
  • “lower” is added to the name of the member on the lower arm side
  • “upper” is added to the name of the member on the upper arm side.
  • the power semiconductor module 1 of the first embodiment includes a lower ceramic wiring substrate (lower insulating substrate) 2, an upper ceramic wiring substrate (upper insulating substrate) 3, and a lower IGBT (Insulated Gate Bipolar Transistor: insulated gate bipolar transistor) chip.
  • (Power semiconductor device) 4 upper IGBT chip (power semiconductor device) 5, lower diode chip (power semiconductor device) 6, upper diode chip (power semiconductor device) 7, lower gate terminal 8, and upper gate terminal 9
  • the P lead terminal (external connection terminal) 10, the N lead terminal (external connection terminal) 11, and the OUT lead terminal (external connection terminal) 12 are the main components.
  • the lower ceramic wiring board 2 is provided on the low thermal expansion ceramic substrate 13 and the upper surface 13a of the low thermal expansion ceramic substrate 13, and is provided on the metal pattern 14 made of Al and the lower surface 13b of the low thermal expansion ceramic substrate 13, and made of Al. And a metal pattern 15.
  • the metal pattern 14 is separated into a lower pattern 14a and an upper pattern 14b by an insulating groove 14c.
  • the upper ceramic wiring board 3 is provided on the low thermal expansion ceramic substrate 16, the upper surface 16a of the low thermal expansion ceramic substrate 16, the metal pattern 17 made of Al, the lower pattern 16b of the low thermal expansion ceramic substrate 16, and the metal made of Al.
  • a pattern 18 is separated into a lower pattern 18a and an upper pattern 18b by an insulating groove 18c.
  • the lower IGBT chip 4 is bonded to the lower pattern 14a of the lower ceramic wiring board 2 with a high-temperature solder 19 made of SnSbAgCu.
  • a spacer 20 is interposed between the lower IGBT chip 4 and the lower pattern 18a of the upper ceramic wiring board 3.
  • the spacer 20 and the lower IGBT chip 4, and the spacer 20 and the lower pattern 18a are joined by high-temperature solders 21 and 22 made of SnSbAgCu.
  • the upper IGBT chip 5 is bonded to the upper pattern 14b of the lower ceramic wiring board 2 with high-temperature solder (not shown) made of SnSbAgCu.
  • a spacer 27 is interposed between the upper IGBT chip 5 and the upper pattern 18b of the upper ceramic wiring board 3.
  • the spacer 27 and the upper IGBT chip, and the spacer 27 and the upper pattern 18b are joined with high-temperature solder (not shown) made of SnSbAgCu.
  • the lower diode chip 6 is bonded to the lower pattern 14a of the lower ceramic wiring board 2 with a high-temperature solder 23 made of SnSbAgCu.
  • a spacer 24 is interposed between the lower diode chip 6 and the lower pattern 18a of the upper ceramic wiring board 3.
  • the spacer 24 and the lower diode chip 6, and the spacer 24 and the lower pattern 18a are joined by high-temperature solders 25 and 26 made of SnSbAgCu.
  • the upper diode chip 7 is bonded to the upper pattern 14b of the lower ceramic wiring board 2 with high-temperature solder (not shown) made of SnSbAgCu.
  • a spacer 28 is interposed between the upper diode chip 7 and the upper pattern 18b of the upper ceramic wiring board 3.
  • the spacer 28 and the upper diode chip 7, and the spacer 28 and the upper pattern 18b are joined by high-temperature solder (not shown) made of SnSbAgCu.
  • the lower gate terminal 8 is a terminal for supplying a gate voltage to the gate of the lower IGBT chip 5.
  • the lower gate terminal 8 is on the lower pattern 14a side of the lower ceramic wiring substrate 2, and is joined to a plurality of patterns 14e separated by the lower pattern 14a and the insulating grooves 14d with a high-temperature solder 31 made of SnSbAgCu.
  • the lower gate terminal 8 and the lower IGBT chip 5 are joined by a bonding wire 29.
  • the upper gate terminal 9 is a terminal for supplying a gate voltage to the gate of the upper IGBT chip 5.
  • the upper gate terminal 9 is on the upper pattern 14b side of the lower ceramic wiring board 2, and is bonded to a plurality of patterns 14g separated by the upper pattern 14b and the insulating grooves 14f with high-temperature solder (not shown) made of SnSbAgCu. ing.
  • the upper gate terminal 9 and the upper IGBT chip 5 are joined by a bonding wire 30.
  • the P lead terminal 10 is a terminal connected to the positive terminal of the DC intermediate circuit, and is interposed between the lower ceramic wiring board 2 and the upper ceramic wiring board 3.
  • the leading end of the P lead terminal 10 is formed in a crank shape from a vertical extending portion 10a and a horizontal extending portion 10b.
  • the vertically extending portion 10a is bent at a right angle from the tip of the base portion 10c and extends in the direction of the lower ceramic wiring board 2.
  • the horizontal extension portion 10b is bent at a right angle from the tip of the vertical extension portion 10a and extends to the left in FIGS.
  • the horizontal extension 10b is joined to the upper pattern 14b of the lower ceramic wiring board 2 with a high-temperature solder 32 made of SnSbAgCu.
  • the base 10c is bonded to the pattern 18d of the upper ceramic wiring board 3 with a high-temperature solder 33 made of SnSbAgCu.
  • the pattern 18d is separated from the upper pattern 18b by the insulating groove 18e
  • the N lead terminal 11 is a terminal connected to the negative terminal of the DC intermediate circuit, and is interposed between the lower ceramic wiring board 2 and the upper ceramic wiring board 3.
  • the tip of the N lead terminal 11 is formed in a crank shape from a vertical extending portion 11a and a horizontal extending portion 11b.
  • the vertically extending portion 11a is bent at a right angle from the tip of the base portion 11c and extends in the direction of the lower ceramic wiring board 2.
  • the horizontal extension 11b is bent at a right angle from the tip of the vertical extension 11a and extends to the left in FIGS.
  • the base 11c is joined to the lower pattern 18a of the upper ceramic wiring board 3 with high-temperature solder (not shown) made of SnSbAgCu.
  • the horizontally extending portion 11b is joined to the pattern 14h of the lower ceramic wiring board 2 with high-temperature solder (not shown) made of SnSbAgCu.
  • the pattern 14h is separated from the lower pattern 14a by the insulating groove 14i.
  • the OUT lead terminal 12 is an AC output part of the upper and lower arm series circuit, and is interposed between the lower ceramic wiring board 2 and the upper ceramic wiring board 3.
  • the distal end of the OUT lead terminal 12 is formed in a crank shape from a vertical extending portion 12a and a horizontal extending portion 12b.
  • the vertically extending portion 12a is bent at a right angle from the tip of the base portion 12c and extends in the direction of the lower ceramic wiring board 2.
  • the horizontal extension portion 12b is bent at a right angle from the tip of the vertical extension portion 12a and extends to the right in FIGS.
  • the base 12c is joined to the upper pattern 18b of the upper ceramic wiring board 3 with a high-temperature solder 34 made of SnSbAgCu.
  • the horizontal extension 12b is joined to the lower pattern 14a of the lower ceramic wiring board 2 with a high-temperature solder 35 made of SnSbAgCu.
  • the lower ceramic wiring substrate 2 and the upper ceramic wiring substrate 3 are resin-sealed by a transfer molding method with a mold resin in which an epoxy resin is filled with a silica filler.
  • the metal pattern 15 of the lower ceramic wiring board 2 and the metal pattern 17 of the upper ceramic wiring board 3 are exposed from the sealing resin 36 formed by resin sealing.
  • the lower gate terminal 8, the upper gate terminal 9, the base portion 10c of the P lead terminal 10, the base portion 11c of the N lead terminal 11, and the base portion 12c of the OUT lead terminal 12 are exposed from the sealing resin 36.
  • the metal pattern 15 and the metal pattern 17 are in close contact with a cooler (not shown) disposed above and below the power semiconductor module 1 using heat conductive grease.
  • FIG. 7 is a circuit configuration diagram of the power semiconductor module 1.
  • the lower gate terminal 8 is connected to the gate of the lower IGBT chip 4.
  • the N lead terminal 11 is connected to the emitter of the lower IGBT chip 4 via the lower pattern 18a and the spacer 20, and is connected to the lower diode chip 6 via the lower pattern 18a and the spacer 24.
  • the OUT lead terminal 12 is connected to the collector of the lower IGBT chip 4 and the lower diode chip 6 through the lower pattern 14a.
  • the upper gate terminal 9 is connected to the gate of the upper IGBT chip 5.
  • the P lead terminal 10 is connected to the collector of the upper IGBT chip 5 and the upper diode chip 7 through the upper pattern 14b.
  • the OUT lead terminal 12 is connected to the emitter of the upper IGBT chip 5 via the lower pattern 18a and the spacer 27, and is connected to the upper diode chip 7 via the lower pattern 18a and the spacer 28.
  • the tips of the P lead terminal 10, N lead terminal 11 and OUT lead terminal 12 are formed in a crank shape and interposed between the lower ceramic wiring board 2 and the upper ceramic wiring board 3, so that each lead The distance between the lower ceramic wiring board 2 and the upper ceramic wiring board 3 is maintained by the terminals 10, 11, and 12, and the stress resistance performance can be ensured.
  • the compression force or tensile force acting between the lower ceramic wiring board 2 and the upper ceramic wiring board 3 by the lead terminals 10, 11, 12 is applied to the device (lower IGBT chip 4, upper IGBT chip 5, lower diode chip). 6. It can be dispersed other than the upper diode chip 7) and its junction.
  • the thermal stress generated at the joint of the device at the time of thermal expansion and contraction is reduced and dispersed, and the rigidity around the chip of the device is secured for the purpose of ensuring the rigidity to withstand the pressing force from the cooler.
  • a plurality of inorganic members for defining the distance between the lower ceramic wiring board and the upper ceramic wiring board are separately provided. For this reason, there was a problem that the number of parts increased.
  • the inorganic member needs to be bonded to the upper and lower ceramic wiring boards, respectively, there is a problem in that the number of man-hours increases due to the increase in the number of bonding points, and the size of the module increases due to securing the bonding area.
  • the function of ensuring the stress resistance performance is given to each lead terminal 10, 11, 12 necessary for conduction, so that a new one is ensured to ensure the stress resistance performance.
  • the joining area does not increase, the module can be prevented from being enlarged.
  • each lead terminal 10, 11, 12 is originally bonded to at least one ceramic wiring board, compared with the prior art in which the inorganic member is bonded to the upper and lower ceramic wiring boards respectively, The number of joints can be reduced, and an increase in man-hours can be suppressed.
  • the lead terminals 10, 11, 12 are connected to the lower ceramic wiring board 2.
  • the metal patterns 14 and 18 of the upper ceramic wiring board 3 are joined.
  • the P lead terminal 10 needs to be electrically connected to the metal pattern 14, but does not need to be electrically connected to the metal pattern 18.
  • the N lead terminal 11 needs to be electrically connected to the metal pattern 18, but need not be electrically connected to the metal pattern 14.
  • the pattern 18d which is the joint portion with the P lead terminal 10 in the metal pattern 18 is insulated from the upper pattern 18b, and the pattern 14h which is the joint portion with the N lead terminal 11 in the metal pattern 14 is lower pattern. Insulated from 14a. That is, since the dedicated patterns 18d and 14h for joining the P and N lead terminals 10 and 11 are provided, unnecessary electrical connection between the P and N lead terminals 10 and 11 and the metal patterns 18 and 14 is avoided, and Stress performance can be secured.
  • the power semiconductor module 1 of the first embodiment constitutes a series circuit of upper and lower arms of an inverter circuit, three power semiconductor modules 1 are combined, each P lead terminal 10 is connected to the positive terminal of the battery, and each N lead A three-phase inverter circuit can be configured by connecting the terminal 11 to the negative terminal of the battery and connecting each OUT lead terminal 12 to each phase (U phase, V phase, W phase) of the electric motor.
  • the external wiring can be simplified and the inverter circuit can be formed compactly.
  • the power semiconductor module 1 has the following effects.
  • P lead terminal 10, N lead terminal 11 and OUT lead terminal 12 for electrically connecting lower IGBT chip 4 and upper IGBT chip 5 to the outside are connected to upper ceramic wiring board 3 and lower ceramic wiring board 2. Intervened between.
  • Each lead terminal 10, 11, 12 required for conduction is given a function to maintain the distance between the upper ceramic wiring board 3 and the lower ceramic wiring board 2, so that stress resistance can be achieved without adding new components. Performance can be secured and the number of parts can be reduced.
  • an increase in the bonding area can be suppressed, an increase in the size of the module can be suppressed.
  • the number of joints can be reduced, an increase in man-hours can be suppressed.
  • the pattern 18d which is a joint portion with the P lead terminal 10 in the metal pattern 18 of the upper ceramic wiring board 3 is insulated from the upper pattern 18b, and is connected to the N lead terminal 11 in the metal pattern 14 of the lower ceramic wiring board 2.
  • the pattern 14h, which is a joint portion, was insulated from the lower pattern 14a.
  • the OUT lead terminal 12 is an AC output part of the upper and lower arm series circuit of the inverter circuit, the external wiring can be simplified and a three-phase AC inverter circuit can be formed in a compact manner.
  • the power semiconductor module of the present invention has been described above based on the embodiments.
  • the specific configuration is not limited to the embodiments, and the gist of the invention according to each claim described in the claims is described. Design changes and additions are permissible without departing.
  • the lead terminals 10, 11, and 12 are formed in a crank shape.
  • the distance between the lower ceramic wiring board 2 and the upper ceramic wiring board 3 can be secured, and the necessary minimum
  • the shape of each lead terminal can be arbitrarily set as long as a sufficient rigidity can be secured.
  • an example in which all the lead terminals 10, 11, and 12 are interposed between the lower ceramic wiring board 2 and the upper ceramic wiring board 3 is shown.
  • At least one lead terminal is connected to the lower ceramic wiring board. If it is the structure interposed between the board
  • Power semiconductor module 2 Lower ceramic wiring board (lower insulating board) 3 Upper ceramic wiring board (upper insulating board) 4 Lower IGBT chip (power semiconductor device) 5 Upper IGBT chip (power semiconductor device) 6 Lower diode chip (power semiconductor device) 7 Upper diode chip (power semiconductor device) 10 P lead terminal (external connection terminal) 11 N lead terminal (external connection terminal) 12 OUT lead terminal (external connection terminal, AC output section) 14 Metal pattern 14a Lower pattern 14h pattern 18 metal pattern 18b upper pattern 18d pattern

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)

Abstract

A power semiconductor module (1) has a lower IGBT chip (4) and an upper IGBT chip (5) disposed between an upper ceramic wiring substrate (3) and a lower ceramic wiring substrate (2). A P lead terminal (10), N lead terminal (11), and OUT lead terminal (12) that electrically connect the lower IGBT chip (4) and the upper IGBT chip (5) to the outside are mounted between the upper ceramic wiring substrate (3) and the lower ceramic wiring substrate (2).

Description

パワー半導体モジュールPower semiconductor module
　本発明は、パワー半導体モジュールに関する。 The present invention relates to a power semiconductor module.
　従来のパワー半導体モジュールは、デバイスの上下を低熱膨張のセラミック配線基板で挟み、デバイスの各チップの周囲に上下セラミック配線基板間の隙間を埋める絶縁性の無機部材を配置している。この記載に関係する技術の一例は、特許文献１に開示されている。 In the conventional power semiconductor module, the upper and lower sides of the device are sandwiched between ceramic wiring boards having a low thermal expansion, and insulating inorganic members that fill the gaps between the upper and lower ceramic wiring boards are arranged around each chip of the device. An example of a technique related to this description is disclosed in Patent Document 1.
特開2007-311441号公報JP 2007-311441
　しかしながら、上記従来技術にあっては、複数の無機部材を別途設ける必要があるため、部品数の増加を招くという問題があった。
  本発明の目的は、部品数を低減できるパワー半導体モジュールを提供することにある。 However, in the above prior art, there is a problem that an increase in the number of parts is caused because it is necessary to separately provide a plurality of inorganic members.
An object of the present invention is to provide a power semiconductor module that can reduce the number of components.
　上記目的を達成するため、本発明では、パワー半導体デバイスと外部とを電気的に接続する外部接続端子を、上側絶縁基板と下側絶縁基板との間に介装した。 In order to achieve the above object, in the present invention, an external connection terminal for electrically connecting the power semiconductor device and the outside is interposed between the upper insulating substrate and the lower insulating substrate.
　よって、本発明にあっては、導通のために必要な外部接続端子に上側絶縁基板と下側絶縁基板との間の距離を保持して耐応力性能を確保する機能を付与したため、部品数を低減できる。 Therefore, in the present invention, the external connection terminals necessary for conduction are given the function of ensuring the stress resistance performance by maintaining the distance between the upper insulating substrate and the lower insulating substrate. Can be reduced.
実施例１のパワー半導体モジュールの平面図である。1 is a plan view of a power semiconductor module of Example 1. FIG. 図１のS2-S2線に沿ってみた矢視図である。FIG. 2 is an arrow view taken along line S2-S2 of FIG. 図１のS3-S3線に沿ってみた矢視図である。It is the arrow line view seen along the S3-S3 line of FIG. 図２の要部拡大図である。FIG. 3 is an enlarged view of main parts of FIG. 2. 図３の要部拡大図である。It is a principal part enlarged view of FIG. 樹脂封止前の(a)パワー半導体モジュールの分解斜視図、(b)下側セラミック配線基板の斜視図である。FIG. 2A is an exploded perspective view of a power semiconductor module before resin sealing, and FIG. 2B is a perspective view of a lower ceramic wiring board. 実施例１のパワー半導体モジュールの回路構成図である。1 is a circuit configuration diagram of a power semiconductor module according to Embodiment 1. FIG.
　以下、本発明のパワー半導体モジュールを実施するための形態を、図面に示す実施例に基づいて説明する。
  〔実施例１〕
  まず、構成を説明する。
  図１は実施例１のパワー半導体モジュール1の平面図、図２は図１のS2-S2矢視図、図３は図１のS3-S3矢視図、図４は図２の要部拡大図、図５は図３の要部拡大図、図６は樹脂封止前の(a)パワー半導体モジュール1の分解斜視図、(b)下側セラミック配線基板の斜視図である。
  実施例１のパワー半導体モジュール1は、車両走行用の三相交流モータをPWM駆動制御するインバータの各相（U相、V相およびW相）に対応する上アームおよび下アームを同一モジュールとして内蔵したものである。つまり、パワー半導体モジュール1はインバータ回路の上下アーム直列回路を形成しており、３つのパワー半導体モジュール1を組み合わせることで三相インバータ回路が形成される。
  以下の説明では、下アーム側の部材の名称に「ロア」を付し、上アーム側の部材の名称に「アッパ」を付す。 EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing the power semiconductor module of this invention is demonstrated based on the Example shown on drawing.
[Example 1]
First, the configuration will be described.
1 is a plan view of the power semiconductor module 1 according to the first embodiment, FIG. 2 is a view taken along the arrow S2-S2 in FIG. 1, FIG. 3 is a view taken along the arrow S3-S3 in FIG. FIG. 5 is an enlarged view of the main part of FIG. 3, FIG. 6 is (a) an exploded perspective view of the power semiconductor module 1 before resin sealing, and (b) a perspective view of the lower ceramic wiring board.
The power semiconductor module 1 according to the first embodiment incorporates an upper arm and a lower arm corresponding to each phase (U phase, V phase, and W phase) of an inverter that performs PWM drive control of a three-phase AC motor for vehicle travel as the same module. It is a thing. That is, the power semiconductor module 1 forms an upper and lower arm series circuit of an inverter circuit, and a three-phase inverter circuit is formed by combining the three power semiconductor modules 1.
In the following description, “lower” is added to the name of the member on the lower arm side, and “upper” is added to the name of the member on the upper arm side.
　実施例１のパワー半導体モジュール1は、下側セラミック配線基板（下側絶縁基板）2と、上側セラミック配線基板（上側絶縁基板）3と、ロアIGBT（Insulated Gate Bipolar Transistor：絶縁ゲートバイポーラトランジスタ）チップ（パワー半導体デバイス）4と、アッパIGBTチップ（パワー半導体デバイス）5と、ロアダイオードチップ（パワー半導体デバイス）6と、アッパダイオードチップ（パワー半導体デバイス）7と、ロアゲート端子8と、アッパゲート端子9と、Pリード端子（外部接続端子）10と、Nリード端子（外部接続端子）11と、OUTリード端子（外部接続端子）12と、を主要な構成とする。 The power semiconductor module 1 of the first embodiment includes a lower ceramic wiring substrate (lower insulating substrate) 2, an upper ceramic wiring substrate (upper insulating substrate) 3, and a lower IGBT (Insulated Gate Bipolar Transistor: insulated gate bipolar transistor) chip. (Power semiconductor device) 4, upper IGBT chip (power semiconductor device) 5, lower diode chip (power semiconductor device) 6, upper diode chip (power semiconductor device) 7, lower gate terminal 8, and upper gate terminal 9 The P lead terminal (external connection terminal) 10, the N lead terminal (external connection terminal) 11, and the OUT lead terminal (external connection terminal) 12 are the main components.
　下側セラミック配線基板2は、低熱膨張セラミック基板13と、低熱膨張セラミック基板13の上面13aに設けられ、Alからなる金属パターン14と、低熱膨張セラミック基板13の下面13bに設けられ、Alからなる金属パターン15と、を有する。金属パターン14は、絶縁溝14cによってロアパターン14aとアッパパターン14bとに分離されている。
  上側セラミック配線基板3は、低熱膨張セラミック基板16と、低熱膨張セラミック基板16の上面16aに設けられ、Alからなる金属パターン17と、低熱膨張セラミック基板16の下面16bに設けられ、Alからなる金属パターン18と、を有する。金属パターン18は、絶縁溝18cによってロアパターン18aとアッパパターン18bとに分離されている。 The lower ceramic wiring board 2 is provided on the low thermal expansion ceramic substrate 13 and the upper surface 13a of the low thermal expansion ceramic substrate 13, and is provided on the metal pattern 14 made of Al and the lower surface 13b of the low thermal expansion ceramic substrate 13, and made of Al. And a metal pattern 15. The metal pattern 14 is separated into a lower pattern 14a and an upper pattern 14b by an insulating groove 14c.
The upper ceramic wiring board 3 is provided on the low thermal expansion ceramic substrate 16, the upper surface 16a of the low thermal expansion ceramic substrate 16, the metal pattern 17 made of Al, the lower pattern 16b of the low thermal expansion ceramic substrate 16, and the metal made of Al. And a pattern 18. The metal pattern 18 is separated into a lower pattern 18a and an upper pattern 18b by an insulating groove 18c.
　ロアIGBTチップ4は、下側セラミック配線基板2のロアパターン14aに対し、SnSbAgCuからなる高温はんだ19で接合されている。ロアIGBTチップ4と上側セラミック配線基板3のロアパターン18aとの間には、スペーサ20が介装されている。スペーサ20とロアIGBTチップ4、およびスペーサ20とロアパターン18aとは、SnSbAgCuからなる高温はんだ21,22で接合されている。
  アッパIGBTチップ5は、下側セラミック配線基板2のアッパパターン14bに対し、SnSbAgCuからなる高温はんだ（不図示）で接合されている。アッパIGBTチップ5と上側セラミック配線基板3のアッパパターン18bとの間には、スペーサ27が介装されている。スペーサ27とアッパIGBTチップ、およびスペーサ27とアッパパターン18bとは、SnSbAgCuからなる高温はんだ（不図示）で接合されている。 The lower IGBT chip 4 is bonded to the lower pattern 14a of the lower ceramic wiring board 2 with a high-temperature solder 19 made of SnSbAgCu. A spacer 20 is interposed between the lower IGBT chip 4 and the lower pattern 18a of the upper ceramic wiring board 3. The spacer 20 and the lower IGBT chip 4, and the spacer 20 and the lower pattern 18a are joined by high- temperature solders 21 and 22 made of SnSbAgCu.
The upper IGBT chip 5 is bonded to the upper pattern 14b of the lower ceramic wiring board 2 with high-temperature solder (not shown) made of SnSbAgCu. A spacer 27 is interposed between the upper IGBT chip 5 and the upper pattern 18b of the upper ceramic wiring board 3. The spacer 27 and the upper IGBT chip, and the spacer 27 and the upper pattern 18b are joined with high-temperature solder (not shown) made of SnSbAgCu.
　ロアダイオードチップ6は、下側セラミック配線基板2のロアパターン14aに対し、SnSbAgCuからなる高温はんだ23で接合されている。ロアダイオードチップ6と上側セラミック配線基板3のロアパターン18aとの間には、スペーサ24が介装されている。スペーサ24とロアダイオードチップ6、およびスペーサ24とロアパターン18aとは、SnSbAgCuからなる高温はんだ25,26で接合されている。
  アッパダイオードチップ7は、下側セラミック配線基板2のアッパパターン14bに対し、SnSbAgCuからなる高温はんだ（不図示）で接合されている。アッパダイオードチップ7と上側セラミック配線基板3のアッパパターン18bとの間には、スペーサ28が介装されている。スペーサ28とアッパダイオードチップ7、およびスペーサ28とアッパパターン18bとは、SnSbAgCuからなる高温はんだ（不図示）で接合されている。 The lower diode chip 6 is bonded to the lower pattern 14a of the lower ceramic wiring board 2 with a high-temperature solder 23 made of SnSbAgCu. A spacer 24 is interposed between the lower diode chip 6 and the lower pattern 18a of the upper ceramic wiring board 3. The spacer 24 and the lower diode chip 6, and the spacer 24 and the lower pattern 18a are joined by high- temperature solders 25 and 26 made of SnSbAgCu.
The upper diode chip 7 is bonded to the upper pattern 14b of the lower ceramic wiring board 2 with high-temperature solder (not shown) made of SnSbAgCu. A spacer 28 is interposed between the upper diode chip 7 and the upper pattern 18b of the upper ceramic wiring board 3. The spacer 28 and the upper diode chip 7, and the spacer 28 and the upper pattern 18b are joined by high-temperature solder (not shown) made of SnSbAgCu.
　ロアゲート端子8は、ロアIGBTチップ5のゲートにゲート電圧を供給する端子である。ロアゲート端子8は、下側セラミック配線基板2のロアパターン14a側であって、ロアパターン14aと絶縁溝14dによって分離された複数のパターン14eに対し、SnSbAgCuからなる高温はんだ31で接合されている。ロアゲート端子8とロアIGBTチップ5は、ボンディングワイヤ29により接合されている。
  アッパゲート端子9は、アッパIGBTチップ5のゲートにゲート電圧を供給する端子である。アッパゲート端子9は、下側セラミック配線基板2のアッパパターン14b側であって、アッパパターン14bと絶縁溝14fによって分離された複数のパターン14gに対し、SnSbAgCuからなる高温はんだ(不図示)で接合されている。アッパゲート端子9とアッパIGBTチップ5は、ボンディングワイヤ30により接合されている。 The lower gate terminal 8 is a terminal for supplying a gate voltage to the gate of the lower IGBT chip 5. The lower gate terminal 8 is on the lower pattern 14a side of the lower ceramic wiring substrate 2, and is joined to a plurality of patterns 14e separated by the lower pattern 14a and the insulating grooves 14d with a high-temperature solder 31 made of SnSbAgCu. The lower gate terminal 8 and the lower IGBT chip 5 are joined by a bonding wire 29.
The upper gate terminal 9 is a terminal for supplying a gate voltage to the gate of the upper IGBT chip 5. The upper gate terminal 9 is on the upper pattern 14b side of the lower ceramic wiring board 2, and is bonded to a plurality of patterns 14g separated by the upper pattern 14b and the insulating grooves 14f with high-temperature solder (not shown) made of SnSbAgCu. ing. The upper gate terminal 9 and the upper IGBT chip 5 are joined by a bonding wire 30.
　Pリード端子10は、直流中間回路の正端子に接続される端子であり、下側セラミック配線基板2と上側セラミック配線基板3との間に介装されている。Pリード端子10の先端は、垂直延在部10aと水平延在部10bとからクランク状に形成されている。垂直延在部10aは、基部10cの先端から直角に折れ曲がり、下側セラミック配線基板2の方向に延びている。水平延在部10bは、垂直延在部10aの先端から直角に折れ曲がり、図１～図５の左方に延びている。水平延在部10bは、下側セラミック配線基板2のアッパパターン14bに対し、SnSbAgCuからなる高温はんだ32で接合されている。基部10cは、上側セラミック配線基板3のパターン18dに対し、SnSbAgCuからなる高温はんだ33で接合されている。パターン18dは、絶縁溝18eによってアッパパターン18bと分離されている。 The P lead terminal 10 is a terminal connected to the positive terminal of the DC intermediate circuit, and is interposed between the lower ceramic wiring board 2 and the upper ceramic wiring board 3. The leading end of the P lead terminal 10 is formed in a crank shape from a vertical extending portion 10a and a horizontal extending portion 10b. The vertically extending portion 10a is bent at a right angle from the tip of the base portion 10c and extends in the direction of the lower ceramic wiring board 2. The horizontal extension portion 10b is bent at a right angle from the tip of the vertical extension portion 10a and extends to the left in FIGS. The horizontal extension 10b is joined to the upper pattern 14b of the lower ceramic wiring board 2 with a high-temperature solder 32 made of SnSbAgCu. The base 10c is bonded to the pattern 18d of the upper ceramic wiring board 3 with a high-temperature solder 33 made of SnSbAgCu. The pattern 18d is separated from the upper pattern 18b by the insulating groove 18e.
　Nリード端子11は、直流中間回路の負端子に接続される端子であり、下側セラミック配線基板2と上側セラミック配線基板3との間に介装されている。Nリード端子11の先端は、垂直延在部11aと水平延在部11bとからクランク状に形成されている。垂直延在部11aは、基部11cの先端から直角に折れ曲がり、下側セラミック配線基板2の方向に延びている。水平延在部11bは、垂直延在部11aの先端から直角に折れ曲がり、図１～図５の左方に延びている。基部11cは、上側セラミック配線基板3のロアパターン18aに対し、SnSbAgCuからなる高温はんだ（不図示）で接合されている。水平延在部11bは、下側セラミック配線基板2のパターン14hに対し、SnSbAgCuからなる高温はんだ（不図示）で接合されている。パターン14hは、絶縁溝14iによってロアパターン14aと分離されている。 The N lead terminal 11 is a terminal connected to the negative terminal of the DC intermediate circuit, and is interposed between the lower ceramic wiring board 2 and the upper ceramic wiring board 3. The tip of the N lead terminal 11 is formed in a crank shape from a vertical extending portion 11a and a horizontal extending portion 11b. The vertically extending portion 11a is bent at a right angle from the tip of the base portion 11c and extends in the direction of the lower ceramic wiring board 2. The horizontal extension 11b is bent at a right angle from the tip of the vertical extension 11a and extends to the left in FIGS. The base 11c is joined to the lower pattern 18a of the upper ceramic wiring board 3 with high-temperature solder (not shown) made of SnSbAgCu. The horizontally extending portion 11b is joined to the pattern 14h of the lower ceramic wiring board 2 with high-temperature solder (not shown) made of SnSbAgCu. The pattern 14h is separated from the lower pattern 14a by the insulating groove 14i.
　OUTリード端子12は、上下アーム直列回路の交流出力部であり、下側セラミック配線基板2と上側セラミック配線基板3との間に介装されている。OUTリード端子12の先端は、垂直延在部12aと水平延在部12bとからクランク状に形成されている。垂直延在部12aは、基部12cの先端から直角に折れ曲がり、下側セラミック配線基板2の方向に延びている。水平延在部12bは、垂直延在部12aの先端から直角に折れ曲がり、図１～図５の右方に延びている。基部12cは、上側セラミック配線基板3のアッパパターン18bに対し、SnSbAgCuからなる高温はんだ34で接合されている。水平延在部12bは、下側セラミック配線基板2のロアパターン14aに対し、SnSbAgCuからなる高温はんだ35で接合されている。 The OUT lead terminal 12 is an AC output part of the upper and lower arm series circuit, and is interposed between the lower ceramic wiring board 2 and the upper ceramic wiring board 3. The distal end of the OUT lead terminal 12 is formed in a crank shape from a vertical extending portion 12a and a horizontal extending portion 12b. The vertically extending portion 12a is bent at a right angle from the tip of the base portion 12c and extends in the direction of the lower ceramic wiring board 2. The horizontal extension portion 12b is bent at a right angle from the tip of the vertical extension portion 12a and extends to the right in FIGS. The base 12c is joined to the upper pattern 18b of the upper ceramic wiring board 3 with a high-temperature solder 34 made of SnSbAgCu. The horizontal extension 12b is joined to the lower pattern 14a of the lower ceramic wiring board 2 with a high-temperature solder 35 made of SnSbAgCu.
　下側セラミック配線基板2と上側セラミック配線基板3は、エポキシ樹脂にシリカの充填剤を充填したモールド樹脂でトランスファーモールド法により樹脂封止されている。下側セラミック配線基板2の金属パターン15、上側セラミック配線基板3の金属パターン17は樹脂封止により形成された封止樹脂36から露出している。また、ロアゲート端子8、アッパゲート端子9、Pリード端子10の基部10c、Nリード端子11の基部11cおよびOUTリード端子12の基部12cは、封止樹脂36から露出している。
  金属パターン15および金属パターン17は、パワー半導体モジュール1の上下に配置される図外の冷却器と熱伝導性グリスを用いて密着している。 The lower ceramic wiring substrate 2 and the upper ceramic wiring substrate 3 are resin-sealed by a transfer molding method with a mold resin in which an epoxy resin is filled with a silica filler. The metal pattern 15 of the lower ceramic wiring board 2 and the metal pattern 17 of the upper ceramic wiring board 3 are exposed from the sealing resin 36 formed by resin sealing. Further, the lower gate terminal 8, the upper gate terminal 9, the base portion 10c of the P lead terminal 10, the base portion 11c of the N lead terminal 11, and the base portion 12c of the OUT lead terminal 12 are exposed from the sealing resin 36.
The metal pattern 15 and the metal pattern 17 are in close contact with a cooler (not shown) disposed above and below the power semiconductor module 1 using heat conductive grease.
　図７は、パワー半導体モジュール1の回路構成図である。
  ロアゲート端子8は、ロアIGBTチップ4のゲートと接続されている。Nリード端子11は、ロアパターン18aとスペーサ20とを介してロアIGBTチップ4のエミッタと接続され、ロアパターン18aとスペーサ24とを介してロアダイオードチップ6と接続されている。OUTリード端子12は、ロアパターン14aを介してロアIGBTチップ4のコレクタおよびロアダイオードチップ6と接続されている。
  アッパゲート端子9は、アッパIGBTチップ5のゲートと接続されている。Pリード端子10は、アッパパターン14bを介してアッパIGBTチップ5のコレクタおよびアッパダイオードチップ7と接続されている。OUTリード端子12は、ロアパターン18aとスペーサ27とを介してアッパIGBTチップ5のエミッタと接続され、ロアパターン18aとスペーサ28とを介してアッパダイオードチップ7と接続されている。 FIG. 7 is a circuit configuration diagram of the power semiconductor module 1.
The lower gate terminal 8 is connected to the gate of the lower IGBT chip 4. The N lead terminal 11 is connected to the emitter of the lower IGBT chip 4 via the lower pattern 18a and the spacer 20, and is connected to the lower diode chip 6 via the lower pattern 18a and the spacer 24. The OUT lead terminal 12 is connected to the collector of the lower IGBT chip 4 and the lower diode chip 6 through the lower pattern 14a.
The upper gate terminal 9 is connected to the gate of the upper IGBT chip 5. The P lead terminal 10 is connected to the collector of the upper IGBT chip 5 and the upper diode chip 7 through the upper pattern 14b. The OUT lead terminal 12 is connected to the emitter of the upper IGBT chip 5 via the lower pattern 18a and the spacer 27, and is connected to the upper diode chip 7 via the lower pattern 18a and the spacer 28.
　次に、作用を説明する。
  ［リード端子による耐応力性能の確保］
  実施例１では、Pリード端子10、Nリード端子11およびOUTリード端子12の先端をクランク状に形成して下側セラミック配線基板2と上側セラミック配線基板3との間に介装したため、各リード端子10,11,12により下側セラミック配線基板2と上側セラミック配線基板3との間の距離が保持され、耐応力性能を確保できる。つまり、各リード端子10,11,12によって下側セラミック配線基板2と上側セラミック配線基板3との間に作用する圧縮や引張の力をデバイス（ロアIGBTチップ4、アッパIGBTチップ5、ロアダイオードチップ6、アッパダイオードチップ7）やその接合部以外に分散させることができる。この結果、トランスファーモールド時や使用時にモジュールが低温から高温に変動したときのデバイスの接合部に発生する熱歪を低減でき、熱疲労寿命および耐熱性の向上を図ることができる。また、冷却器を固定する際に作用する圧縮応力を分散させることができ、変形や破損を抑制できる。 Next, the operation will be described.
[Ensuring stress resistance performance with lead terminals]
In the first embodiment, the tips of the P lead terminal 10, N lead terminal 11 and OUT lead terminal 12 are formed in a crank shape and interposed between the lower ceramic wiring board 2 and the upper ceramic wiring board 3, so that each lead The distance between the lower ceramic wiring board 2 and the upper ceramic wiring board 3 is maintained by the terminals 10, 11, and 12, and the stress resistance performance can be ensured. In other words, the compression force or tensile force acting between the lower ceramic wiring board 2 and the upper ceramic wiring board 3 by the lead terminals 10, 11, 12 is applied to the device (lower IGBT chip 4, upper IGBT chip 5, lower diode chip). 6. It can be dispersed other than the upper diode chip 7) and its junction. As a result, it is possible to reduce the thermal strain generated in the joint portion of the device when the module changes from low temperature to high temperature during transfer molding or use, and to improve the thermal fatigue life and heat resistance. Moreover, the compressive stress which acts when fixing the cooler can be dispersed, and deformation and breakage can be suppressed.
　［低コスト化および小型化］
  従来のパワー半導体モジュールでは、熱膨張、収縮時においてデバイスの接合部に発生する熱応力の低減および分散、冷却器からの押圧力に耐えうる剛性の確保等を目的とし、デバイスの各チップの周囲に下側セラミック配線基板と上側セラミック配線基板との間の距離を規定する複数の無機部材を別途設けている。このため、部品数が増加するという問題があった。また、無機部材は上側および下側セラミック配線基板とそれぞれ接合する必要があるため、接合箇所の増加に伴う工数増や接合面積の確保に伴うモジュールの大型化を招くという問題があった。
  これに対し、実施例１のパワー半導体モジュール1では、導通のために必要な各リード端子10,11,12に耐応力性能を確保する機能を付与したため、耐応力性能を確保するために新たな部品を設ける必要がなく、部品数を低減できる。また、接合面積も増加しないため、モジュールの大型化を抑制できる。なお、各リード端子10,11,12は、本来から少なくとも一方のセラミック配線基板に接合されるものであるため、無機部材を上側および下側セラミック配線基板とそれぞれ接合する従来技術と比較して、接合箇所を減らすことができ、工数増を抑制できる。 [Cost reduction and miniaturization]
In the conventional power semiconductor module, the thermal stress generated at the joint of the device at the time of thermal expansion and contraction is reduced and dispersed, and the rigidity around the chip of the device is secured for the purpose of ensuring the rigidity to withstand the pressing force from the cooler. In addition, a plurality of inorganic members for defining the distance between the lower ceramic wiring board and the upper ceramic wiring board are separately provided. For this reason, there was a problem that the number of parts increased. In addition, since the inorganic member needs to be bonded to the upper and lower ceramic wiring boards, respectively, there is a problem in that the number of man-hours increases due to the increase in the number of bonding points, and the size of the module increases due to securing the bonding area.
On the other hand, in the power semiconductor module 1 of the first embodiment, the function of ensuring the stress resistance performance is given to each lead terminal 10, 11, 12 necessary for conduction, so that a new one is ensured to ensure the stress resistance performance. There is no need to provide parts, and the number of parts can be reduced. Further, since the joining area does not increase, the module can be prevented from being enlarged. In addition, since each lead terminal 10, 11, 12 is originally bonded to at least one ceramic wiring board, compared with the prior art in which the inorganic member is bonded to the upper and lower ceramic wiring boards respectively, The number of joints can be reduced, and an increase in man-hours can be suppressed.
　［リード端子の絶縁確保］
  実施例１では、各リード端子10,11,12により下側セラミック配線基板2と上側セラミック配線基板3との距離を確保するために、各リード端子10,11,12を下側セラミック配線基板2および上側セラミック配線基板3の金属パターン14,18と接合している。このうち、Pリード端子10については、金属パターン14とは電気的に接続する必要があるが、金属パターン18とは電気的に接続する必要がない。また、Nリード端子11については、金属パターン18とは電気的に接続する必要があるが、金属パターン14とは電気的に接続する必要がない。
  そこで、実施例１では、金属パターン18におけるPリード端子10との接合部分であるパターン18dをアッパパターン18bから絶縁し、金属パターン14におけるNリード端子11との接合部分であるパターン14hをロアパターン14aから絶縁した。つまり、P,Nリード端子10,11を接合する専用のパターン18d,14hを設けたため、P,Nリード端子10,11と金属パターン18,14との不要な電気的接続を回避しつつ、耐応力性能を確保できる。 [Ensuring insulation of lead terminals]
In the first embodiment, in order to secure the distance between the lower ceramic wiring board 2 and the upper ceramic wiring board 3 by the lead terminals 10, 11, 12, the lead terminals 10, 11, 12 are connected to the lower ceramic wiring board 2. The metal patterns 14 and 18 of the upper ceramic wiring board 3 are joined. Among these, the P lead terminal 10 needs to be electrically connected to the metal pattern 14, but does not need to be electrically connected to the metal pattern 18. Further, the N lead terminal 11 needs to be electrically connected to the metal pattern 18, but need not be electrically connected to the metal pattern 14.
Therefore, in the first embodiment, the pattern 18d which is the joint portion with the P lead terminal 10 in the metal pattern 18 is insulated from the upper pattern 18b, and the pattern 14h which is the joint portion with the N lead terminal 11 in the metal pattern 14 is lower pattern. Insulated from 14a. That is, since the dedicated patterns 18d and 14h for joining the P and N lead terminals 10 and 11 are provided, unnecessary electrical connection between the P and N lead terminals 10 and 11 and the metal patterns 18 and 14 is avoided, and Stress performance can be secured.
　［インバータのコンパクト化］
  実施例１のパワー半導体モジュール1は、インバータ回路の上下アーム直列回路を構成しているため、３つのパワー半導体モジュール1を組み合わせ、各Pリード端子10をバッテリの正端子と接続し、各Nリード端子11をバッテリの負端子と接続し、各OUTリード端子12を電動モータの各相（U相、V相、W相）と接続することで、三相インバータ回路を構成できる。このとき、配線のほとんどは各パワー半導体モジュール1内部の金属パターンで代用できるため、外部配線を簡略化でき、インバータ回路をコンパクトに形成できる。 [Inverter compactness]
Since the power semiconductor module 1 of the first embodiment constitutes a series circuit of upper and lower arms of an inverter circuit, three power semiconductor modules 1 are combined, each P lead terminal 10 is connected to the positive terminal of the battery, and each N lead A three-phase inverter circuit can be configured by connecting the terminal 11 to the negative terminal of the battery and connecting each OUT lead terminal 12 to each phase (U phase, V phase, W phase) of the electric motor. At this time, since most of the wiring can be substituted by the metal pattern inside each power semiconductor module 1, the external wiring can be simplified and the inverter circuit can be formed compactly.
　次に、効果を説明する。
  実施例１のパワー半導体モジュール1にあっては、以下に列挙する効果を奏する。
  (1) ロアIGBTチップ4およびアッパIGBTチップ5と外部とを電気的に接続するPリード端子10、Nリード端子11およびOUTリード端子12を、上側セラミック配線基板3と下側セラミック配線基板2との間に介装した。
  導通のために必要な各リード端子10,11,12に上側セラミック配線基板3と下側セラミック配線基板2との間の距離を保持する機能を付与したため、新たな部品を追加することなく耐応力性能を確保でき、部品数を低減できる。また、接合面積の増加が抑えられるため、モジュールの大型化を抑制できる。さらに、接合箇所を少なくできるため、工数増を抑制できる。 Next, the effect will be described.
The power semiconductor module 1 according to the first embodiment has the following effects.
(1) P lead terminal 10, N lead terminal 11 and OUT lead terminal 12 for electrically connecting lower IGBT chip 4 and upper IGBT chip 5 to the outside are connected to upper ceramic wiring board 3 and lower ceramic wiring board 2. Intervened between.
Each lead terminal 10, 11, 12 required for conduction is given a function to maintain the distance between the upper ceramic wiring board 3 and the lower ceramic wiring board 2, so that stress resistance can be achieved without adding new components. Performance can be secured and the number of parts can be reduced. Moreover, since an increase in the bonding area can be suppressed, an increase in the size of the module can be suppressed. Furthermore, since the number of joints can be reduced, an increase in man-hours can be suppressed.
　(2) 上側セラミック配線基板3の金属パターン18におけるPリード端子10との接合部分であるパターン18dをアッパパターン18bから絶縁し、下側セラミック配線基板2の金属パターン14におけるNリード端子11との接合部分であるパターン14hをロアパターン14aから絶縁した。
  これにより、P,Nリード端子10,11と金属パターン18,14との不要な電気的接続を回避しつつ、耐応力性能を確保できる。
  (3) OUTリード端子12をインバータ回路の上下アーム直列回路の交流出力部としたため、外部配線を簡略化でき、三相交流インバータ回路をコンパクトに形成できる。 (2) The pattern 18d which is a joint portion with the P lead terminal 10 in the metal pattern 18 of the upper ceramic wiring board 3 is insulated from the upper pattern 18b, and is connected to the N lead terminal 11 in the metal pattern 14 of the lower ceramic wiring board 2. The pattern 14h, which is a joint portion, was insulated from the lower pattern 14a.
As a result, it is possible to ensure stress resistance performance while avoiding unnecessary electrical connection between the P and N lead terminals 10 and 11 and the metal patterns 18 and 14.
(3) Since the OUT lead terminal 12 is an AC output part of the upper and lower arm series circuit of the inverter circuit, the external wiring can be simplified and a three-phase AC inverter circuit can be formed in a compact manner.
　（他の実施例）
  以上、本発明のパワー半導体モジュールを実施例に基づいて説明したが、具体的な構成については、実施例に限られるものではなく、特許請求の範囲に記載の各請求項に係る発明の要旨を逸脱しない限り、設計の変更や追加は許容される。
  例えば、実施例１では、各リード端子10,11,12をクランク状に形成した例を示したが、下側セラミック配線基板2と上側セラミック配線基板3との間の距離を確保でき、必要最小限の剛性が確保できれば、各リード端子の形状は任意に設定できる。
  実施例１では、全てのリード端子10,11,12を下側セラミック配線基板2と上側セラミック配線基板3との間に介装した例を示したが、少なくとも１つのリード端子を下側セラミック配線基板2と上側セラミック配線基板3との間に介装した構成であれば、実施例１で述べたリード端子による耐応力性能の確保、低コスト化および小型化の効果を得ることができる。 (Other examples)
The power semiconductor module of the present invention has been described above based on the embodiments. However, the specific configuration is not limited to the embodiments, and the gist of the invention according to each claim described in the claims is described. Design changes and additions are permissible without departing.
For example, in the first embodiment, the lead terminals 10, 11, and 12 are formed in a crank shape. However, the distance between the lower ceramic wiring board 2 and the upper ceramic wiring board 3 can be secured, and the necessary minimum The shape of each lead terminal can be arbitrarily set as long as a sufficient rigidity can be secured.
In the first embodiment, an example in which all the lead terminals 10, 11, and 12 are interposed between the lower ceramic wiring board 2 and the upper ceramic wiring board 3 is shown. However, at least one lead terminal is connected to the lower ceramic wiring board. If it is the structure interposed between the board | substrate 2 and the upper side ceramic wiring board 3, the effect of ensuring stress-resistant performance by the lead terminal described in Example 1, cost reduction, and size reduction can be acquired.
1　パワー半導体モジュール
2　下側セラミック配線基板（下側絶縁基板）
3　上側セラミック配線基板（上側絶縁基板）
4　ロアIGBTチップ（パワー半導体デバイス）
5　アッパIGBTチップ（パワー半導体デバイス）
6　ロアダイオードチップ（パワー半導体デバイス）
7　アッパダイオードチップ（パワー半導体デバイス）
10　Pリード端子（外部接続端子）
11　Nリード端子（外部接続端子）
12　OUTリード端子（外部接続端子、交流出力部）
14　金属パターン
14a　ロアパターン
14h　パターン
18　金属パターン
18b　アッパパターン
18d　パターン 1 Power semiconductor module
2 Lower ceramic wiring board (lower insulating board)
3 Upper ceramic wiring board (upper insulating board)
4 Lower IGBT chip (power semiconductor device)
5 Upper IGBT chip (power semiconductor device)
6 Lower diode chip (power semiconductor device)
7 Upper diode chip (power semiconductor device)
10 P lead terminal (external connection terminal)
11 N lead terminal (external connection terminal)
12 OUT lead terminal (external connection terminal, AC output section)
14 Metal pattern
14a Lower pattern
14h pattern
18 metal pattern
18b upper pattern
18d pattern

Claims (3)

  1. 　上側絶縁基板と下側絶縁基板との間にパワー半導体デバイスを配置したパワー半導体モジュールにおいて、
    　前記パワー半導体デバイスと外部とを電気的に接続する外部接続端子を、前記上側絶縁基板と前記下側絶縁基板との間に介装したことを特徴とするパワー半導体モジュール。     In the power semiconductor module in which the power semiconductor device is disposed between the upper insulating substrate and the lower insulating substrate,
    An external connection terminal for electrically connecting the power semiconductor device and the outside is interposed between the upper insulating substrate and the lower insulating substrate.
  2. 　請求項１に記載のパワー半導体モジュールにおいて、
    　前記上側絶縁基板および前記下側絶縁基板の金属パターンにおける前記外部接続端子との接合部分の一方を、周囲の部分から絶縁したことを特徴とするパワー半導体モジュール。     The power semiconductor module according to claim 1,
    One of the joining parts with the said external connection terminal in the metal pattern of the said upper side insulating substrate and the said lower side insulating substrate was insulated from the surrounding part.
  3. 　請求項１に記載のパワー半導体モジュールにおいて、
    　前記パワー半導体デバイスと前記金属パターンとを用いてインバータ回路の上下アーム直列回路を形成し、
    　前記外部接続端子を前記上下アーム直列回路の交流出力部としたことを特徴とするパワー半導体モジュール。     The power semiconductor module according to claim 1,
    Using the power semiconductor device and the metal pattern, an upper and lower arm series circuit of an inverter circuit is formed,
    The power semiconductor module, wherein the external connection terminal is an AC output unit of the upper and lower arm series circuit.
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