JP4640213B2 - Power semiconductor device and inverter bridge module using the same - Google Patents

Power semiconductor device and inverter bridge module using the same Download PDF

Info

Publication number
JP4640213B2
JP4640213B2 JP2006051858A JP2006051858A JP4640213B2 JP 4640213 B2 JP4640213 B2 JP 4640213B2 JP 2006051858 A JP2006051858 A JP 2006051858A JP 2006051858 A JP2006051858 A JP 2006051858A JP 4640213 B2 JP4640213 B2 JP 4640213B2
Authority
JP
Japan
Prior art keywords
power semiconductor
semiconductor device
bus bar
bridge module
inverter bridge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2006051858A
Other languages
Japanese (ja)
Other versions
JP2007236044A (en
Inventor
直樹 吉松
利彰 篠原
武志 王丸
光徳 愛甲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2006051858A priority Critical patent/JP4640213B2/en
Publication of JP2007236044A publication Critical patent/JP2007236044A/en
Application granted granted Critical
Publication of JP4640213B2 publication Critical patent/JP4640213B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73221Strap and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

この発明は、インバータ装置に使用するインバータブリッジモジュール及びそれに使用する電力半導体装置に係り、特に電力半導体装置相互を結線するバスバーの配線インダクタンス低減に関するものである。   The present invention relates to an inverter bridge module used for an inverter device and a power semiconductor device used therefor, and more particularly to reduction of wiring inductance of a bus bar connecting the power semiconductor devices.

電気自動車等の駆動源には通常モータが用いられており、モータはインバータ装置によって制御されている。このようなインバータ装置の主回路にはIGBT又はパワーMOSFET等の電力半導体装置が用いられている。特許文献1の図1には、このような電力半導体装置が、図19にはこの電力半導体装置を複数個結線した三相インバータブリッジモジュールの構成が示されている。   A motor is usually used as a drive source for an electric vehicle or the like, and the motor is controlled by an inverter device. A power semiconductor device such as an IGBT or a power MOSFET is used for a main circuit of such an inverter device. FIG. 1 of Patent Document 1 shows such a power semiconductor device, and FIG. 19 shows a configuration of a three-phase inverter bridge module in which a plurality of power semiconductor devices are connected.

特開2003−31765号公報 (図1,図19)Japanese Patent Laid-Open No. 2003-31765 (FIGS. 1 and 19)

上記特許文献の図1に示された電力半導体装置においては、コレクタ端子及びエミッタ端子の2つの主端子が筐体の一側面から引き出されている。このような電力半導体装置を6個使用し、それらを相互に結線して上記特許文献の図19に示されたような三相インバータブリッジモジュールが構成されている。この図においては、6個の電力半導体装置は3個ずつ2列に配置されており、一方の列の電力半導体装置のエミッタ端子と他方の列の電力半導体装置のコレクタ端子とが所定の間隔をおいて向かい合っている。すなわち、共通の出力端子U,V,Wに接続されるべき主端子の接続端部同士が、所定の間隔をおいて向き合っている。また、一方の列の各電力半導体装置のコレクタ端子は一列に並び共通の電源端子Pに接続されており、他方の列の各電力半導体装置のエミッタ端子は一列に並び共通の電源端子Nに接続されている。   In the power semiconductor device shown in FIG. 1 of the above-mentioned patent document, two main terminals of a collector terminal and an emitter terminal are drawn out from one side surface of the housing. Six such power semiconductor devices are used and connected to each other to form a three-phase inverter bridge module as shown in FIG. In this figure, six power semiconductor devices are arranged in two rows of three, and the emitter terminal of the power semiconductor device in one row and the collector terminal of the power semiconductor device in the other row are spaced apart from each other by a predetermined distance. Facing each other. That is, the connection ends of the main terminals to be connected to the common output terminals U, V, and W face each other at a predetermined interval. The collector terminals of the power semiconductor devices in one column are arranged in a row and connected to a common power supply terminal P, and the emitter terminals of the power semiconductor devices in the other row are arranged in a row and connected to a common power supply terminal N. Has been.

しかしながら、従来の三相インバータブリッジモジュールにおいては、対向配置されている2列の電力半導体装置の間に電源端子P,Nのバスバーだけでなく出力端子U,V,Wのバスバーも配置されているため、各バスバーの配置が複雑化するだけでなく、電源端子P,Nのバスバー間の間隔を大きくせざるを得ず、三相インバータブリッジモジュールの配線インダクタンスが十分に小さくできなかった。   However, in the conventional three-phase inverter bridge module, not only the power supply terminals P and N but also the output terminals U, V, and W are disposed between the two power semiconductor devices arranged opposite to each other. Therefore, not only is the arrangement of the bus bars complicated, but the distance between the bus bars of the power terminals P and N must be increased, and the wiring inductance of the three-phase inverter bridge module cannot be sufficiently reduced.

このように配線インダクタンスが大きくなると、インバータブリッジモジュールのスイッチング動作時における急激な電流変化(di/dt)により発生するサージ電圧が上記インダクタンスに比例して大きくなり、そのようなサージ電圧による電力半導体装置の破壊を防止するために、急激な電流変化を抑制する工夫が必要となり、そのことが電力変換の効率低下またはコストの増大を招いていた。   When the wiring inductance increases in this way, a surge voltage generated by a sudden current change (di / dt) during the switching operation of the inverter bridge module increases in proportion to the inductance, and the power semiconductor device due to such a surge voltage. In order to prevent the destruction of the power, it is necessary to devise a device for suppressing a rapid current change, which causes a reduction in power conversion efficiency or an increase in cost.

この発明は、上述のような課題を解決するためになされたもので、その目的は、インバータブリッジモジュールの構成及びそれに使用される電力半導体装置の主端子配置に工夫を加えることにより、バスバーの配線インダクタンスを減少させるとともに、小型、軽量でコストの低廉なインバータブリッジモジュールを提供しようとするものである。   The present invention has been made to solve the above-described problems, and its object is to devise the structure of the inverter bridge module and the layout of the main terminals of the power semiconductor device used therefor, thereby wiring the bus bars. An object of the present invention is to provide an inverter bridge module that reduces inductance and is small, lightweight, and low in cost.

前記の目的を達成するために、本発明に係る電力半導体装置は、互いに対向する第1の側面と第2の側面とを有する筐体と、上記筐体の第1の側面から引き出された第1の主端子と、上記筐体の第1の側面から引き出された第2の主端子と、上記筐体の第2の側面から引き出され、上記第1の主端子と上記筐体内部で電気的に接続された第3の主端子と、上記筐体内部に封入され、上記第1の主端子が電気的に接続された金属ブロックと、上記金属ブロック上にその一方の主面と接するように戴置され、その他方の主面に上記第2の主端子が電気的に接続された少なくとも1つの電力半導体素子とを備えることを特徴とする。   In order to achieve the above object, a power semiconductor device according to the present invention includes a housing having a first side surface and a second side surface facing each other, and a first part pulled out from the first side surface of the housing. 1 main terminal, a second main terminal drawn out from the first side surface of the housing, and a second main terminal drawn out from the second side surface of the housing to be electrically connected inside the first main terminal and the housing. A third main terminal connected to each other, a metal block enclosed in the housing and electrically connected to the first main terminal, and one main surface of the metal block on the metal block And having at least one power semiconductor element electrically connected to the second main terminal on the other main surface.

また、本発明に係る電力半導体装置の別の局面では、互いに対向する第1の側面と第2の側面とを有する筐体と、上記筐体の第1の側面から引き出された第1の主端子と、上記筐体の第1の側面から引き出された第2の主端子と、上記筐体の第2の側面から引き出され、上記第2の主電極と上記筐体内部で一体で接続された第3の主端子と、上記筐体内部に封入され、上記第1の主端子が電気的に接続された金属ブロックと、上記金属ブロック上にその一方の主面と接するように戴置され、その他方の主面に上記第2の主端子が電気的に接続された少なくとも1つの電力半導体素子とを備える。   In another aspect of the power semiconductor device according to the present invention, a housing having a first side surface and a second side surface facing each other, and a first main drawn out from the first side surface of the housing. A terminal, a second main terminal drawn from the first side surface of the casing, and a second side terminal of the casing, and connected integrally with the second main electrode inside the casing. A third main terminal, a metal block enclosed in the housing and electrically connected to the first main terminal, and placed on the metal block so as to be in contact with one main surface thereof. And at least one power semiconductor element having the second main terminal electrically connected to the other main surface.

さらに、本発明に係るインバータブリッジモジュールは、第1のバスバーと、上記第1のバスバーに近接して平行に並置されている第2のバスバーと、上記第1のバスバーと前記第2のバスバーのそれぞれに接続された少なくとも一対の上記本発明に係る電力半導体装置とを備えたインバータブリッジモジュールであって、上記一対の電力半導体装置は、それぞれ上記第1のバスバー又は第2のバスバーに対してその第1の側面が対向するように配置されていることを特徴とする。   Furthermore, an inverter bridge module according to the present invention includes a first bus bar, a second bus bar juxtaposed in parallel near the first bus bar, the first bus bar, and the second bus bar. An inverter bridge module comprising at least a pair of the power semiconductor devices according to the present invention connected to each of the power bus devices, wherein the pair of power semiconductor devices are respectively connected to the first bus bar or the second bus bar. It arrange | positions so that a 1st side surface may oppose.

上記のような構成としたため、本発明に係るインバータブリッジモジュールによれば、従来のインバータブリッジモジュールと比較して主電流経路を構成するバスバー配線が簡素化され、インバータブリッジモジュール固有の配線インダクタンスが小さくなり、併せてシステムの小型・軽量化が図られ、電力変換効率がよくコストの低廉なインバータブリッジモジュールが実現できる。   Due to the configuration as described above, according to the inverter bridge module according to the present invention, the bus bar wiring constituting the main current path is simplified and the wiring inductance inherent to the inverter bridge module is reduced as compared with the conventional inverter bridge module. In addition, the system can be reduced in size and weight, and an inverter bridge module with high power conversion efficiency and low cost can be realized.

<実施の形態>
以下、本発明の実施の形態を図に基づいて説明する。図1は本発明に係る三相インバータブリッジモジュールの実施の形態を示す斜視図である。図2は図1の三相インバータブリッジモジュールに使用されているバスバーの平面図(a)及び正面図(b)である。図3は図1の三相インバータブリッジモジュールに使用されている電力半導体装置の外観を示す斜視図である。図4は図1の三相インバータブリッジモジュールの回路図である。
<Embodiment>
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view showing an embodiment of a three-phase inverter bridge module according to the present invention. 2 is a plan view (a) and a front view (b) of a bus bar used in the three-phase inverter bridge module of FIG. FIG. 3 is a perspective view showing the appearance of the power semiconductor device used in the three-phase inverter bridge module of FIG. FIG. 4 is a circuit diagram of the three-phase inverter bridge module of FIG.

図1において、銅又は銅合金からなり、ストライプ形状を有し、厚みが1.5mmのPバスバー1とNバスバー2がヒートシンク3の上面のほぼ中央に設けられている。Pバスバー1とNバスバー2は互いに近接して2mmの間隔で平行に並置されており、図2に示されるように、電源と接続するためのボルト穴が形成された1つのタブ(1a又は2a)をストライプ端部の互いに対向する位置にそれぞれ有しており、さらに後述する電力半導体装置と接続するためのボルト穴が形成された3つのタブ(1b又は2b)をストライプ側部の互いに対向する位置にそれぞれ有している。Pバスバー1の3つのタブ1bには3つの電力半導体装置4が接続されている。これら3つの電力半導体装置は同一のものであるが、区別のため順に4a,4b,4cと番号を付与する。Nバスバー2の3つのタブ2bにもやはり3つの電力半導体装置4が上述した電力半導体装置4a,4b,4cとそれぞれ対向するように接続されている。これら3つの電力半導体装置は上述の電力半導体装置4a,4b,4cと同一のものであるが、区別のため順に4d,4e,4fと番号を付与する。これらの電力半導体装置4a,4b,4c及び電力半導体装置4d,4e,4fはヒートシンク3の上面に互いに所定の間隔で向かい合って固定されている。   In FIG. 1, a P bus bar 1 and an N bus bar 2 made of copper or a copper alloy, having a stripe shape, and having a thickness of 1.5 mm are provided at substantially the center of the upper surface of the heat sink 3. The P bus bar 1 and the N bus bar 2 are juxtaposed in parallel with an interval of 2 mm close to each other, and as shown in FIG. 2, one tab (1a or 2a) in which a bolt hole for connecting to a power source is formed. ) At opposite positions of the stripe end, and three tabs (1b or 2b) formed with bolt holes for connecting to a power semiconductor device to be described later are opposed to each other on the stripe side. Each has a position. Three power semiconductor devices 4 are connected to the three tabs 1 b of the P bus bar 1. These three power semiconductor devices are the same, but are numbered 4a, 4b, 4c in order for distinction. The three power semiconductor devices 4 are also connected to the three tabs 2b of the N bus bar 2 so as to face the power semiconductor devices 4a, 4b, and 4c described above. These three power semiconductor devices are the same as the power semiconductor devices 4a, 4b, and 4c described above, but numbers 4d, 4e, and 4f are given in order for distinction. The power semiconductor devices 4a, 4b, 4c and the power semiconductor devices 4d, 4e, 4f are fixed to the upper surface of the heat sink 3 so as to face each other at a predetermined interval.

電力半導体装置4は、IGBTとフリーホイールダイオードとが逆並列に接続されて1つのエポキシ樹脂の筐体9の中に封入されており、図3に示されるように、筐体9は上面と底面と4つの側面を有する直方体形状を有し、その第1の側面から主端子の1つである第1のコレクタ端子5とやはり主端子のひとつである第1のエミッタ端子6が引き出されている。上記第1側面と反対側の第2の側面からは主端子のひとつである第2のコレクタ端子7が引き出されている。図1の電力半導体装置4a,4b,4cにおいては、各電力半導体装置はその第1の側面がPバスバー1に対向するように並置され、各第1のコレクタ端子5がPバスバー1の3つのタブ1bにボルトで接続固定されており、電力半導体装置4d,4e,4fにおいては、各電力半導体装置はその第1の側面がNバスバー2に対向するように並置され、各第1のエミッタ端子6がNバスバー2の3つのタブ2bにボルトで接続固定されている。Pバスバー1とNバスバー2とを挟んで対向配置されている電力半導体装置4aの第1のエミッタ端子6と電力半導体装置4dの第1のコレクタ端子5とは、Pバスバー1及びNバスバー2の下方において適当な接続部材で橋絡することにより、互いに電気的に接続されている。電力半導体装置4d,4e,4fの各第2のコレクタ端子7は、それぞれインバータブリッジモジュールの出力端子U,V,Wを構成しており、バスバー等によりモータ等の負荷に接続される。電力半導体装置4a,4b,4cの第2のコレクタ端子7は、本実施例においてはどこにも接続されておらず、根元から切断されていてもよい。このように結線されることにより、図1のインバータブリッジモジュールは図4のような回路構成となっている。   In the power semiconductor device 4, an IGBT and a free wheel diode are connected in reverse parallel and sealed in one epoxy resin casing 9, and the casing 9 has an upper surface and a bottom surface as shown in FIG. The first collector terminal 5 which is one of the main terminals and the first emitter terminal 6 which is also one of the main terminals are drawn out from the first side face thereof. . A second collector terminal 7 which is one of the main terminals is drawn out from the second side opposite to the first side. In the power semiconductor devices 4a, 4b, and 4c in FIG. 1, each power semiconductor device is juxtaposed so that the first side faces the P bus bar 1, and each of the first collector terminals 5 includes three P bus bars 1. In the power semiconductor devices 4d, 4e, and 4f, the power semiconductor devices are juxtaposed so that the first side faces the N bus bar 2 and is connected to the tab 1b with bolts. 6 is fixedly connected to the three tabs 2b of the N bus bar 2 with bolts. The first emitter terminal 6 of the power semiconductor device 4a and the first collector terminal 5 of the power semiconductor device 4d that are arranged to face each other with the P bus bar 1 and the N bus bar 2 interposed therebetween are the P bus bar 1 and the N bus bar 2 They are electrically connected to each other by bridging with an appropriate connecting member below. The second collector terminals 7 of the power semiconductor devices 4d, 4e, and 4f respectively constitute output terminals U, V, and W of the inverter bridge module, and are connected to a load such as a motor by a bus bar or the like. The second collector terminals 7 of the power semiconductor devices 4a, 4b, 4c are not connected anywhere in the present embodiment, and may be disconnected from the base. By connecting in this way, the inverter bridge module of FIG. 1 has a circuit configuration as shown in FIG.

次に電力半導体装置4の内部構造について説明する。図5は電力半導体装置4の内部構造を示す平面図(a)とそのA−A断面図(b)である。便宜上筐体9についてはその輪郭を破線で示している。厚みが3mmの金属ブロック10の上にはダイオード素子11及びIGBT素子12が戴置されており、ダイオード素子11及びIGBT素子12の裏面と金属ブロック10の表面とが半田接合により固着されている。金属ブロック10はダイオード素子11及びIGBT素子12の支持のほかに、ダイオード素子11及びIGBT素子12から発生する熱を外部に放散させる役割や電極としての役割を担っており、そのため3〜4mm程度の厚さを有することが望ましく、熱伝導性及び電気伝導性の良好な材料が使用されている。   Next, the internal structure of the power semiconductor device 4 will be described. FIG. 5A is a plan view showing the internal structure of the power semiconductor device 4, and FIG. For convenience, the outline of the housing 9 is indicated by a broken line. The diode element 11 and the IGBT element 12 are placed on the metal block 10 having a thickness of 3 mm, and the back surface of the diode element 11 and the IGBT element 12 and the surface of the metal block 10 are fixed by soldering. In addition to supporting the diode element 11 and the IGBT element 12, the metal block 10 plays a role of dissipating heat generated from the diode element 11 and the IGBT element 12 to the outside and a role as an electrode. It is desirable to have a thickness, and materials with good thermal and electrical conductivity are used.

ダイオード素子11及びIGBT素子12の表面にはそれぞれエミッタ電極及びアノード電極が形成されており、筐体9の内部に延びている第1のエミッタ端子6とこれら電極は半田により接合されている。やはり筐体9の内部に延びている第1のコレクタ端子5及び第2のコレクタ端子7は、半田接合又は超音波接合により金属ブロック10に固着されている。補助エミッタ端子13はアルミニウム細線によるワイヤボンドによりIGBT素子12の表面のエミッタ電極に電気的に接続されており、制御端子14はIGBT素子12の表面のゲート電極に同様に電気的に接続されており、センス端子15はIGBT素子12の表面のセンスエミッタ電極に同様に電気的に接続されている。以上述べたような構造体全体を封入するようにエポキシ樹脂によりモールドし筐体9が形成されている。第1のコレクタ端子5、第2のコレクタ端子7、補助エミッタ端子13、制御端子14及びセンス端子15は、通常パターン付けされたリードフレームを用い、樹脂モールド後不要部分を切断して形成されるため、材料には加工性を重視して1mm以下の薄い銅板が使用される。   Emitter electrodes and anode electrodes are respectively formed on the surfaces of the diode element 11 and the IGBT element 12, and the first emitter terminal 6 extending into the housing 9 and these electrodes are joined by solder. The first collector terminal 5 and the second collector terminal 7 that also extend inside the housing 9 are fixed to the metal block 10 by solder bonding or ultrasonic bonding. The auxiliary emitter terminal 13 is electrically connected to the emitter electrode on the surface of the IGBT element 12 by wire bonding using a thin aluminum wire, and the control terminal 14 is electrically connected to the gate electrode on the surface of the IGBT element 12 in the same manner. The sense terminal 15 is electrically connected to the sense emitter electrode on the surface of the IGBT element 12 in the same manner. A casing 9 is formed by molding with an epoxy resin so as to enclose the entire structure as described above. The first collector terminal 5, the second collector terminal 7, the auxiliary emitter terminal 13, the control terminal 14 and the sense terminal 15 are formed by using an ordinary patterned lead frame and cutting unnecessary portions after resin molding. Therefore, a thin copper plate having a thickness of 1 mm or less is used as the material with emphasis on workability.

次に本実施の形態に係る三相インバータブリッジモジュールの動作について説明する。インバータブリッジモジュールは直流電力を任意の周波数の交流電力に電力変換をおこなう場合に用いられる。Pバスバー1には比較的高い電位を有する直流電源が、Nバスバー2には比較的低い電位を有する直流電源が接続され、これら直流電源より供給された直流電力を三相交流電力に変換して、出力端子U,V,Wからモータ等の負荷に供給する。出力端子Uに接続されている電力半導体装置4aと電力半導体装置4dとは同時に導通状態になることはないため、電力半導体装置4aは導通状態にあり電力半導体装置4dは非導通状態にあるときは、Pバスバー1から入力された主電流は電力半導体装置4aの第1のコレクタ端子5、金属ブロック10、IGBT素子12、第1のエミッタ端子6、電力半導体装置4dの第1のコレクタ端子5、金属ブロック10、第2のコレクタ端子7という電流経路を経て出力端子Uから負荷に流れ込む。このとき電力半導体装置4e及び電力半導体装置4fのいずれか又は両方が導通状態にあれば、前記主電流は負荷より出力端子V及び出力端子Wのいずれか又は両方に帰還し、電力半導体装置4e及び電力半導体装置4fのいずれか又は両方の第2のコレクタ端子7、金属ブロック10、IGBT素子12、第1のエミッタ端子6という電流経路を経てNバスバー2から直流電源に戻る。   Next, the operation of the three-phase inverter bridge module according to the present embodiment will be described. The inverter bridge module is used when DC power is converted into AC power having an arbitrary frequency. A DC power source having a relatively high potential is connected to the P bus bar 1, and a DC power source having a relatively low potential is connected to the N bus bar 2, and the DC power supplied from these DC power sources is converted into three-phase AC power. The output terminals U, V, and W are supplied to a load such as a motor. Since the power semiconductor device 4a and the power semiconductor device 4d connected to the output terminal U are not conductive at the same time, when the power semiconductor device 4a is in the conductive state and the power semiconductor device 4d is in the non-conductive state The main current input from the P bus bar 1 includes the first collector terminal 5 of the power semiconductor device 4a, the metal block 10, the IGBT element 12, the first emitter terminal 6, the first collector terminal 5 of the power semiconductor device 4d, The current flows from the output terminal U to the load through the current path of the metal block 10 and the second collector terminal 7. At this time, if either or both of the power semiconductor device 4e and the power semiconductor device 4f are in a conductive state, the main current is fed back from the load to either or both of the output terminal V and the output terminal W, and the power semiconductor device 4e and The power semiconductor device 4f returns to the DC power source from the N bus bar 2 via a current path of the second collector terminal 7, the metal block 10, the IGBT element 12, and the first emitter terminal 6 of both or both of the power semiconductor devices 4f.

同様に、出力端子Vに接続されている電力半導体装置4bと電力半導体装置4eとは同時に導通状態になることはないため、電力半導体装置4bは導通状態にあり電力半導体装置4eは非導通状態にあるときは、Pバスバー1から入力された主電流は電力半導体装置4bの第1のコレクタ端子5、金属ブロック10、IGBT素子12、第1のエミッタ端子6、電力半導体装置4eの第1のコレクタ端子5、金属ブロック10、第2のコレクタ端子7という電流経路を経て出力端子Vから負荷に流れ込む。このとき電力半導体装置4d及び電力半導体装置4fのいずれか又は両方が導通状態にあれば、前記主電流は負荷より出力端子U及び出力端子Wのいずれか又は両方に帰還し、電力半導体装置4d及び電力半導体装置4fのいずれか又は両方の第2のコレクタ端子7、金属ブロック10、IGBT素子12、第1のエミッタ端子6という電流経路を経てNバスバー2から直流電源に戻る。電力半導体装置4cが導通状態にあり電力半導体装置4fが非導通状態にあるときも同様であるので説明は省略する。   Similarly, since the power semiconductor device 4b and the power semiconductor device 4e connected to the output terminal V are not in the conductive state at the same time, the power semiconductor device 4b is in the conductive state and the power semiconductor device 4e is in the non-conductive state. In some cases, the main current input from the P bus bar 1 is the first collector terminal 5 of the power semiconductor device 4b, the metal block 10, the IGBT element 12, the first emitter terminal 6, and the first collector of the power semiconductor device 4e. The current flows from the output terminal V to the load through the current path of the terminal 5, the metal block 10, and the second collector terminal 7. At this time, if either or both of the power semiconductor device 4d and the power semiconductor device 4f are in a conductive state, the main current is fed back from the load to either or both of the output terminal U and the output terminal W, and the power semiconductor device 4d and The power semiconductor device 4f returns to the DC power source from the N bus bar 2 via a current path of the second collector terminal 7, the metal block 10, the IGBT element 12, and the first emitter terminal 6 of both or both of the power semiconductor devices 4f. The same applies when the power semiconductor device 4c is in a conducting state and the power semiconductor device 4f is in a non-conducting state, and thus the description thereof is omitted.

上記動作説明からもわかるように、このようなインバータブリッジモジュールにおいては、電源から供給される電流は常にPバスバー1及びNバスバー2を流れ、その大きさは等しく逆方向である。本実施の形態に係るインバータブリッジモジュールにおいては、構成要素である電力半導体装置4の筐体9の第1の側面から第1のコレクタ端子5及び第1のエミッタ端子6を引き出し、反対側の第2の側面から第2のコレクタ端子7を引き出しているので、出力端子U,V,Wに接続されるバスバーをPバスバー1及びNバスバー2と別の位置に配置することが可能となり、Pバスバー1とNバスバー2との間の距離を十分に小さく設定できる。これにより、バスバー配線が簡素化し、インバータブリッジモジュール全体の小型化、低コスト化ができるだけでなく、Pバスバー1及びNバスバー2それぞれの配線インダクタンスがキャンセルされ、インバータブリッジモジュール全体の配線インダクタンスが小さくなり、発生するサージ電圧が低下するため、電力変換効率がよくコストの低廉なインバータブリッジモジュールが実現できる。   As can be seen from the above description of operation, in such an inverter bridge module, the current supplied from the power supply always flows through the P bus bar 1 and the N bus bar 2, and the magnitudes thereof are equal and in the reverse direction. In the inverter bridge module according to the present embodiment, the first collector terminal 5 and the first emitter terminal 6 are drawn out from the first side surface of the housing 9 of the power semiconductor device 4 which is a component, and the opposite first Since the second collector terminal 7 is drawn out from the side surface of 2, the bus bar connected to the output terminals U, V, W can be arranged at a position different from the P bus bar 1 and the N bus bar 2, and the P bus bar The distance between 1 and the N bus bar 2 can be set sufficiently small. As a result, the bus bar wiring is simplified, the entire inverter bridge module can be reduced in size and cost, and the wiring inductance of each of the P bus bar 1 and the N bus bar 2 is canceled, and the wiring inductance of the entire inverter bridge module is reduced. Since the generated surge voltage is reduced, an inverter bridge module with high power conversion efficiency and low cost can be realized.

<変形例1>
図6は図1のインバータブリッジモジュールに使用されている電力半導体装置の変形例1の内部構造を示す平面図である。図5の電力半導体装置との相違は第1のコレクタ端子5と第2のコレクタ端子7とを金属ブロック10の対角位置に接合したことである。この変形例においても図5の電力半導体装置と同様に、その筐体9の第1の側面から第1のコレクタ端子5及び第1のエミッタ端子6を引き出し、反対側の第2の側面から第2のコレクタ端子7を引き出しているので、インバータブリッジモジュールのバスバーの簡素化や配線インダクタンスの低減に寄与することはいうまでもない。さらに、金属ブロック10には厚みの厚い銅を使用しているため、組立て工程において金属ブロック10に接合された第1のコレクタ端子5又は第2のコレクタ端子7が金属ブロック10の重量により変形し接合部に亀裂が生じるという問題点があったが、本変形例においては第1のコレクタ端子5又は第2のコレクタ端子7が金属ブロック10の対角位置に接合されており、金属ブロック10は第1のコレクタ端子5と第2のコレクタ端子7とによりバランス良く保持されるので接合部に過大な応力がかかる心配はなく、上述したような問題点も解消することができる。
<Modification 1>
FIG. 6 is a plan view showing the internal structure of Modification 1 of the power semiconductor device used in the inverter bridge module of FIG. The difference from the power semiconductor device of FIG. 5 is that the first collector terminal 5 and the second collector terminal 7 are joined to the diagonal position of the metal block 10. Also in this modified example, the first collector terminal 5 and the first emitter terminal 6 are drawn out from the first side surface of the housing 9 and the second side surface on the opposite side is used as in the power semiconductor device of FIG. Since the two collector terminals 7 are pulled out, it goes without saying that it contributes to simplification of the bus bar of the inverter bridge module and reduction of wiring inductance. Furthermore, since the thick copper is used for the metal block 10, the first collector terminal 5 or the second collector terminal 7 joined to the metal block 10 in the assembly process is deformed by the weight of the metal block 10. Although there was a problem that a crack occurs in the joint portion, in the present modification, the first collector terminal 5 or the second collector terminal 7 is joined to the diagonal position of the metal block 10, and the metal block 10 Since the first collector terminal 5 and the second collector terminal 7 are held in a well-balanced manner, there is no fear that excessive stress is applied to the joint portion, and the above-described problems can be solved.

<変形例2>
図7は図1のインバータブリッジモジュールに使用されている電力半導体装置の変形例2の内部構造を示す平面図である。図5の電力半導体装置との相違は、第2のコレクタ端子7の替わりに第2のエミッタ端子8が設けられており、第2のエミッタ端子8は第1のエミッタ端子6に一体で接続されていることである。すなわち第1のエミッタ端子6と第2のエミッタ端子8とは1つの薄い銅板からできている。この図7の電力半導体装置を図1のインバータブリッジモジュールに適用する場合には、出力端子U,V,Wの役割はそれぞれ電力半導体装置4a,4b,4cの各第2のエミッタ端子8が担うことになる。その場合の回路構成は図8のようになり、実質的に図4の回路構成と同じである。したがって、この変形例においても図5の電力半導体装置と同様に、その筐体9の第1の側面から第1のコレクタ端子5及び第1のエミッタ端子6を引き出し、反対側の第2の側面から第2のエミッタ端子8を引き出しているので、インバータブリッジモジュールのバスバーの簡素化や配線インダクタンスの低減に寄与することはいうまでもない。さらに本変形例においては、金属ブロック10と第2のエミッタ端子8との接合が不要となるため、電力半導体装置の信頼性も向上する。
<Modification 2>
FIG. 7 is a plan view showing the internal structure of Modification 2 of the power semiconductor device used in the inverter bridge module of FIG. A difference from the power semiconductor device of FIG. 5 is that a second emitter terminal 8 is provided instead of the second collector terminal 7, and the second emitter terminal 8 is integrally connected to the first emitter terminal 6. It is that. That is, the first emitter terminal 6 and the second emitter terminal 8 are made of one thin copper plate. When the power semiconductor device of FIG. 7 is applied to the inverter bridge module of FIG. 1, the roles of the output terminals U, V, and W are respectively played by the second emitter terminals 8 of the power semiconductor devices 4a, 4b, and 4c. It will be. The circuit configuration in that case is as shown in FIG. 8, which is substantially the same as the circuit configuration of FIG. Therefore, also in this modification, like the power semiconductor device of FIG. 5, the first collector terminal 5 and the first emitter terminal 6 are pulled out from the first side surface of the housing 9 and the second side surface on the opposite side. It goes without saying that the second emitter terminal 8 is led out from this, which contributes to simplification of the bus bar of the inverter bridge module and reduction of wiring inductance. Furthermore, in this modification, since the junction between the metal block 10 and the second emitter terminal 8 is not necessary, the reliability of the power semiconductor device is also improved.

以上、本発明の具体的な実施形態を説明したが、本発明はこれらに限らず種々の改変が可能である。例えば、上記実施の形態においてインバータブリッジモジュールは直流を三相交流に変換する三相ブリッジの構成であるが、直流を単相交流に変換する単相ブリッジの構成やハーフブリッジの構成とすることもできる。単相ブリッジの構成の場合は、インバータブリッジモジュールの構成は、図1において電力半導体装置4cと電力半導体装置4fを除いた構成となり、ハーフブリッジの構成の場合は、インバータブリッジモジュールの構成は、さらに電力半導体装置4cと電力半導体装置4fを除いた構成となる。すなわち、Pバスバー1とNバスバー2とを挟んだ少なくとも一対の電力半導体装置4aと電力半導体装置4dが備わっておれば、本発明の効果は発揮されることはいうまでもない。   Although specific embodiments of the present invention have been described above, the present invention is not limited to these and various modifications can be made. For example, in the above embodiment, the inverter bridge module has a three-phase bridge configuration that converts direct current to three-phase alternating current. However, a single-phase bridge configuration or a half-bridge configuration that converts direct current to single-phase alternating current may be used. it can. In the case of the single-phase bridge configuration, the configuration of the inverter bridge module is the configuration excluding the power semiconductor device 4c and the power semiconductor device 4f in FIG. 1, and in the case of the half-bridge configuration, the configuration of the inverter bridge module is further The power semiconductor device 4c and the power semiconductor device 4f are excluded. That is, it goes without saying that the effect of the present invention is exhibited as long as at least a pair of power semiconductor devices 4a and 4d sandwiching the P bus bar 1 and the N bus bar 2 are provided.

本発明に係る三相インバータブリッジモジュールの実施の形態を示す斜視図である。It is a perspective view showing an embodiment of a three-phase inverter bridge module according to the present invention. 図1の三相インバータブリッジモジュールに使用されているバスバーの平面図(a)及び正面図(b)である。It is the top view (a) and front view (b) of the bus bar which are used for the three-phase inverter bridge module of FIG. 図1の三相インバータブリッジモジュールに使用されている電力半導体装置の外観を示す斜視図である。It is a perspective view which shows the external appearance of the power semiconductor device currently used for the three-phase inverter bridge module of FIG. 図1の三相インバータブリッジモジュールの回路図である。FIG. 2 is a circuit diagram of the three-phase inverter bridge module of FIG. 1. 図3の電力半導体装置の内部構造を示す平面図(a)とそのA−A断面図(b)である。It is the top view (a) which shows the internal structure of the electric power semiconductor device of FIG. 3, and its AA sectional drawing (b). 図1の三相インバータブリッジモジュールに使用されている電力半導体装置の変形例1の内部構造を示す平面図である。It is a top view which shows the internal structure of the modification 1 of the power semiconductor device used for the three-phase inverter bridge module of FIG. 図1の三相インバータブリッジモジュールに使用されている電力半導体装置の変形例2の内部構造を示す平面図である。It is a top view which shows the internal structure of the modification 2 of the power semiconductor device used for the three-phase inverter bridge module of FIG. 図1の三相インバータブリッジモジュールに図7の電力半導体装置を適用したときの回路図である。FIG. 8 is a circuit diagram when the power semiconductor device of FIG. 7 is applied to the three-phase inverter bridge module of FIG. 1.

符号の説明Explanation of symbols

1 Pバスバー、 2 Nバスバー、 3 ヒートシンク、 4 電力半導体装置、 5 第1のコレクタ端子、 6 第1のエミッタ端子、 7 第2のコレクタ端子、 8 第2のエミッタ端子、 9 筐体、 10 金属ブロック 11 ダイオード素子 12 IGBT素子 13 補助エミッタ端子 14 制御端子 15 センス端子 。

1 P bus bar, 2 N bus bar, 3 heat sink, 4 power semiconductor device, 5 first collector terminal, 6 first emitter terminal, 7 second collector terminal, 8 second emitter terminal, 9 housing, 10 metal Block 11 Diode element 12 IGBT element 13 Auxiliary emitter terminal 14 Control terminal 15 Sense terminal

Claims (3)

互いに対向する第1の側面と第2の側面とを有する筐体と、
前記筐体の第1の側面から引き出された第1の主端子と、
前記筐体の第1の側面から引き出された第2の主端子と、
前記筐体の第2の側面から引き出され、前記第1の主端子と前記筐体内部で電気的に接続された第3の主端子と、
前記筐体内部に封入され、前記第1の主端子が電気的に接続された金属ブロックと、
前記金属ブロック上にその一方の主面と接するように戴置され、その他方の主面に前記第2の主端子が電気的に接続された少なくとも1つの電力半導体素子と、
を備える電力半導体装置。
A housing having a first side surface and a second side surface facing each other;
A first main terminal drawn from the first side surface of the housing;
A second main terminal drawn from the first side surface of the housing;
A third main terminal drawn from the second side surface of the housing and electrically connected to the first main terminal inside the housing;
A metal block enclosed in the housing and electrically connected to the first main terminal;
At least one power semiconductor element placed on the metal block so as to be in contact with one main surface and electrically connected to the second main terminal on the other main surface;
A power semiconductor device comprising:
互いに対向する第1の側面と第2の側面とを有する筐体と、
前記筐体の第1の側面から引き出された第1の主端子と、
前記筐体の第1の側面から引き出された第2の主端子と、
前記筐体の第2の側面から引き出され、前記第2の主端子と前記筐体内部で一体で接続された第3の主端子と、
前記筐体内部に封入され、前記第1の主端子が電気的に接続された金属ブロックと、
前記金属ブロック上にその一方の主面と接するように戴置され、その他方の主面に前記第2の主端子が電気的に接続された少なくとも1つの電力半導体素子と、
を備える電力半導体装置。
A housing having a first side surface and a second side surface facing each other;
A first main terminal drawn from the first side surface of the housing;
A second main terminal drawn from the first side surface of the housing;
A third main terminal pulled out from the second side surface of the casing and integrally connected to the second main terminal inside the casing;
A metal block enclosed in the housing and electrically connected to the first main terminal;
At least one power semiconductor element placed on the metal block so as to be in contact with one main surface and electrically connected to the second main terminal on the other main surface;
A power semiconductor device comprising:
第1のバスバーと、
前記第1のバスバーに近接して平行に並置されている第2のバスバーと、
前記第1のバスバーと前記第2のバスバーのそれぞれに接続された少なくとも一対の請求項1又は請求項2記載の電力半導体装置と、
を備えたインバータブリッジモジュールであって、
前記一対の電力半導体装置は、それぞれ前記第1のバスバー又は第2のバスバーに対してその第1の側面が対向するように配置されていることを特徴とするインバータブリッジモ
ジュール。
A first bus bar;
A second bus bar juxtaposed in parallel adjacent to the first bus bar;
The power semiconductor device according to claim 1 or 2, wherein the power semiconductor device is connected to each of the first bus bar and the second bus bar.
An inverter bridge module comprising:
The inverter bridge module, wherein the pair of power semiconductor devices are arranged such that the first side faces the first bus bar or the second bus bar, respectively.
JP2006051858A 2006-02-28 2006-02-28 Power semiconductor device and inverter bridge module using the same Active JP4640213B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006051858A JP4640213B2 (en) 2006-02-28 2006-02-28 Power semiconductor device and inverter bridge module using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006051858A JP4640213B2 (en) 2006-02-28 2006-02-28 Power semiconductor device and inverter bridge module using the same

Publications (2)

Publication Number Publication Date
JP2007236044A JP2007236044A (en) 2007-09-13
JP4640213B2 true JP4640213B2 (en) 2011-03-02

Family

ID=38556071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006051858A Active JP4640213B2 (en) 2006-02-28 2006-02-28 Power semiconductor device and inverter bridge module using the same

Country Status (1)

Country Link
JP (1) JP4640213B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9693476B2 (en) 2014-09-11 2017-06-27 Keihin Corporation Power conversion apparatus

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5262752B2 (en) * 2009-01-26 2013-08-14 株式会社デンソー Power converter
EP2465138B1 (en) 2009-08-10 2016-11-23 Fuji Electric Co., Ltd. Semiconductor module and cooling unit
WO2011083737A1 (en) 2010-01-05 2011-07-14 富士電機システムズ株式会社 Unit for semiconductor device, and semiconductor device
JP5464159B2 (en) 2011-03-08 2014-04-09 三菱電機株式会社 Power module
JP2013090408A (en) * 2011-10-17 2013-05-13 Denso Corp Electric power conversion device
JP6346008B2 (en) * 2014-07-03 2018-06-20 株式会社東芝 Power converter
CN106133908B (en) 2014-10-10 2018-12-25 富士电机株式会社 Semiconductor device and busbar
JP6594000B2 (en) 2015-02-26 2019-10-23 ローム株式会社 Semiconductor device
JP7172326B2 (en) 2018-09-14 2022-11-16 富士電機株式会社 Semiconductor units, semiconductor modules and semiconductor devices
JP7215265B2 (en) 2019-03-19 2023-01-31 富士電機株式会社 Semiconductor units, semiconductor modules and semiconductor devices
CN111697846B (en) * 2020-06-10 2021-08-24 中国第一汽车股份有限公司 Motor controller and vehicle

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738013A (en) * 1993-07-22 1995-02-07 Origin Electric Co Ltd Composite base member and power semiconductor device
JP2002203941A (en) * 2001-01-04 2002-07-19 Nissan Motor Co Ltd Semiconductor packaging structure
JP2003031765A (en) * 2001-07-17 2003-01-31 Hitachi Ltd Power module and inverter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738013A (en) * 1993-07-22 1995-02-07 Origin Electric Co Ltd Composite base member and power semiconductor device
JP2002203941A (en) * 2001-01-04 2002-07-19 Nissan Motor Co Ltd Semiconductor packaging structure
JP2003031765A (en) * 2001-07-17 2003-01-31 Hitachi Ltd Power module and inverter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9693476B2 (en) 2014-09-11 2017-06-27 Keihin Corporation Power conversion apparatus

Also Published As

Publication number Publication date
JP2007236044A (en) 2007-09-13

Similar Documents

Publication Publication Date Title
JP4640213B2 (en) Power semiconductor device and inverter bridge module using the same
JP5169353B2 (en) Power module
US7227259B2 (en) Low-inductance circuit arrangement for power semiconductor modules
JP6160780B2 (en) 3-level power converter
JP5263334B2 (en) Busbar module
KR20140123935A (en) Semiconductor device
EP2099120B1 (en) Power converter
JP2011151981A (en) Onboard power converter
JP2004208411A (en) Semiconductor module for half bridge circuit
JP4498170B2 (en) Semiconductor device and manufacturing method thereof
JP4885046B2 (en) Power semiconductor module
WO2005119896A1 (en) Inverter device
US10027094B2 (en) Power module, power converter and drive arrangement with a power module
JP4349364B2 (en) Semiconductor device
JP2006186170A (en) Semiconductor device
KR101734712B1 (en) Power module
JP6331294B2 (en) Semiconductor device
JP2010287737A (en) Semiconductor device
JP2020009834A (en) Semiconductor device
JP2004095769A (en) Power semiconductor device
WO2019189450A1 (en) Power conversion device
JP2013125889A (en) Semiconductor device
JP2007325387A (en) Power conversion device
JP4695041B2 (en) Semiconductor device
JP2002238260A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080521

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100716

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100803

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100901

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101102

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20101115

R151 Written notification of patent or utility model registration

Ref document number: 4640213

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131210

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250