JP6331294B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP6331294B2
JP6331294B2 JP2013181368A JP2013181368A JP6331294B2 JP 6331294 B2 JP6331294 B2 JP 6331294B2 JP 2013181368 A JP2013181368 A JP 2013181368A JP 2013181368 A JP2013181368 A JP 2013181368A JP 6331294 B2 JP6331294 B2 JP 6331294B2
Authority
JP
Japan
Prior art keywords
semiconductor
electrode
joint
solder
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013181368A
Other languages
Japanese (ja)
Other versions
JP2015050340A (en
Inventor
吉田 航也
航也 吉田
Original Assignee
株式会社ジェイテクト
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ジェイテクト filed Critical 株式会社ジェイテクト
Priority to JP2013181368A priority Critical patent/JP6331294B2/en
Publication of JP2015050340A publication Critical patent/JP2015050340A/en
Application granted granted Critical
Publication of JP6331294B2 publication Critical patent/JP6331294B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754Coating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005Shape
    • H01L2224/4007Shape of bonding interfaces, e.g. interlocking features
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8434Bonding interfaces of the connector
    • H01L2224/84345Shape, e.g. interlocking features
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Description

本発明は、半導体装置に関し、詳細には半導体装置内の配線接続における接合構造に関するものである。 The present invention relates to a semiconductor equipment, and more particularly to an junction structure in the wiring connection in the semiconductor device.
従来、直流電力と交流電力とを変換する電力変換装置として、パワーモジュール型インバータ装置が知られている。この電力変換装置のパワーモジュール(ブリッジ回路)は、複数の半導体素子(スイッチング素子)が実装された半導体装置を用いたものが提案されている(例えば、特許文献1参照)。特許文献1に記載の半導体装置は、直流電源の正極から接続されている上アームと、上アームから接続され、直流電源の負極に接続されている下アームとを並列に配設し、一体にパッケージングされた構造を有し、上下アームを一対にしてインバータ制御をおこなうものである。この半導体装置において、入力端子と電気的に接続された金属板、および出力端子と電気的に接続された導電部材(バスバー)は、それぞれ半導体素子の裏面および表面の電極にはんだを介して接合されている。また、信号端子は半導体素子の表面のゲート電極にワイヤを介して電気的に接続されている。   Conventionally, a power module type inverter device is known as a power conversion device that converts direct current power and alternating current power. As a power module (bridge circuit) of this power conversion device, one using a semiconductor device on which a plurality of semiconductor elements (switching elements) are mounted has been proposed (for example, see Patent Document 1). The semiconductor device described in Patent Document 1 includes an upper arm connected from the positive electrode of the DC power supply and a lower arm connected from the upper arm and connected to the negative electrode of the DC power supply arranged in parallel, and integrated with each other. It has a packaged structure and performs inverter control with a pair of upper and lower arms. In this semiconductor device, the metal plate electrically connected to the input terminal and the conductive member (bus bar) electrically connected to the output terminal are joined to the electrodes on the back surface and front surface of the semiconductor element via solder, respectively. ing. The signal terminal is electrically connected to the gate electrode on the surface of the semiconductor element via a wire.
特開2011−23748号公報JP 2011-23748 A
通常、上記のようなインバータ装置のパワーモジュールに使用される半導体装置は、半導体素子の接合領域が広い電極ははんだ接合で、狭い電極はアルミワイヤなどによるワイヤボンディングにより導電部材と接続されている。しかしながら、アルミワイヤと半導体素子の電極との間の接合寿命は、はんだ接合部の寿命と比較して短くなる。また、はんだ接合とワイヤボンディングとの2つの工法を用いると、製造工程が増えることにより、タクトタイムの調整、製造設備数の増加、生産ラインの拡大などが必要となったり、導電部材を装着後にワイヤボンディングにより結線しているため作業性も悪くなり、製造コストが増大する場合がある。   Usually, in a semiconductor device used in the power module of the inverter device as described above, an electrode having a wide bonding region of a semiconductor element is connected to a conductive member by solder bonding, and a narrow electrode is connected to a conductive member by wire bonding using an aluminum wire or the like. However, the joint life between the aluminum wire and the electrode of the semiconductor element is shorter than the life of the solder joint. Also, when using two methods of solder bonding and wire bonding, the number of manufacturing processes will increase, and it will be necessary to adjust the tact time, increase the number of manufacturing facilities, expand the production line, etc. Since the wires are connected by wire bonding, the workability is also deteriorated, and the manufacturing cost may increase.
さらに、配線接続の高密度化が進むにつれ、接合箇所の面積が小さくなっており、接合領域が狭い電極ではんだ接合をおこなう場合、半導体素子の電極と導電部材先端部との間の安定した隙間確保が難しく、導電部材先端部が押付けにより受ける熱応力などが原因ではんだ接合部にクラックが発生する場合がある。このように、はんだ接合部において十分な寿命、接合強度、信頼性が得られない可能性がある。   Further, as the density of wiring connection increases, the area of the joint portion is reduced, and when solder joining is performed with an electrode having a narrow joint region, a stable gap between the electrode of the semiconductor element and the conductive member tip portion It may be difficult to ensure, and cracks may occur in the solder joint due to thermal stress received at the tip of the conductive member by pressing. Thus, there is a possibility that sufficient life, bonding strength, and reliability may not be obtained at the solder joint.
本発明は、上記課題を解決するためになされたものであり、その目的は、配線接続部において、十分な接合強度が得られるとともに、生産性の高い接合構造を有し、高信頼性、低コスト化された半導体装置を提供することにある。 The present invention has been made in order to solve the above-described problems. The object of the present invention is to obtain a sufficient bonding strength in the wiring connection portion and to have a highly productive bonding structure, which has high reliability and low and to provide a cost semiconductor equipment.
上記課題を解決するために、請求項1に記載の発明は、半導体素子と、前記半導体素子を設置し、前記半導体素子の電極と電気的に接続された平板状の金属部材と、前記半導体素子の前記電極または前記金属部材と電気的に接続された平板状の金属製のバスバーと、前記金属部材の前記半導体素子とは反対側に固着され前記金属部材を絶縁するシート状の絶縁部材と、全体を封止する樹脂部材と、を備え、前記バスバーは、入出力端子に形成された複数の広い電極用接合部と、信号端子に形成された複数の狭い電極用接合部と、を有し、あらかじめ一体的に成形され、前記狭い電極用接合部は、前記半導体素子の前記電極と接合材を溶融固化した接合部を介して接合されるとともに、前記接合との接合面に所定の高さを有して一体的に形成され前記半導体素子の表面に当接する1個の突起を有し、前記突起は、前記接合部の前記狭い電極用接合部の長手方向の中心位置よりも一方向にずらした位置に配置され、前記接合部の断面形状が前記突起を挟んで前記狭い電極用接合部の長手方向に非対称に形成されることを要旨とする In order to solve the above problems, the invention according to claim 1 is a semiconductor element, a flat metal member in which the semiconductor element is installed and electrically connected to an electrode of the semiconductor element, and the semiconductor element A plate-shaped metal bus bar electrically connected to the electrode or the metal member, a sheet-like insulating member that is fixed to the opposite side of the metal member from the semiconductor element and insulates the metal member; A resin member for sealing the whole, and the bus bar includes a plurality of wide electrode joints formed on the input / output terminals and a plurality of narrow electrode joints formed on the signal terminals. The narrow electrode joint portion is integrally formed in advance and joined through the joint portion obtained by melting and solidifying the electrode and the joining material of the semiconductor element, and has a predetermined height on the joint surface with the joint portion. And integrally formed Is has one protrusion to contact with the surface of the semiconductor element, the protrusion is disposed at a position shifted in one direction than the longitudinal center position of the narrow electrode junction of the joining portion, the The gist is that the cross-sectional shape of the joint is formed asymmetrically in the longitudinal direction of the narrow electrode joint across the protrusion .
上記構成によれば、バスバーは、半導体素子の電極に電気的に接続される入出力端子の広い電極用接合部と信号端子の狭い電極用接合部とを有して、あらかじめ一体構造として成形されている。これにより、バスバーと、半導体素子の電極および金属部材との接合をすべて接合材(例えば、はんだ)を介して接続することができる。この結果、接合部の寿命、強度および信頼性が向上する。また、接合工法を統一して一括で製作できるので、工程が減少することにより製造コストを削減することができる。   According to the above configuration, the bus bar has an electrode joint with a wide input / output terminal and a electrode joint with a narrow signal terminal electrically connected to the electrode of the semiconductor element, and is molded in advance as an integral structure. ing. Thereby, all the joining of a bus-bar, the electrode of a semiconductor element, and a metal member can be connected via a joining material (for example, solder). As a result, the life, strength and reliability of the joint are improved. In addition, since the joining method can be unified and manufactured in a lump, manufacturing costs can be reduced by reducing the number of processes.
さらに、信号端子の狭い電極用接合部は、半導体素子の表面の電極に接合材を介して接続され、接合面には所定の高さを有して半導体素子の電極に当接する突起が一体に形成されている。これにより、接合部の高さ方向の隙間寸法および接合材の高さを安定させることができ、接合部は長手方向に受ける熱応力に対して強度的に耐えることができる。
Further, the electrode joint having a narrow signal terminal is connected to the electrode on the surface of the semiconductor element through a bonding material, and a protrusion having a predetermined height and contacting the electrode of the semiconductor element is integrally formed on the bonding surface. Is formed. Thereby, the gap dimension in the height direction of the joint portion and the height of the joining material can be stabilized, and the joint portion can withstand the thermal stress received in the longitudinal direction.
さらに、信号端子の狭い電極用接合部が受ける応力の方向に応じて突起の位置を非対称に変化させ、すなわち、押付けられた側に塗布される接合材の量が多くなるように突起の位置を一方にずらして配置する。これにより、バスバーとモールドされた樹脂部材との熱膨張係数の差異によって発生する力に対して、接合部が受ける長手方向の熱応力によるクラックなどの発生を防止することができる。この結果、接合部の十分な寿命、強度が得られ、信頼性の向上を図ることができる。
Furthermore, the position of the protrusion is changed asymmetrically according to the direction of the stress applied to the electrode joint having a narrow signal terminal, that is, the position of the protrusion is adjusted so that the amount of the bonding material applied to the pressed side is increased. Shift to one side. Thereby, the generation | occurrence | production of the crack by the thermal stress of the longitudinal direction which a junction part receives with respect to the force generate | occur | produced by the difference in the thermal expansion coefficient of a bus bar and the molded resin member can be prevented. As a result, a sufficient life and strength of the joint can be obtained, and reliability can be improved.
本発明によれば、半導体素子の電極とバスバーとの間の配線接続部において、十分な接合強度が得られるとともに、生産性の高い接合構造を有し、高信頼性、低コスト化された半導体装置を提供できる。 According to the present invention, in a wiring connection part between an electrode of a semiconductor element and a bus bar, a sufficient bonding strength can be obtained, and a semiconductor having a highly productive bonding structure, high reliability, and low cost. It can provide the equipment.
本発明の第1〜3の実施形態に係るインバータ装置に用いられるパワーモジュールの概略構成を示す回路図。The circuit diagram which shows schematic structure of the power module used for the inverter apparatus which concerns on the 1st-3rd embodiment of this invention. 本発明の第1〜3の実施形態に係る半導体装置の概略構成を示す平面図。The top view which shows schematic structure of the semiconductor device which concerns on the 1st-3rd embodiment of this invention. 図2におけるバスバーが形成された平板導体を示す平面図。The top view which shows the flat conductor in which the bus-bar in FIG. 2 was formed. 本発明の第1の実施形態に係る半導体装置の概略構成を示す断面図。1 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. 図4における狭い電極用接合部と半導体素子とを接合した接合部を示す拡大断面図。The expanded sectional view which shows the junction part which joined the junction part for narrow electrodes in FIG. 4, and the semiconductor element. (a)は、本発明の第2の実施形態に係る狭い電極用接合部と半導体素子とを接合した接合部を示す拡大断面図、(b)は、本発明の第3の実施形態に係る狭い電極用接合部と半導体素子とを接合した接合部を示す拡大断面図。(A) is an expanded sectional view which shows the junction part which joined the junction part for narrow electrodes and the semiconductor element which concern on the 2nd Embodiment of this invention, (b) concerns on the 3rd Embodiment of this invention. The expanded sectional view which shows the junction part which joined the junction part for narrow electrodes, and the semiconductor element.
以下、本発明の実施形態について、図に基づいて具体的に説明する。
図1は、本発明の第1〜3の実施形態に係るインバータ装置に用いられるパワーモジュール15の概略構成を示す回路図である。インバータ装置は、例えば、ハイブリッド車や電気自動車などの走行駆動モータや電動パワーステアリング装置などのブラシレスモータなどの交流負荷を駆動する電力変換装置して使用され、複数の半導体スイッチング素子からなるブリッジ回路を構成するパワーモジュール15を備えている。
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
FIG. 1 is a circuit diagram showing a schematic configuration of a power module 15 used in an inverter device according to first to third embodiments of the present invention. The inverter device is used as a power conversion device that drives an AC load such as a travel drive motor such as a hybrid vehicle or an electric vehicle or a brushless motor such as an electric power steering device, and includes a bridge circuit composed of a plurality of semiconductor switching elements. A power module 15 is provided.
図1に示すように、本実施形態では3相交流用の場合であり、パワーモジュール15は、3つの半導体装置1(1U,1V,1W)で構成されている。U相、V相、W相の各相の半導体装置1には、それぞれ半導体スイッチング素子が設けられており、半導体スイッチング素子として、例えば、素子構造にダイオードを含んでいるMOSFETが用いられる。各相毎に共通の直流電源正極端子P側からドレイン電極、ソース電極に接続されている上アーム部分と、上アームのソース電極からドレイン電極、ソース電極に接続され、共通の直流電源負極端子N側に接続されている下アーム部分とを一対にして並列に配設されている。なお、本実施形態では、上アームと下アームとを一体にして2in1パッケージングされた半導体装置1が形成されている。   As shown in FIG. 1, in this embodiment, it is a case for three-phase alternating current, and the power module 15 is comprised by the three semiconductor devices 1 (1U, 1V, 1W). The semiconductor device 1 of each phase of the U phase, the V phase, and the W phase is provided with a semiconductor switching element. As the semiconductor switching element, for example, a MOSFET including a diode in the element structure is used. An upper arm portion connected to the drain electrode and the source electrode from the common DC power source positive terminal P side for each phase, and a common DC power source negative terminal N connected to the drain electrode and the source electrode from the source electrode of the upper arm A pair of lower arm portions connected to the side are arranged in parallel. In the present embodiment, the semiconductor device 1 is formed in which the upper arm and the lower arm are integrated into a 2-in-1 package.
また、各相の上アームと下アームとの接続点(モータ端子)U,V,Wが、図示しない3相ブラシレスモータの各巻線に接続されている。さらに、半導体スイッチング素子のゲート電極(制御端子)u1,u2,v1、v2、w1、w2には、図示しない駆動回路から出力される駆動信号がそれぞれ印加される。これにより、各スイッチング素子がオン・オフ制御され、モータ端子U,V,Wに所定の周波数および電圧の3相交流電力が供給される。   Also, connection points (motor terminals) U, V, W between the upper arm and the lower arm of each phase are connected to respective windings of a three-phase brushless motor (not shown). Further, drive signals output from a drive circuit (not shown) are respectively applied to the gate electrodes (control terminals) u1, u2, v1, v2, w1, and w2 of the semiconductor switching element. Thereby, each switching element is on / off controlled, and three-phase AC power having a predetermined frequency and voltage is supplied to the motor terminals U, V, and W.
次に、図2は、本発明の第1〜3の実施形態に係るパワーモジュール15に用いられる半導体装置1の概略構成を示す平面図、図3は、図2におけるバスバー2が形成された平板導体11を示す平面図である。
図2に示す半導体装置1は、半導体スイッチング素子(以下、半導体素子という)3(3a,3b)と、半導体素子3の裏面の電極が接合された平板の四角形状の金属板(金属部材)6(6a,6b)と、半導体素子3の表面の電極および金属板6の表面に電気的に接続されたバスバー2と、金属板6の半導体素子3とは反対側(裏面)に固着された平板の四角形状の絶縁シート(絶縁部材)5と、全体を封止する樹脂部材4とを備えたパワー半導体モジュールである。
2 is a plan view showing a schematic configuration of the semiconductor device 1 used in the power module 15 according to the first to third embodiments of the present invention, and FIG. 3 is a flat plate on which the bus bar 2 in FIG. 2 is formed. 3 is a plan view showing a conductor 11. FIG.
A semiconductor device 1 shown in FIG. 2 includes a semiconductor switching element (hereinafter referred to as a semiconductor element) 3 (3a, 3b) and a flat rectangular metal plate (metal member) 6 in which electrodes on the back surface of the semiconductor element 3 are joined. (6a, 6b), the electrode on the surface of the semiconductor element 3 and the bus bar 2 electrically connected to the surface of the metal plate 6, and the flat plate fixed to the opposite side (back surface) of the metal plate 6 to the semiconductor element 3 It is a power semiconductor module provided with the square-shaped insulation sheet (insulation member) 5 and the resin member 4 which seals the whole.
半導体素子3には、例えば、MOSFETが用いられ、表裏(両)面に図示しないソース電極、ゲート電極、ドレイン電極の各電極が配置されている。本実施形態では、表面にソース電極およびゲート電極、裏面にドレイン電極がそれぞれ配置されており、2つの半導体素子3a,3bが直列に配置され一対で使用されている。各ドレイン電極、ソース電極に接続された入力端子12、出力端子13、およびゲート電極に接続された信号端子14によって、外部からの入力および外部への出力をおこなっている。半導体素子3(3a,3b)の表面のゲート電極は、信号端子14と接続されている。半導体素子3aの表面のソース電極は、入力端子12に接続され、裏面のドレイン電極は、金属板6aを介して半導体素子3bのソース電極に接続されている。また、半導体素子3bの表面のソース電極は、出力端子13に接続され、裏面のドレイン電極は、金属板6bを介して入力端子12に接続されている。なお、上記の各電極、端子間の接続は、はんだ(接合材)を介して接合されている。   For example, a MOSFET is used for the semiconductor element 3, and a source electrode, a gate electrode, and a drain electrode (not shown) are arranged on the front and back (both) surfaces. In this embodiment, a source electrode and a gate electrode are disposed on the front surface, and a drain electrode is disposed on the back surface, and two semiconductor elements 3a and 3b are disposed in series and used as a pair. Input from the outside and output to the outside are performed by each drain electrode, the input terminal 12 connected to the source electrode, the output terminal 13, and the signal terminal 14 connected to the gate electrode. The gate electrode on the surface of the semiconductor element 3 (3a, 3b) is connected to the signal terminal. The source electrode on the front surface of the semiconductor element 3a is connected to the input terminal 12, and the drain electrode on the back surface is connected to the source electrode of the semiconductor element 3b through the metal plate 6a. Further, the source electrode on the front surface of the semiconductor element 3b is connected to the output terminal 13, and the drain electrode on the back surface is connected to the input terminal 12 through the metal plate 6b. The connection between each of the electrodes and the terminals is joined via solder (joining material).
バスバー2は、入力端子12と、半導体素子3aのドレイン電極と半導体素子3bのソース電極との間を接続する配線を含む出力端子13と、信号端子14とで構成されている。バスバー2は、平板の金属材料(例えば、銅合金など)からなり、表面は金属(例えば、ニッケルなど)でめっき処理されている。   The bus bar 2 includes an input terminal 12, an output terminal 13 including a wiring connecting the drain electrode of the semiconductor element 3a and the source electrode of the semiconductor element 3b, and a signal terminal 14. The bus bar 2 is made of a flat metal material (for example, a copper alloy), and the surface thereof is plated with a metal (for example, nickel).
金属板6は、熱伝導率が高く、電気抵抗が小さい金属材料(例えば、純銅など)からなる平板であり、表面は金属(例えば、ニッケルなど)によりめっき処理されている。上記のようなMOSFETなどの半導体素子3は、大電流をスイッチング制御するため発熱量が大きいので、金属板6は放熱板としても機能する。本実施形態では、2枚の金属板6a,6bにそれぞれ1つの半導体素子3a,3bが搭載されて裏面のドレイン電極にはんだを介して接合されている。   The metal plate 6 is a flat plate made of a metal material (for example, pure copper) having high thermal conductivity and low electrical resistance, and the surface thereof is plated with a metal (for example, nickel). Since the semiconductor element 3 such as a MOSFET as described above has a large amount of heat generation because it controls switching of a large current, the metal plate 6 also functions as a heat sink. In the present embodiment, one semiconductor element 3a, 3b is mounted on each of the two metal plates 6a, 6b and joined to the drain electrode on the back surface via solder.
2枚の金属板6a,6bを絶縁するために金属板6a,6bの裏面に固着された絶縁シート5は、例えば、エポキシ樹脂などが用いられる。金属板6a,6bの裏面側に図示しない放熱板やヒートシンクなどが密着して設けられ、絶縁シート5は、金属板6a,6bとヒートシンクなどとの間を絶縁するとともに、半導体素子3a,3bでの発熱は金属板6a,6bおよび絶縁シート5を伝わって放熱され、半導体素子3a,3bの温度上昇を抑制することができる。   For the insulating sheet 5 fixed to the back surfaces of the metal plates 6a and 6b in order to insulate the two metal plates 6a and 6b, for example, an epoxy resin is used. A heat sink or a heat sink (not shown) is provided in close contact with the back side of the metal plates 6a and 6b, and the insulating sheet 5 insulates the metal plates 6a and 6b from the heat sink and the like, and includes the semiconductor elements 3a and 3b. This heat is transmitted through the metal plates 6a and 6b and the insulating sheet 5 to be dissipated to suppress the temperature rise of the semiconductor elements 3a and 3b.
図3に示すように、バスバー2はあらかじめ平板導体11に一体成形されており、入力端子12、出力端子13にソース電極および金属板6a,6bに接続される複数(本実施形態では、4箇所)の広い電極用接合部7と、信号端子14にゲート電極に接続される複数(本実施形態では、2箇所)の狭い電極用接合部8とが、それぞれ形成されている。平板導体11は、半導体素子3a,3bの表面の各電極および金属板6a,6bにはんだを介して接合された後、切り離されてバスバー2の入力端子12、出力端子13、および信号端子14(図2参照)が形成される。   As shown in FIG. 3, the bus bar 2 is integrally formed with the flat conductor 11 in advance, and the input terminal 12 and the output terminal 13 are connected to the source electrode and the metal plates 6a and 6b (in this embodiment, four locations). ) Wide electrode joints 7 and a plurality (two in this embodiment) of narrow electrode joints 8 connected to the gate electrode of the signal terminal 14 are formed. The flat conductor 11 is joined to the respective electrodes on the surfaces of the semiconductor elements 3a and 3b and the metal plates 6a and 6b via solder, and then cut off to be separated from the input terminal 12, the output terminal 13 and the signal terminal 14 ( 2) is formed.
半導体装置1全体を封止する樹脂部材4は、樹脂材料(例えば、エポキシ、PPS、PBTなど)を用いてパッケージ構造に形成されている。   The resin member 4 for sealing the entire semiconductor device 1 is formed in a package structure using a resin material (for example, epoxy, PPS, PBT, etc.).
次に、図4は、本発明の第1の実施形態に係る半導体装置1の概略構成を示す断面図、図5は、図4における狭い電極用接合部8と半導体素子3とを接合したはんだ接合部9を示す拡大断面図である。
図4に示すように、半導体素子3a,3bの表裏面の電極の接合面、および金属板6a,6bの表面と入力端子12および出力端子13との接合面は、はんだを介して接合されている。
Next, FIG. 4 is a cross-sectional view showing a schematic configuration of the semiconductor device 1 according to the first embodiment of the present invention, and FIG. 5 is a solder that joins the narrow electrode joint 8 and the semiconductor element 3 in FIG. FIG. 6 is an enlarged cross-sectional view showing a joint portion 9.
As shown in FIG. 4, the joining surfaces of the front and back electrodes of the semiconductor elements 3a and 3b, and the joining surfaces of the metal plates 6a and 6b and the input terminals 12 and the output terminals 13 are joined via solder. Yes.
図5に示すように、信号端子14の狭い電極用接合部8には、半導体素子3の表面に当接するように所定の高さを有して突起10が、例えば、曲げにより一体成形されている。この狭い電極用接合部8の長手方向に突起10の両側に溶融したはんだが充填され、固化されて、高さ方向の隙間(はんだ高さ)が安定した状態で半導体素子3と信号端子14とが接合され断面が台形状のはんだ接合部9が形成される。これにより、高さ方向のはんだ塗布量を一定にして長手方向に発生する熱応力に対するはんだ接合部9の接合強度を大きくすることができる。ここで、狭い電極用接合部8は、例えば、厚さ0.4mm程度の平板であり、はんだ接合部9は、例えば、0.1mm程度のはんだ高さで形成されている。   As shown in FIG. 5, a projection 10 having a predetermined height so as to abut the surface of the semiconductor element 3 is integrally formed by bending, for example, at the narrow electrode joint 8 of the signal terminal 14. Yes. The melted solder is filled on both sides of the protrusion 10 in the longitudinal direction of the narrow electrode joint 8 and solidified, and the semiconductor element 3 and the signal terminal 14 are in a state where the gap in the height direction (solder height) is stable. Are joined to form a solder joint 9 having a trapezoidal cross section. As a result, it is possible to increase the bonding strength of the solder joint portion 9 against the thermal stress generated in the longitudinal direction with a constant amount of solder applied in the height direction. Here, the narrow electrode joint portion 8 is a flat plate having a thickness of about 0.4 mm, for example, and the solder joint portion 9 is formed with a solder height of about 0.1 mm, for example.
次に、図6(a)は、本発明の第2の実施形態に係る狭い電極用接合部8と半導体素子3とを接合したはんだ接合部9を示す拡大断面図、図6(b)は、本発明の第3の実施形態に係る狭い電極用接合部8と半導体素子3とを接合したはんだ接合部9を示す拡大断面図である。はんだ接合状態において、信号端子14の先端部は、主に長手方向(図中、矢印方向)の熱応力を受ける。信号端子14先端部の狭い電極用接合部8は、例えば、バスバー2とモールドされた樹脂部材4(図2参照)との熱膨張係数の差異により長手方向の応力を受けると、はんだ接合部9は大きな接合強度が必要となる。   Next, FIG. 6A is an enlarged cross-sectional view showing a solder joint 9 obtained by joining the narrow electrode joint 8 and the semiconductor element 3 according to the second embodiment of the present invention, and FIG. FIG. 7 is an enlarged cross-sectional view showing a solder joint 9 obtained by joining a narrow electrode joint 8 and a semiconductor element 3 according to a third embodiment of the present invention. In the solder joint state, the distal end portion of the signal terminal 14 is mainly subjected to thermal stress in the longitudinal direction (the arrow direction in the figure). When the electrode joint 8 having a narrow tip of the signal terminal 14 receives stress in the longitudinal direction due to a difference in thermal expansion coefficient between the bus bar 2 and the molded resin member 4 (see FIG. 2), for example, the solder joint 9 Requires a large bonding strength.
図6(a),(b)に示すように、信号端子14先端部の狭い電極用接合部8が受ける熱応力の方向に対応して突起10を中心位置から一方向にずらしてはんだ接合部9の断面形状を非対称に形成する。すなわち、応力方向(図中、矢印で示す)側のはんだ接合部9の断面形状が大きくなるように突起10の位置を変更する。これにより、押付けられた側(応力方向)の接合面積が大幅に拡大し、はんだの塗布量が増加することにより、はんだ接合部9の接合強度が大きくなる。   As shown in FIGS. 6A and 6B, the solder joints are formed by shifting the protrusions 10 from the center position in one direction corresponding to the direction of the thermal stress received by the narrow electrode joint 8 at the tip of the signal terminal 14. The cross-sectional shape of 9 is formed asymmetrically. That is, the position of the protrusion 10 is changed so that the cross-sectional shape of the solder joint 9 on the stress direction (indicated by the arrow in the drawing) side is increased. As a result, the bonding area on the pressed side (stress direction) is greatly enlarged, and the amount of solder applied increases, thereby increasing the bonding strength of the solder bonding portion 9.
次に、上記のように構成された本発明の第1〜3の実施形態に係る半導体装置1の作用および効果について説明する。   Next, operations and effects of the semiconductor device 1 according to the first to third embodiments of the present invention configured as described above will be described.
上記第1〜3の実施形態によれば、バスバー2は、ソース電極および金属板6a,6bに接続される入力端子12、出力端子13の複数の広い電極用接合部7と、ゲート電極に接続される信号端子14の複数の狭い電極用接合部8とが、あらかじめ平板導体11に一体構造として成形されている。平板導体11は、半導体素子3a,3bの表面の各電極および金属板6a,6bにはんだを介して接合された後、切り離されて入力端子12、出力端子13および信号端子14が形成される。これにより、バスバー2と、半導体素子3a,3bの電極および金属板6a,6bとの間の接続は、すべてはんだを介して接合することによりおこなわれる。この結果、はんだ接合部9のはんだ寿命、接合強度および信頼性が向上する。また、接合工法をはんだ接合に統一して一括で製作できるので、工程が減少することにより製造コストを削減することができる。   According to the first to third embodiments, the bus bar 2 is connected to the gate electrode and the plurality of wide electrode joints 7 of the input terminal 12 and the output terminal 13 connected to the source electrode and the metal plates 6a and 6b. A plurality of narrow electrode joints 8 of the signal terminal 14 are formed in advance on the flat conductor 11 as an integral structure. The flat conductor 11 is joined to each electrode on the surface of the semiconductor elements 3a and 3b and the metal plates 6a and 6b via solder, and then separated to form the input terminal 12, the output terminal 13, and the signal terminal 14. Thereby, all the connections between the bus bar 2, the electrodes of the semiconductor elements 3a and 3b, and the metal plates 6a and 6b are made by joining via solder. As a result, the solder life, joint strength and reliability of the solder joint portion 9 are improved. In addition, since the joining method can be unified and manufactured by solder joining, manufacturing costs can be reduced by reducing the number of processes.
また、第1の実施形態によれば、信号端子14先端部の狭い電極用接合部8には、半導体素子3の表面の電極に当接するように所定の高さを有して、突起10が曲げにより一体成形されている。狭い電極用接合部8の長手方向に突起10の両側に溶融したはんだが充填され、固化されて、高さ方向の隙間(はんだ高さ)が安定した状態で半導体素子3と信号端子14とが接合され、断面が台形状のはんだ接合部9が形成される。これにより、高さ方向のはんだ塗布量を一定にして長手方向に発生する熱応力に対するはんだ接合部9の接合強度を大きくすることができる。   Further, according to the first embodiment, the narrow electrode joint 8 at the tip of the signal terminal 14 has a predetermined height so as to contact the electrode on the surface of the semiconductor element 3, and the protrusion 10 It is integrally formed by bending. The melted solder is filled on both sides of the protrusion 10 in the longitudinal direction of the narrow electrode joint 8 and solidified, and the semiconductor element 3 and the signal terminal 14 are connected with each other in a state where the height gap (solder height) is stable. The solder joints 9 having a trapezoidal cross section are formed. As a result, it is possible to increase the bonding strength of the solder joint portion 9 against the thermal stress generated in the longitudinal direction with a constant amount of solder applied in the height direction.
さらに、第2および第3の実施形態によれば、突起10は、信号端子14先端部の狭い電極用接合部8が受ける熱応力の方向に対応して中心位置からずらしてはんだ接合部9の断面形状が非対称に形成されている。すなわち、応力方向側のはんだ接合部9の断面形状が大きくなるように突起10の位置を一方にずらして配置する。これにより、バスバー2とモールドされた樹脂部材4との熱膨張係数の差異により発生する力に対して、長手方向に応力方向側の接合面積が大幅に拡大し、はんだの塗布量が増加することにより、はんだ接合部9が受ける長手方向の熱応力によるクラックの発生を防止することができる。この結果、はんだ接合部9において十分なはんだ寿命、接合強度が得られ、信頼性の向上を図ることができる。   Furthermore, according to the second and third embodiments, the protrusion 10 is shifted from the center position in accordance with the direction of the thermal stress received by the narrow electrode joint 8 at the tip of the signal terminal 14. The cross-sectional shape is formed asymmetrically. That is, the position of the protrusion 10 is shifted to one side so that the cross-sectional shape of the solder joint portion 9 on the stress direction side is increased. This greatly increases the bonding area on the stress direction side in the longitudinal direction and increases the amount of solder applied to the force generated by the difference in thermal expansion coefficient between the bus bar 2 and the molded resin member 4. Thus, it is possible to prevent the occurrence of cracks due to the thermal stress in the longitudinal direction received by the solder joint 9. As a result, a sufficient solder life and joint strength can be obtained in the solder joint portion 9, and the reliability can be improved.
以上のように、本発明の実施形態によれば、半導体素子の電極とバスバーとの間の配線接続部において、信号端子の接合面に突起を設けてはんだ接合することにより、十分な接合強度が得られるとともに、生産性の高い接合構造を有し、高信頼性、低コスト化された半導体装置を提供できる。
As described above, according to the embodiment of the present invention, in the wiring connection portion between the electrode of the semiconductor element and the bus bar, by providing a protrusion on the joint surface of the signal terminal and soldering, sufficient joint strength can be obtained. with the resulting, has a high productive junction structure, high reliability, it can be provided at low cost semiconductor equipment.
以上、本発明に係る実施形態について説明したが、本発明はさらに他の形態で実施することも可能である。   As mentioned above, although embodiment which concerns on this invention was described, this invention can also be implemented with another form.
上記実施形態では、半導体素子3としてMOSFETを用いた例を示したが、これに限定されるものでなく、他の半導体スイッチング素子(例えば、IGBT、トランジスタなどとフリーホイールダイオードを並列接続したもの)を用いてもよい。   In the above embodiment, an example in which a MOSFET is used as the semiconductor element 3 has been described. However, the present invention is not limited to this, and other semiconductor switching elements (for example, IGBTs, transistors, etc. and freewheel diodes connected in parallel) May be used.
上記実施形態では、半導体装置1として上アームと下アームとから構成される1相分をパッケージングした例を示したが、これに限定されるものでなく、例えば、アーム単体、または、3相分が一体となった構造でパワーモジュール15が形成されたものであってもよい。   In the above-described embodiment, an example in which one phase composed of an upper arm and a lower arm is packaged as the semiconductor device 1 is shown. However, the present invention is not limited to this. The power module 15 may be formed with a structure in which the minutes are integrated.
上記実施形態では、半導体素子3の片面(裏面)に金属板6、絶縁シート5を設け、ヒートシンクなどに設置する構造について示したが、これに限定されるものでなく、半導体素子3の表裏両面にバスバー2および絶縁シート5を配置して、半導体素子3の両面からヒートシンクなどで挟み込む構造であってもよい。   In the said embodiment, although the metal plate 6 and the insulating sheet 5 were provided in the single side | surface (back surface) of the semiconductor element 3, and it showed about the structure installed in a heat sink etc., it is not limited to this, Both front and back both surfaces of the semiconductor element 3 Alternatively, the bus bar 2 and the insulating sheet 5 may be disposed on each side of the semiconductor element 3 and sandwiched by heat sinks from both sides.
上記実施形態では、車載用モータを駆動するインバータ装置の配線接続に電極構造を適用する例を示したが、これに限定されるものでなく、モータを備えた高信頼性、低コストが求められる他の用途の電気機器装置などに適用してもよい。   In the said embodiment, although the example which applies an electrode structure to the wiring connection of the inverter apparatus which drives a vehicle-mounted motor was shown, it is not limited to this, The high reliability provided with the motor and low cost are calculated | required. You may apply to the electrical equipment apparatus of another use, etc.
1,1U,1V,1W:半導体装置、2:バスバー、3,3a,3b:半導体素子、
4:樹脂部材、5:絶縁シート(絶縁部材)、6,6a,6b:金属板(金属部材)、7:広い電極用接合部、8:狭い電極用接合部、9:はんだ接合部、10:突起、
11:平板導体、12:入力端子、13:出力端子、14:信号端子、
15:パワーモジュール、P,N:直流電源端子、U,V,W:モータ端子、
u1,u2,v1,v2,w1,w2:制御端子
1, 1U, 1V, 1W: semiconductor device, 2: bus bar, 3, 3a, 3b: semiconductor element,
4: resin member, 5: insulating sheet (insulating member), 6, 6a, 6b: metal plate (metal member), 7: wide electrode joint, 8: narrow electrode joint, 9: solder joint, 10 : Protrusion,
11: flat conductor, 12: input terminal, 13: output terminal, 14: signal terminal,
15: Power module, P, N: DC power supply terminal, U, V, W: Motor terminal,
u1, u2, v1, v2, w1, w2: control terminals

Claims (1)

  1. 半導体素子と、
    前記半導体素子を設置し、前記半導体素子の電極と電気的に接続された平板状の金属部材と、
    前記半導体素子の前記電極または前記金属部材と電気的に接続された平板状の金属製のバスバーと、
    前記金属部材の前記半導体素子とは反対側に固着され前記金属部材を絶縁するシート状の絶縁部材と、
    全体を封止する樹脂部材と、を備え、
    前記バスバーは、入出力端子に形成された複数の広い電極用接合部と、信号端子に形成された複数の狭い電極用接合部と、を有し、あらかじめ一体的に成形され、
    前記狭い電極用接合部は、前記半導体素子の前記電極と接合材を溶融固化した接合部を介して接合されるとともに、前記接合との接合面に所定の高さを有して一体的に形成され前記半導体素子の表面に当接する1個の突起を有し、
    前記突起は、前記接合部の前記狭い電極用接合部の長手方向の中心位置よりも一方向にずらした位置に配置され、前記接合部の断面形状が前記突起を挟んで前記狭い電極用接合部の長手方向に非対称に形成されることを特徴とする半導体装置。
    A semiconductor element;
    A flat metal member that is installed with the semiconductor element and electrically connected to the electrode of the semiconductor element;
    A flat metal bus bar electrically connected to the electrode or the metal member of the semiconductor element;
    A sheet-like insulating member that is fixed to the side opposite to the semiconductor element of the metal member and insulates the metal member;
    A resin member for sealing the whole,
    The bus bar has a plurality of wide electrode joints formed on the input / output terminals and a plurality of narrow electrode joints formed on the signal terminals, and is integrally molded in advance,
    The narrow electrode bonding portion is bonded to the electrode of the semiconductor element via a bonding portion obtained by melting and solidifying a bonding material , and has a predetermined height on a bonding surface with the bonding portion. Having one protrusion formed and in contact with the surface of the semiconductor element;
    The protrusion is arranged at a position shifted in one direction from the center position in the longitudinal direction of the narrow electrode joint of the joint, and the cross-sectional shape of the joint is the narrow electrode joint sandwiching the protrusion A semiconductor device characterized in that it is formed asymmetrically in the longitudinal direction .
JP2013181368A 2013-09-02 2013-09-02 Semiconductor device Active JP6331294B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013181368A JP6331294B2 (en) 2013-09-02 2013-09-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013181368A JP6331294B2 (en) 2013-09-02 2013-09-02 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2015050340A JP2015050340A (en) 2015-03-16
JP6331294B2 true JP6331294B2 (en) 2018-05-30

Family

ID=52700101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013181368A Active JP6331294B2 (en) 2013-09-02 2013-09-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JP6331294B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11037870B2 (en) 2017-05-19 2021-06-15 Shindengen Electric Manufacturing Co., Ltd. Electronic module, lead frame and manufacturing method for electronic module
JP6808849B2 (en) * 2017-10-26 2021-01-06 新電元工業株式会社 Semiconductor device
EP3703121A1 (en) 2017-10-26 2020-09-02 Shindengen Electric Manufacturing Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
WO2019135284A1 (en) * 2018-01-05 2019-07-11 三菱電機株式会社 Semiconductor device
WO2021145206A1 (en) * 2020-01-17 2021-07-22 パナソニックIpマネジメント株式会社 Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53139974A (en) * 1977-05-13 1978-12-06 Hitachi Ltd Semiconductor device
JPS5512728A (en) * 1978-07-14 1980-01-29 Hitachi Ltd Regin sealing type power transistor
JP2006222298A (en) * 2005-02-10 2006-08-24 Renesas Technology Corp Semiconductor device and manufacturing method thereof
JP5708359B2 (en) * 2011-08-11 2015-04-30 株式会社デンソー Semiconductor device and manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JP2015050340A (en) 2015-03-16

Similar Documents

Publication Publication Date Title
JP6331294B2 (en) Semiconductor device
US9390996B2 (en) Double-sided cooling power module and method for manufacturing the same
US9673118B2 (en) Power module and method of manufacturing power module
JP5263334B2 (en) Busbar module
JP4973059B2 (en) Semiconductor device and power conversion device
JP4640213B2 (en) Power semiconductor device and inverter bridge module using the same
JP2012004543A (en) Semiconductor unit, and semiconductor device using the same
WO2019107077A1 (en) Power semiconductor device, and manufacturing method for same
CA2951293A1 (en) Power converter provided with dual function bus bars
JP4942629B2 (en) Power semiconductor module
JP5213919B2 (en) Semiconductor device
WO2019187679A1 (en) Power semiconductor device
US20170288564A1 (en) Power conversion apparatus and method for manufacturing the same
WO2018235197A1 (en) Semiconductor device, power conversion device, and semiconductor device production method
JP2014229782A (en) Semiconductor device and manufacturing method of the same
JP2013236035A (en) Semiconductor module and manufacturing method of the same
JP5381903B2 (en) Electronic component equipment
JP6407300B2 (en) Semiconductor module and conductive member for semiconductor module
JP5062029B2 (en) Semiconductor device
JP2017022157A (en) Power semiconductor device
JP6272459B2 (en) Semiconductor module
JP2016144377A (en) Dc side wiring board of power module and method of manufacturing the same
JP2016092283A (en) Circuit board
JP2010177573A (en) Semiconductor device
JP6898588B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160809

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170418

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170509

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170616

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20171128

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20171225

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180403

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180416

R150 Certificate of patent or registration of utility model

Ref document number: 6331294

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150