CN115173729A

CN115173729A - Intelligent power module

Info

Publication number: CN115173729A
Application number: CN202210889761.1A
Authority: CN
Inventors: 黄志召; 李宇雄; 段三丁
Original assignee: Wuhan Yibian Electric Co ltd
Current assignee: Wuhan Yibian Electric Co ltd
Priority date: 2022-07-26
Filing date: 2022-07-26
Publication date: 2022-10-11

Abstract

The invention discloses an intelligent power module, which optimizes the layout mode of chips, adopts the mode that the chips are arranged in a line, leads the bonding connection of a driving electrode of the chip and a driving circuit to be more convenient, reduces the connection distance and can effectively reduce the parasitic inductance of a driving loop; the upper and lower switch chips and the corresponding driving chips of the three-phase full-bridge circuit are separately arranged, and the wiring between the upper and lower tube driving chips has no influence on each other; the switch chip of the three-phase full-bridge circuit is in Kelvin connection in a driving mode, so that common-source inductance can be effectively reduced, and coupling between a driving loop and a main power loop is reduced; a high-frequency decoupling capacitor is additionally arranged between the positive electrode and the negative electrode of the direct-current side of the three-phase full-bridge circuit, so that the parasitic inductance of a current conversion loop can be effectively reduced, the voltage peak of a power semiconductor chip in the high-speed switching process is reduced, and the damage of devices is avoided.

Description

Intelligent power module

Technical Field

The invention relates to the technical field of semiconductors, in particular to an intelligent power module.

Background

An Intelligent Power Module (IPM) is a hybrid integrated circuit combining power electronics and integrated circuit technologies, and generally includes a power electronic power device, a driving circuit, a detection circuit, a protection circuit, and the like. Compared with the traditional discrete device, the intelligent power module has the advantages of small volume, high integration degree, high reliability and the like, is convenient to use, can reduce the volume and the development time of a system, and is beneficial to enhancing the reliability of the system. The intelligent power module adapts to the development direction of the current power device, namely modularization, compounding and Power Integrated Circuit (PIC), and is widely applied to the fields of power electronics, such as variable frequency speed regulation, servo drive, electric traction and the like.

The intelligent power module is internally integrated with a driving circuit of a power semiconductor chip (IGB or MOSFET and the like), the driving circuit is close to the power semiconductor chip, the connecting line of the driving circuit and the power semiconductor chip is shortened, the impedance of driving current is low, and the switching speed of the power semiconductor chip can be increased, so that the switching loss is reduced, and the system efficiency is improved. However, in the existing intelligent power module, a common source inductor exists between the driving circuit and the main power circuit, which is not beneficial to increasing the switching speed, and the connection mode of the driving electrode of the power semiconductor chip is complex, which results in the problems of high processing failure rate, low efficiency and the like. In addition, the existing intelligent power module is connected with the outside through a lead frame, so that a large parasitic inductance is introduced, and a certain parasitic inductance is brought by the layout mode inside the power module. Under high-speed switching, the larger parasitic inductance of the main power loop can cause higher turn-off overvoltage, and the device can be damaged in serious conditions. Most of the existing intelligent power modules are packaged by plastics of epoxy molding compound, and the epoxy molding compound can protect chips from being influenced by external environment; resistance to external moisture, solvents, and impact; electrically insulating the chip from the external environment; good installation performance. However, the plastic package has low temperature resistance, low temperature cycle resistance and poor heat dissipation performance, and is only suitable for low-power intelligent power modules.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide an intelligent power module that realizes a compact power module package, an extremely low internal commutation loop parasitic inductance, a high temperature resistant package structure, and easy internal connection.

The intelligent power module comprises a three-phase full-bridge circuit, a driving and temperature detecting circuit, a metal shell consisting of a metal base and a cover plate, a signal terminal and first to fifth power terminals; the signal terminal includes: an A-phase upper bridge isolation power supply ground VEE1, an A-phase upper bridge isolation power supply VCC1, an A-phase upper bridge driving signal PWM1, a B-phase upper bridge isolation power supply ground VEE2, an A-phase upper bridge isolation power supply VCC2, a B-phase upper bridge driving signal PWM3, a C-phase upper bridge isolation power supply ground VEE3, a C-phase upper bridge isolation power supply VCC3, a C-phase upper bridge driving signal PWM5, a lower bridge isolation power supply ground VEE4, a lower bridge isolation power supply VCC4, an A-phase lower bridge driving signal PWM4, a B-phase lower bridge driving signal PWM6, a C-phase lower bridge driving signal PWM2 and a temperature detection signal VT; the first to fifth power terminals are: c phase output C, B phase output B, A phase output A, a three-phase full-bridge circuit cathode N and a three-phase full-bridge circuit anode P;

the metal base comprises a bottom plate and a side plate arranged on the bottom plate, the first power terminal, the second power terminal, the third power terminal, the fourth power terminal, the fifth power terminal, the signal terminal and the fourth power terminal are arranged on the side plate; the three-phase full-bridge circuit is arranged on the lower side of the bottom plate, the driving and temperature detecting circuit comprises a driving circuit and a temperature detecting circuit, and the driving circuit and the temperature detecting circuit are arranged on the upper side of the bottom plate side by side;

the three-phase full-bridge circuit comprises a first copper-clad ceramic substrate, six power semiconductor chips, a plurality of power bonding wires, a plurality of driving bonding wires, a plurality of copper strips and a plurality of decoupling capacitors, wherein the six power semiconductor chips are arranged in a row and are arranged on the first copper-clad ceramic substrate close to the upper edge, and the grid electrodes of the power semiconductor chips are arranged in the same direction and are close to the upper edge; the first copper-clad ceramic substrate is of a three-layer structure, the upper layer and the lower layer are copper foils, the middle layer is a ceramic substrate, the upper layer copper foil forms a circuit pattern through processing, the upper layer copper foil is composed of a first copper foil, a second copper foil, a third copper foil, a fourth copper foil and a fifth copper foil, and the lower layer copper foil is connected with the bottom plate in an eutectic mode through alloy solder.

Furthermore, a drain electrode of the first power semiconductor chip is connected to the first copper foil, the first copper foil is connected with the fifth power terminal through a fifth copper strip, a source electrode of the first power semiconductor chip is connected with the third copper foil through a first power bonding wire, the third copper foil is connected with the third power terminal through a third copper strip, the drain electrode of the second power semiconductor chip is welded on the third copper foil, the source electrode of the second power semiconductor chip is connected to the second copper foil through a fourth power bonding wire, and the second copper foil is connected with the fourth power terminal through a fourth copper strip; therefore, the circuit where the first power semiconductor chip and the second power semiconductor chip are located forms an A-phase half-bridge circuit;

the drain electrode of the third power semiconductor chip is connected to the first copper foil, the first copper foil is connected with the fifth power terminal through a fifth copper strip, the source electrode of the third power semiconductor chip is connected with the fourth copper foil through a second power bonding wire, the fourth copper foil is connected with the second power terminal through a second copper strip, the drain electrode of the fourth power semiconductor chip is welded on the fourth copper foil, the source electrode of the fourth power semiconductor chip is connected to the second copper foil through the fifth power bonding wire, and the second copper foil is connected with the fourth power terminal through the fourth copper strip, so that a circuit where the third power semiconductor chip and the fourth power semiconductor chip are located forms a B-phase half-bridge circuit;

the drain electrode of the fifth power semiconductor chip is connected to the first copper foil, the first copper foil is connected with the fifth power terminal through a fifth copper strip, the source electrode of the fifth power semiconductor chip is connected with the fifth copper foil through a third power bonding wire, the fifth copper foil is connected with the first power terminal through the first copper strip, the drain electrode of the sixth power semiconductor chip is welded on the fifth copper foil, the source electrode of the sixth power semiconductor chip is connected to the second copper foil through a sixth power bonding wire, and the second copper foil is connected with the fourth power terminal through a fourth copper strip.

Furthermore, a plurality of decoupling capacitors are parallelly arranged on the first copper-clad ceramic substrate and close to the side plate of the lower side, one pin of each decoupling capacitor is welded on the second copper foil and connected to the negative electrode N of the three-phase full-bridge circuit through the fourth copper strip, and the other pin of each decoupling capacitor is welded on the first copper foil and connected to the power terminal P through the fifth copper strip.

Further, the metal base and the cover plate are assembled together by a parallel sealing process, and inert gas is filled inside to form a hermetic package.

Furthermore, a plurality of power end insulating ceramics and a plurality of signal end insulating ceramics are arranged on the metal base, the power end insulating ceramics surround the first power terminal, the second power terminal, the third power terminal, the fourth power terminal, the fifth power terminal and the metal base, so that the power terminals are insulated from the metal base, and the signal end insulating ceramics surround the signal terminals, so that the signal terminals are insulated from the metal base.

Furthermore, the driving circuit comprises 1 circuit board, 6 driving chips, 6 groups of dry driving bonding pads, a plurality of signal connecting bonding wires and a plurality of resistance-capacitance elements arranged on the circuit board, 6 driving chips are welded on the

circuit board

63, 6 groups of driving bonding pads respectively close to the driving chips are arranged on the circuit board, 6 groups of driving bonding pads respectively correspond to the 6 groups of driving bonding pads of the 6 power semiconductor chips, and driving electrodes of the 6 power semiconductor chips are respectively and correspondingly connected;

the first driving chip drives a sixth power semiconductor chip, a second signal connection bonding wire is connected to PWM2 on the side plate, driving signals enter the intelligent power module through the PWM2 and are connected to the first driving chip through the second signal connection bonding wire, output signals of the first driving chip are connected to a first driving bonding pad, and the output signals of the first driving chip are connected to a grid electrode and a source electrode bonding pad of the sixth power semiconductor chip through the sixth driving bonding wire;

the second driving chip drives a fourth power semiconductor chip, a third signal connection bonding wire is connected to PWM6 on the side plate, a driving signal enters the intelligent power module through PWM4 and is connected to the second driving chip through the third signal connection bonding wire, an output signal of the second driving chip is connected to a second driving bonding pad and is connected to a grid electrode and a source electrode bonding pad of the fourth power semiconductor chip through a fifth driving bonding wire;

a third driving chip drives a second power semiconductor chip, a fourth signal connection bonding wire is connected to PWM4 on the side plate, a driving signal enters the intelligent power module through the PWM4 and is connected to the third driving chip through the fourth signal connection bonding wire, an output signal of the third driving chip is connected to a third driving bonding pad and is connected to a grid electrode and a source electrode bonding pad of the second power semiconductor chip through the fourth driving bonding wire;

the first driving chip, the second driving chip and the third driving chip are powered by the same group of external isolation power supplies, a fifth signal connection bonding wire is connected to VCC4 on the side plate, and a sixth signal connection bonding wire is connected to VEE4 on the side plate;

the fourth driving chip drives a fifth power semiconductor chip, a seventh signal connection bonding wire is connected to a PWM5 on the side plate, a driving signal enters the intelligent power module through the PWM5 and is connected to the fourth driving chip through the seventh signal connection bonding wire, an output signal of the fourth driving chip is connected to a fourth driving bonding pad and is connected to a grid electrode and a source electrode bonding pad of the fifth power semiconductor chip through a third driving bonding wire; the fourth driving chip is powered by an external isolation power supply, and an eighth signal connection bonding wire and a ninth signal connection bonding wire are respectively connected to VCC3 and VEE3 on the side plate;

the fifth driving chip drives the third power semiconductor chip, a tenth signal connection bonding wire is connected to the PWM3 on the side plate, driving signals enter the intelligent power module through the PWM3 and are connected to the fifth driving chip through the tenth signal connection bonding wire, output signals of the fifth driving chip are connected to a fifth driving bonding pad, and the fifth driving bonding pad is connected to a grid electrode and a source electrode bonding pad of the third power semiconductor chip through a second driving bonding wire; the fifth driving chip is powered by an external isolation power supply, and an eleventh signal connection bonding wire and a twelfth signal connection bonding wire are respectively connected to VCC2 and VEE2 on the side plate;

a sixth driving chip drives the first power semiconductor chip, a thirteenth signal connection bonding wire is connected to a PWM1 on the side plate, a driving signal PWM1 enters the intelligent power module and is connected to the sixth driving chip through the thirteenth signal connection bonding wire, an output signal of the sixth driving chip is connected to a sixth driving bonding pad and is connected to a grid electrode and a source electrode bonding pad of the first power semiconductor chip through the first driving bonding wire; the sixth driving chip is powered by an external isolation power supply, and the fourteenth signal connection bonding wire and the fifteenth signal connection bonding wire are respectively connected to the VCC1 and the signal terminal VEE1 on the side plate.

Furthermore, the temperature detection circuit comprises a second copper-clad ceramic substrate, 1 temperature detection chip and a plurality of resistance-capacitance devices arranged on the second copper-clad ceramic substrate; the upper layer of the second copper-clad ceramic substrate is a copper foil which is processed to form a circuit pattern according to a temperature detection circuit and comprises a sixth copper foil, a seventh copper foil and an eighth copper foil, the sixth copper foil on the copper-clad ceramic substrate is bonded with a temperature detection chip, two pins of the temperature detection chip are respectively welded on the seventh copper foil and the eighth copper foil of the copper-clad ceramic substrate, the temperature detection chip and part of resistance-capacitance elements form a temperature detection circuit, and a first signal connection bonding wire connects an output signal of the temperature detection circuit to VT on the side plate.

Furthermore, in 6 power semiconductor chips in the three-phase full-bridge circuit, three upper tubes and three corresponding driving chips are distributed on the right side in the intelligent power module, the three upper tube driving circuits do not interfere with each other, and three lower tubes and three corresponding driving chips are distributed on the left side in the intelligent power module.

Furthermore, part or all of the first to sixth power bonding wires are respectively formed by connecting a plurality of bonding wires in parallel.

Furthermore, the outer edges of the upper and lower layers of copper foils are positioned on the ceramic substrate and have a certain distance from the edge of the ceramic substrate.

The intelligent power module optimizes the layout mode of the chip, adopts the mode of arranging the chips in a line, ensures that the bonding connection between the driving electrode of the chip and the driving circuit is more convenient, reduces the connection distance and can effectively reduce the parasitic inductance of a driving loop; the upper and lower switch chips and the corresponding driving chips of the three-phase full-bridge circuit are separately arranged, and the wiring between the upper and lower tube driving chips has no influence; the switch chip of the three-phase full-bridge circuit is in Kelvin connection in a driving mode, so that common source inductance can be effectively reduced, and coupling between a driving loop and a main power loop is reduced; a high-frequency decoupling capacitor is additionally arranged between the positive electrode and the negative electrode of the direct-current side of the three-phase full-bridge circuit and integrated inside the module, so that the parasitic inductance of a current conversion loop can be effectively reduced, the voltage peak of a power semiconductor chip in the high-speed switching process is reduced, and the damage of devices is avoided.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a circuit diagram of one embodiment of a smart power module of the present invention;

fig. 2 is an external view of an embodiment of the smart power module of the present invention.

Fig. 3 is an open lid view of the smart power module of fig. 2 of the present invention.

Fig. 4 is a block diagram of a metal housing of the smart power module of fig. 2 according to the present invention.

Fig. 5 is a three-phase full bridge circuit model diagram of the intelligent power module in fig. 2 according to the present invention.

Fig. 6 is a schematic diagram of a first copper-clad ceramic substrate of the smart power module of fig. 2 according to the present invention.

FIG. 7 is a block diagram of a driving and temperature detecting circuit of the smart power module of FIG. 2 according to the present invention.

Wherein, 2: metal base, 3: cover plate, 4: signal terminal, 5: first power terminal, 6: three-phase full bridge circuit, 7: drive and temperature detection circuit, 8: power terminal insulating ceramic, 9: signal terminal insulating ceramic, 10: mounting hole, 11: side plate, 12: bottom plate, 13: second power terminal, 14: third power terminal, 15: fourth power terminal, 16: fifth power terminal, 17: first ceramic substrate, 18: first copper foil, 19: second copper foil, 20: third copper foil, 21: fourth copper foil, 22: fifth copper foil, 13: lower copper foil, 24: first power semiconductor chip, 25: second power semiconductor chip, 26: third power semiconductor chip, 27: power semiconductor chip, 28: power semiconductor chip, 29: power semiconductor chip, 30: first power bonding wire, 31: second power bonding wire, 32: third power bonding wire, 33: fourth power bonding wire, 34: fifth power bond wire, 35: sixth power bond wire, 36: first drive bonding wire, 37: second drive bonding wire, 38: third drive bonding wire, 39: fourth drive bonding wire, 40: fifth drive bonding wire, 41: sixth drive bonding wire, 42: first copper bar, 43: second copper bar, 44: third copper bar, 45: fourth copper bar, 46: fifth copper bar, 47: sixth copper bar, 48: first driver chip, 49: second driver chip, 50: third driver chip, 51: fourth driver chip, 52: fifth driver chip, 53: sixth driver chip, 54: first driving pad, 55: second driving pad, 56: third driving pad, 57: fourth drive pad, 58: fifth driving pad, 59: sixth driving pad, 60: temperature detection chip, 61: second copper-clad ceramic substrate, 62: first signal connection bond wire, 63: circuit board, 64: second signal connection bond wire, 65: third signal connection bond wire, 66: fourth signal connection bond wire, 67: fifth signal connection bond wire, 68: sixth signal connection bond wire, 69: seventh signal connection bond wire, 70: eighth signal connection bonding wire, 71: ninth signal connection bond wire, 72: tenth signal connection bond wire, 73: eleventh signal connection bond wire, 74: twelfth signal connection bond wire, 75: thirteenth signal connection bond wire, 76: fourteenth signal connection bonding wire, 77: and the fifteenth signal is connected with the bonding wire.

Detailed Description

For a more clear understanding of the technical features, objects, and effects of the present invention, embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

Referring to fig. 1 to 7, an intelligent power module includes a three-phase full-bridge circuit 6, a driving and temperature detecting circuit 7, a metal housing 1 composed of a metal base 2 and a cover plate 3, a signal terminal 4, and first to fifth power terminals. The metal base comprises a bottom plate 12 and side plates 11 arranged on the periphery of the bottom plate 12, the metal base 2 and the cover plate 3 are assembled together through a parallel sealing welding process, inert gas is filled inside the metal base to form airtight packaging, and the metal base can resist water vapor corrosion and isolate external impurity pollution after being sealed.

Referring back to fig. 1, the interface symbols and functions in the circuit diagram are defined in the following table.

(symbol)	Definition of functions	(symbol)	Definition of functions
				VEE1	A phase upper bridge isolation power ground	PWM4	Phase A lower bridge driving signal
VCC1	A phase upper bridge isolation power supply	PWM6	B phase lower bridge driving signal
				PWM1	A phase upper bridge driving signal	PWM2	C-phase under-bridge drive signal
VEE2	B-phase upper bridge isolation power ground	NC	Is not connected to
				VCC2	A phase upper bridge isolation power supply	VT	Temperature detection signal
PWM3	B phase upper bridge driving signal	C	Output of C phase
				VEE3	C-phase upper bridge isolation power ground	B	Output of B phase
VCC3	C-phase upper bridge isolation power supply	A	Output of A phase
				PWM5	C-phase upper bridge driving signal	N	Main power cathode
VEE4	Lower bridge isolation power ground	P	Main power positive electrode
				VCC4	Lower bridge isolation power supply

Referring back to fig. 1-2, the signal terminal includes: an A-phase upper bridge isolation power supply ground VEE1, an A-phase upper bridge isolation power supply VCC1, an A-phase upper bridge driving signal PWM1, a B-phase upper bridge isolation power supply ground VEE2, an A-phase upper bridge isolation power supply VCC2, a B-phase upper bridge driving signal PWM3, a C-phase upper bridge isolation power supply ground VEE3, a C-phase upper bridge isolation power supply VCC3, a C-phase upper bridge driving signal PWM5, a lower bridge isolation power supply ground VEE4, a lower bridge isolation power supply VCC4, an A-phase lower bridge driving signal PWM4, a B-phase lower bridge driving signal PWM6, a C-phase lower bridge driving signal PWM2, a disconnected NC and a temperature detection signal VT are sequentially arranged on a side plate 11 on the upper side of the metal base 2 from right to left. The first to fifth power terminals are in turn: the C-phase output C, the B-phase output B, the A-phase output A, the negative pole N of the three-phase full-bridge circuit and the positive pole P of the three-phase full-bridge circuit are sequentially arranged on the side plate 11 on the lower side of the metal base 2 from left to right.

Referring to fig. 3 and 4, the bottom plate 12 of the metal base 2 plays a role in heat conduction and support, and the bottom plate 12 is generally made of dispersed aluminum copper, so that the heat conduction coefficient is high, and the heat conduction efficiency can be improved. Four corners of the bottom plate 12 are respectively provided with a mounting hole 10, and the four mounting holes 10 are distributed on the bottom plate 12, so that the fixed connection with an external radiator and the like can be realized. And a plurality of power end insulating ceramics 8 surround the power terminals, so that the power terminals are insulated from the metal base 2 and play a role of fixing and supporting.

Preferably, the side plate 11 is further provided with a plurality of power terminal insulating ceramics 8 and a plurality of signal terminal insulating ceramics 9, and the plurality of power terminal insulating ceramics 8 surround the first to fifth power terminals, so that the first to fifth power terminals are insulated from the metal base 2 and play a role of fixing and supporting; a plurality of signal terminal insulating ceramics 9 surround the signal terminals to insulate the signal terminals from the metal base 2 and also play a role of fixing and supporting. The dry power terminal insulating ceramics 8 are provided on both the inner and outer faces of the side plate 11.

The three-phase full-bridge circuit can be mainly referred to fig. 1 and 5, 6, the three-phase full-bridge circuit 6 is arranged at the lower side of the bottom plate 12, the driving and temperature detecting circuit 7 comprises a driving circuit and a temperature detecting circuit, and the driving circuit and the temperature detecting circuit are arranged at the upper side of the bottom plate 12 side by side.

The three-phase full-bridge circuit 6 comprises a first copper-clad ceramic substrate 17, six power semiconductor chips, a plurality of power bonding wires, a plurality of driving bonding wires, a plurality of copper strips and a plurality of decoupling capacitors 47. The power semiconductor chip in the present embodiment is exemplified by a MOSFET chip, and is also applicable to other power semiconductor chips such as an IGBT. The six power semiconductor chips are arranged in a line and are arranged on the first copper-clad ceramic substrate 17 close to the upper edge, and the grid electrodes of the power semiconductor chips are arranged in the same direction and close to the upper edge. The arrangement mode enables the driving bonding wires of the six MOSFET chips to be close to the driving and temperature detection circuit 7, can realize bonding wire connection in the shortest distance, and avoids the problems of short circuit, breakage, wire collapse and the like caused by interconnection of long bonding wires. The MOSFET chip of this embodiment is model JNMOS80a600, but the present invention is not limited to this model, with the source and gate of the MOSFET chip on the top surface and the drain on the bottom surface.

The first copper-clad ceramic substrate is of a three-layer structure, the upper layer and the lower layer are copper foils, the middle layer is a ceramic substrate 17, the upper layer of copper foil is processed to form a circuit pattern to play a role in electric conduction and heat transfer, the upper layer of copper foil is composed of a first copper foil 18, a second copper foil 19, a third copper foil 20, a fourth copper foil 21 and a fifth copper foil 22, and the lower layer of copper foil 23 is connected with the bottom plate 12 in an eutectic mode through alloy solders to play a role in heat conduction and fixation. The outer edge of the upper and lower layers of copper foil is located on the ceramic substrate 17, and has a certain distance from the edge of the ceramic substrate 17, and the distance is determined according to the voltage-resistant requirement of the module, in the embodiment, the edge distance is set to be 1.3mm. The intermediate layer of the ceramic substrate 17 is typically a ceramic material such as alumina, aluminum nitride, silicon nitride, etc., and the present embodiment is exemplified by aluminum nitride.

The bottom drain electrode of the first power semiconductor chip 24 is connected to the first copper foil 18 by soldering, the first copper foil 18 is connected to the fifth power terminal 16 through the fifth copper strip 40, and the top source electrode of the first power semiconductor chip 24 is connected to the third copper foil 20 through the first power bonding wire 30. Preferably, the first power bonding wire 30 is formed by connecting a plurality of bonding wires in parallel, so that the current capacity can be increased, and in practical application, the plurality of bonding wires can be selected as much as possible according to the size of the bonding area. The third copper foil 20 is connected with the third power terminal 14 through a third copper strip 44, the bottom drain electrode of the second power semiconductor chip 25 is welded on the third copper foil 20, and the top source electrode of the second power semiconductor chip 25 is connected to the second copper foil 19 through a fourth power bonding wire 33. Preferably, the fourth power bonding wire 33 is formed by connecting a plurality of bonding wires in parallel, so that the current capacity can be increased, and in practical application, the plurality of bonding wires can be selected as much as possible according to the size of the bonding area. The second copper foil 19 is connected with the fourth power terminal 15 through a fourth copper bar 45; thus, the circuit including the first power semiconductor chip 24 and the second power semiconductor chip 25 forms an a-phase half-bridge circuit.

The bottom drain electrode of the third power semiconductor chip 26 is connected to the first copper foil 18 by soldering, the first copper foil 18 is connected to the fifth power terminal 16 through a fifth copper strip 40, and the top source electrode of the third power semiconductor chip 26 is connected to the fourth copper foil 21 through a second power bonding wire 31. Preferably, the second power bonding wire 31 is formed by connecting a plurality of bonding wires in parallel, so that the current capacity can be increased, and in practical application, the plurality of bonding wires can be selected as much as possible according to the size of the bonding area. The fourth copper foil 21 is connected with the second power terminal 13 through a second copper strip 43, the bottom drain electrode of the fourth power semiconductor chip 27 is soldered on the fourth copper foil 21, and the top source electrode of the fourth power semiconductor chip 27 is connected to the second copper foil 19 through a fifth power bonding wire 34. Preferably, the fifth power bonding wire 34 is formed by connecting a plurality of bonding wires in parallel, so that the current capacity can be increased, and in practical application, the plurality of bonding wires can be selected as much as possible according to the size of the bonding area. The second copper foil 19 is connected to the fourth power terminal 15 via the fourth copper bar 45, and thus the circuit in which the third power semiconductor chip 26 and the fourth power semiconductor chip 27 are located constitutes a B-phase half-bridge circuit.

The bottom drain electrode of the fifth power semiconductor chip 28 is connected to the first copper foil 18 by soldering, the first copper foil 18 is connected to the fifth power terminal 16 through a fifth copper strip 40, and the top source electrode of the fifth power semiconductor chip 28 is connected to the fifth copper foil 22 through a third power bonding wire 32. Preferably, the third power bonding wire 32 is formed by connecting a plurality of bonding wires in parallel, so that the current capacity can be increased, and in practical application, the plurality of bonding wires can be selected as much as possible according to the size of the bonding area. The fifth copper foil 22 is connected with the first power terminal 5 through a first copper strip 42, the bottom drain electrode of the sixth power semiconductor chip 29 is welded on the fifth copper foil 22, and the top source electrode of the sixth power semiconductor chip 29 is connected to the second copper foil 19 through a sixth power bonding wire 35. Preferably, the sixth power bonding wire 35 is formed by connecting a plurality of bonding wires in parallel, so that the current capacity can be increased, and in practical application, the plurality of bonding wires can be selected as much as possible according to the size of the bonding area. The second copper foil 19 is connected to the fourth power terminal 15 through the fourth copper bar 45, so that the circuit including the fifth power semiconductor chip 28 and the sixth power semiconductor chip 29 forms a C-phase half-bridge circuit.

Referring to fig. 5, a plurality of decoupling capacitors 47 are arranged in parallel at the edge of the first copper-clad ceramic substrate close to the first side. The decoupling capacitor 47 in this embodiment is a chip multilayer ceramic capacitor, which is temperature resistant and voltage resistant. One pin of the decoupling capacitor 47 is welded on the second copper foil 19 and connected to the negative electrode N of the three-phase full-bridge circuit through a fourth copper strip 45, and the other pin of the decoupling capacitor 47 is welded on the first copper foil 18 and connected to the power terminal P through a fifth copper strip 46. The decoupling capacitor 47 is connected between the positive and negative buses on the direct current side of the three-phase full-bridge circuit 6, and can provide current in the high-speed commutation process of the power semiconductor chip, so that the length of the commutation loop is shortened, and the parasitic inductance of the commutation loop is reduced.

The driving circuit comprises 1

circuit board

63, 6 driving chips, 6 groups of dry driving bonding pads, a plurality of signal connection bonding wires and a plurality of resistance-capacitance elements (resistance elements and capacitance elements) arranged on the circuit board 63, wherein the circuit board 63 is welded with 6 driving chips, 6 groups of driving bonding pads respectively close to the driving chips are arranged on the circuit board 63, the 6 groups of driving bonding pads respectively correspond to the 6 groups of driving bonding pads of the 6 power semiconductor chips, and the driving bonding pads are respectively correspondingly connected with driving electrodes of the 6 power semiconductor chips. The circuit board 63 is a single-layer circuit board, and may be composed of a conventional PCB, a copper-clad ceramic substrate, and the like.

The first driving chip 48 drives the sixth power semiconductor chip 29, the second signal connection bonding wire 64 is connected to the signal terminal PWM2 on the side board, the driving signal enters the smart power module through the signal terminal PWM2, and is connected to the first driving chip 48 through the second signal connection bonding wire 64, the output signal of the first driving chip 48 is connected to the first driving pad 54, and is connected to the gate and source pads of the sixth power semiconductor chip 29 through the sixth driving bonding wire 41.

The second driving chip 49 drives the fourth power semiconductor chip 27, the third signal connection bonding wire 65 is connected to the PWM6 on the side board, the driving signal enters the intelligent power module through the PWM4, and is connected to the second driving chip 49 through the third signal connection bonding wire 65, the output signal of the second driving chip 49 is connected to the second driving bonding pad 55, and is connected to the gate and source bonding pads of the fourth power semiconductor chip 27 through the fifth driving bonding wire 40.

The third driving chip 50 drives the second power semiconductor chip 25, the fourth signal connection bonding wire 66 is connected to the PWM4 on the side plate, the driving signal enters the intelligent power module through the PWM4, and is connected to the third driving chip 50 through the fourth signal connection bonding wire 66, the output signal of the third driving chip 50 is connected to the third driving bonding pad 56, and is connected to the gate and source bonding pads of the second power semiconductor chip 25 through the fourth driving bonding wire 39.

The first driving chip 48, the second driving chip 49 and the third driving chip 50 are powered by the same set of external isolated power sources, the fifth signal connection bonding wire 67 is connected to the signal terminal VCC4 on the side plate, and the sixth signal connection bonding wire 68 is connected to the signal terminal VEE4 on the side plate.

The fourth driving chip 51 drives the fifth power semiconductor chip 28, a seventh signal connection bonding wire 69 is connected to the PWM5 on the side plate, a driving signal enters the intelligent power module through the PWM5, and is connected to the fourth driving chip 51 through the seventh signal connection bonding wire 69, an output signal of the fourth driving chip 51 is connected to the fourth driving bonding pad 57, and is connected to the gate and source bonding pads of the fifth power semiconductor chip 28 through the third driving bonding wire 38; the fourth driving chip 51 is powered by an external isolation power supply, and the eighth signal connection bonding wire 70 and the ninth signal connection bonding wire 71 are connected to the signal terminals VCC3 and VEE3 on the side plate, respectively.

The fifth driving chip 52 drives the third power semiconductor chip 26, the tenth signal connection bonding wire 72 is connected to the PWM3 on the side plate, the driving signal enters the intelligent power module through the PWM3, and is connected to the fifth driving chip 52 through the tenth signal connection bonding wire 72, the output signal of the fifth driving chip 52 is connected to the fifth driving bonding pad 58, and is connected to the gate and source bonding pads of the third power semiconductor chip 26 through the second driving bonding wire 37; the fifth driving chip 52 is powered by an external isolation power supply, and the eleventh and twelfth signal

connection bonding wires

73 and 74 are connected to the signal terminals VCC2 and VEE2 on the side plates, respectively.

The sixth driving chip 53 drives the first power semiconductor chip 24, the thirteenth signal connection bonding wire 75 is connected to the PWM1 on the side plate, the driving signal PWM1 enters the intelligent power module and is connected to the sixth driving chip 53 through the thirteenth signal connection bonding wire 75, the output signal of the sixth driving chip 53 is connected to the sixth driving bonding pad 59 and is connected to the gate and source bonding pads of the first power semiconductor chip 24 through the first driving bonding wire 36; the sixth driving chip 53 is supplied with power from an external isolated power source, and the fourteenth signal connection bonding wire 76 and the fifteenth signal connection bonding wire 77 are connected to the signal terminal VCC1 and the signal terminal VEE1 on the side plate, respectively.

The temperature detection circuit comprises a second copper-clad

ceramic substrate

61, 1 temperature detection chip 60 and a plurality of resistor-capacitor components arranged on the second copper-clad ceramic substrate 61; the upper layer of the second copper-clad ceramic substrate 61 is a copper foil processed to form a circuit pattern according to a temperature detection circuit, and comprises a sixth copper foil, a seventh copper foil and an eighth copper foil, wherein the temperature detection chip 60 is bonded on the sixth copper foil on the copper-clad ceramic substrate 61, two pins of the temperature detection chip 60 are respectively welded on the seventh copper foil and the eighth copper foil of the copper-clad ceramic substrate 61, the temperature detection chip 60 and part of resistance-capacitance elements form the temperature detection circuit, and a first signal connection bonding wire 62 connects an output signal of the temperature detection circuit to VT on a side plate. The temperature detection chip 60 and the resistance-capacitance device on the second copper-clad ceramic substrate 61 together constitute a temperature detection circuit, and if necessary, a partial resistance-capacitance device on the circuit board.

According to the intelligent power module provided by the embodiment of the invention, six power semiconductor chips are distributed on the upper side of the copper-clad ceramic substrate in an optimized layout mode and are close to a circuit board where a driving circuit is located. In addition, the internal connection of the three-phase full-bridge circuit can be realized by optimizing the wiring mode of the power part. The layout mode can change the connection mode of the driving bonding wires of the power semiconductor chip, and the Kelvin connection mode is adopted, so that the common source inductance is reduced, meanwhile, the connection distance between the power semiconductor chip and the driving circuit is shortened, and the parasitic inductance of a driving circuit is reduced. Therefore, the electromagnetic coupling of the main power loop and the driving loop of the three-phase full-bridge circuit can be effectively reduced, the bonding interconnection inside the module is simplified, the problems of short circuit, breakage, wire collapse and the like are not easy to occur, the reliability of module production is improved, and the production yield and efficiency are improved.

Among 6 power semiconductor chips in the three-phase full-bridge circuit, three top tube and the three routes drive chip that corresponds distribute the right side in the module, three routes top tube drive circuit mutual noninterference, three low tube and the three routes drive chip that corresponds distribute the left side in the module, three routes drive chip's power supply is the same, arranges in one, the convenient wiring. In addition, the upper and lower tube driving chips of the three-phase full-bridge circuit are respectively arranged, so that the crossing of upper and lower tube signals is avoided, and the interference can be reduced.

The intelligent power module of the invention adopts a method of internally integrating the high-frequency decoupling capacitor to reduce the parasitic inductance of the main power commutation loop, thereby effectively reducing the voltage peak of the power semiconductor chip in the high-speed turn-off process and ensuring that the chip works in a safe area.

The intelligent power module can effectively improve the heat dissipation performance by adopting the method of hermetically packaging the aluminum nitride AlN ceramic copper-clad substrate and the metal shell 1. In addition, metal casing structural strength is high, simple to operate. The metal shell is high-temperature resistant in air-tight packaging, inert gas is filled in the metal shell, the influence of impurities such as water vapor on the chip can be effectively reduced, and the reliability and the tolerance capability of harsh environment are improved.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. An intelligent power module comprises a three-phase full-bridge circuit (6), a driving and temperature detecting circuit (7), and is characterized by further comprising a metal shell (1) consisting of a metal base (2) and a cover plate (3), a signal terminal (4) and first to fifth power terminals; the signal terminal includes: an A-phase upper bridge isolation power supply ground VEE1, an A-phase upper bridge isolation power supply VCC1, an A-phase upper bridge driving signal PWM1, a B-phase upper bridge isolation power supply ground VEE2, an A-phase upper bridge isolation power supply VCC2, a B-phase upper bridge driving signal PWM3, a C-phase upper bridge isolation power supply ground VEE3, a C-phase upper bridge isolation power supply VCC3, a C-phase upper bridge driving signal PWM5, a lower bridge isolation power supply ground VEE4, a lower bridge isolation power supply VCC4, an A-phase lower bridge driving signal PWM4, a B-phase lower bridge driving signal PWM6, a C-phase lower bridge driving signal PWM2 and a temperature detection signal VT; the first to fifth power terminals are: c phase output C, B phase output B, A phase output A, a three-phase full-bridge circuit cathode N and a three-phase full-bridge circuit anode P;

the metal base comprises a bottom plate (12) and a side plate (11) arranged on the bottom plate (12), first to fifth power terminals are arranged on the side plate (11) on the upper side, and signal terminals are arranged on the side plate (11) on the lower side; the three-phase full-bridge circuit (6) is arranged on the lower side of the bottom plate (12), the driving and temperature detecting circuit (7) comprises a driving circuit and a temperature detecting circuit, and the driving circuit and the temperature detecting circuit (7) are arranged on the upper side of the bottom plate (12) side by side;

the three-phase full-bridge circuit (6) comprises a first copper-clad ceramic substrate, six power semiconductor chips, a plurality of power bonding wires, a plurality of driving bonding wires, a plurality of copper strips and a plurality of decoupling capacitors (47), wherein the six power semiconductor chips are arranged in a row and are arranged on the first copper-clad ceramic substrate close to the upper edge, and the grids of the power semiconductor chips are arranged in the same direction and close to the upper edge; the first copper-clad ceramic substrate is of a three-layer structure, the upper layer and the lower layer are both copper foils, the middle layer is a ceramic substrate (17), the upper layer of copper foil forms a circuit pattern through processing, the upper layer of copper foil is composed of a first copper foil (18), a second copper foil (19), a third copper foil (20), a fourth copper foil (21) and a fifth copper foil (22), and the lower layer of copper foil is connected with the bottom plate (12) through an alloy solder eutectic mode.

2. The smart power module of claim 1,

the drain electrode of the first power semiconductor chip (24) is connected to the first copper foil (18), the first copper foil (18) is connected with the fifth power terminal (16) through a fifth copper strip (40), the source electrode of the first power semiconductor chip (24) is connected with the third copper foil (20) through a first power bonding wire (30), the third copper foil (20) is connected with the third power terminal (14) through a third copper strip (44), the drain electrode of the second power semiconductor chip (25) is welded on the third copper foil (20), the source electrode of the second power semiconductor chip (25) is connected to the second copper foil (19) through a fourth power bonding wire (33), and the second copper foil (19) is connected with the fourth power terminal (15) through a fourth copper strip (45); therefore, the circuit where the first power semiconductor chip (24) and the second power semiconductor chip (25) are located forms an A-phase half-bridge circuit;

the drain electrode of a third power semiconductor chip (26) is connected to a first copper foil (18), the first copper foil (18) is connected with a fifth power terminal (16) through a fifth copper strip (40), the source electrode of the third power semiconductor chip (26) is connected with a fourth copper foil (21) through a second power bonding wire (31), the fourth copper foil (21) is connected with a second power terminal (13) through a second copper strip (43), the drain electrode of a fourth power semiconductor chip (27) is welded on the fourth copper foil (21), the source electrode of the fourth power semiconductor chip (27) is connected to a second copper foil (19) through a fifth power bonding wire (34), and the second copper foil (19) is connected with a fourth power terminal (15) through a fourth copper strip (45), so that the circuits of the third power semiconductor chip (26) and the fourth power semiconductor chip (27) form a circuit with a B phase half bridge;

the drain electrode of a fifth power semiconductor chip (28) is connected to a first copper foil (18), the first copper foil (18) is connected with a fifth power terminal (16) through a fifth copper strip (40), the source electrode of the fifth power semiconductor chip (28) is connected with a fifth copper foil (22) through a third power bonding wire (32), the fifth copper foil (22) is connected with a first power terminal (5) through a first copper strip (42), the drain electrode of a sixth power semiconductor chip (29) is welded on the fifth copper foil (22), the source electrode of the sixth power semiconductor chip (29) is connected to a second copper foil (19) through a sixth power bonding wire (35), and the second copper foil (19) is connected with a fourth power terminal (15) through a fourth copper strip (45), so that the fifth power semiconductor chip (28) and the sixth power semiconductor chip (29) form a circuit in which a C-phase half bridge is formed.

3. The smart power module of claim 1,

a plurality of decoupling capacitors (47) are arranged on the first copper-clad ceramic substrate in parallel and close to the side plate (11) on the lower side, one pin of each decoupling capacitor (47) is welded on the second copper foil (19) and connected to the negative electrode N of the three-phase full-bridge circuit through the fourth copper bar (45), and the other pin of each decoupling capacitor (47) is welded on the first copper foil (18) and connected to the power terminal (P) through the fifth copper bar (46).

4. The smart power module according to claim 1, wherein the metal base (2) and the cover plate (3) are assembled together by a parallel sealing process, and inert gas is filled inside to form a hermetic package.

5. The smart power module according to claim 1, wherein a plurality of power terminal insulating ceramics (8) and a plurality of signal terminal insulating ceramics (9) are further disposed on the metal base, the plurality of power terminal insulating ceramics (8) surround the first to fifth power terminals to insulate the power terminals from the metal base (2), and the plurality of signal terminal insulating ceramics (9) surround the signal terminals to insulate the signal terminals from the metal base (2).

6. The smart power module of claim 1,

the driving circuit comprises 1 circuit board (63), 6 driving chips, 6 groups of dry driving bonding pads, a plurality of signal connection bonding wires and a plurality of resistance-capacitance elements arranged on the circuit board (63), wherein the circuit board (63) is welded with the 6 driving chips, 6 groups of driving bonding pads respectively close to the driving chips are arranged, the 6 groups of driving bonding pads respectively correspond to the 6 groups of driving bonding pads of the 6 power semiconductor chips, and the driving electrodes of the 6 power semiconductor chips are respectively and correspondingly connected;

the first driving chip (48) drives a sixth power semiconductor chip (29), a second signal connection bonding wire (64) is connected to PWM2 on the side plate, a driving signal enters the intelligent power module through the PWM2 and is connected to the first driving chip (48) through the second signal connection bonding wire (64), an output signal of the first driving chip (48) is connected to a first driving bonding pad (54) and is connected to a grid electrode and a source electrode bonding pad of the sixth power semiconductor chip (29) through a sixth driving bonding wire (41);

the second driving chip (49) drives a fourth power semiconductor chip (27), a third signal connection bonding wire (65) is connected to the PWM6 on the side plate, a driving signal enters the intelligent power module through the PWM4 and is connected to the second driving chip (49) through the third signal connection bonding wire (65), an output signal of the second driving chip (49) is connected to a second driving bonding pad (55) and is connected to a grid electrode and a source electrode bonding pad of the fourth power semiconductor chip (27) through a fifth driving bonding wire (40);

a third driving chip (50) drives a second power semiconductor chip (25), a fourth signal connection bonding wire (66) is connected to PWM4 on the side plate, a driving signal enters the intelligent power module through the PWM4 and is connected to the third driving chip (50) through the fourth signal connection bonding wire (66), an output signal of the third driving chip (50) is connected to a third driving bonding pad (56) and is connected to a grid electrode and a source electrode bonding pad of the second power semiconductor chip (25) through a fourth driving bonding wire (39);

the first driving chip (48), the second driving chip (49) and the third driving chip (50) are powered by the same group of external isolation power supplies, a fifth signal connection bonding wire (67) is connected to VCC4 on the side plate, and a sixth signal connection bonding wire (68) is connected to VEE4 on the side plate;

a fourth driving chip (51) drives a fifth power semiconductor chip (28), a seventh signal connection bonding wire (69) is connected to the PWM5 on the side plate, a driving signal enters the intelligent power module through the PWM5 and is connected to the fourth driving chip (51) through the seventh signal connection bonding wire (69), an output signal of the fourth driving chip (51) is connected to a fourth driving bonding pad (57) and is connected to a grid electrode and a source electrode bonding pad of the fifth power semiconductor chip (28) through a third driving bonding wire (38); the fourth driving chip (51) is powered by an external isolation power supply, and an eighth signal connection bonding wire (70) and a ninth signal connection bonding wire (71) are respectively connected to VCC3 and VEE3 on the side plate;

a fifth driving chip (52) drives a third power semiconductor chip (26), a tenth signal connection bonding wire (72) is connected to the PWM3 on the side plate, a driving signal enters the intelligent power module through the PWM3 and is connected to the fifth driving chip (52) through the tenth signal connection bonding wire (72), an output signal of the fifth driving chip (52) is connected to a fifth driving bonding pad (58) and is connected to a grid electrode and a source electrode bonding pad of the third power semiconductor chip (26) through a second driving bonding wire (37); the fifth driving chip (52) is powered by an external isolation power supply, and an eleventh signal connection bonding wire (73) and a twelfth signal connection bonding wire (74) are respectively connected to VCC2 and VEE2 on the side plate;

a sixth driving chip (53) drives the first power semiconductor chip (24), a thirteenth signal connection bonding wire (75) is connected to the PWM1 on the side plate, a driving signal PWM1 enters the intelligent power module and is connected to the sixth driving chip (53) through the thirteenth signal connection bonding wire (75), an output signal of the sixth driving chip (53) is connected to a sixth driving bonding pad (59) and is connected to a grid electrode and a source electrode bonding pad of the first power semiconductor chip (24) through a first driving bonding wire (36); the sixth driving chip (53) is supplied with power from an external isolation power supply, and a fourteenth signal connection bonding wire (76) and a fifteenth signal connection bonding wire (77) are connected to the VCC1 and the signal terminal VEE1 on the side plate, respectively.

7. The smart power module of claim 1,

the temperature detection circuit comprises a second copper-clad ceramic substrate (61), 1 temperature detection chip (60) and a plurality of resistance-capacitance components arranged on the second copper-clad ceramic substrate (61); the upper layer of the second copper-clad ceramic substrate (61) is a copper foil which is processed to form a circuit pattern according to a temperature detection circuit and comprises a sixth copper foil, a seventh copper foil and an eighth copper foil, the sixth copper foil on the copper-clad ceramic substrate (61) is bonded with a temperature detection chip (60), two pins of the temperature detection chip (60) are respectively welded on the seventh copper foil and the eighth copper foil of the copper-clad ceramic substrate (61), the temperature detection chip (60) and part of the resistance-capacitance elements form the temperature detection circuit, and a first signal connection bonding wire (62) connects an output signal of the temperature detection circuit to VT on the side plate.

8. The smart power module of claim 1, wherein, of the 6 power semiconductor chips in the three-phase full-bridge circuit, three upper tubes and corresponding three-way driver chips are distributed on the right side of the smart power module, the three-way upper tube driver circuits do not interfere with each other, and three lower tubes and corresponding three-way driver chips are distributed on the left side of the smart power module.

9. The smart power module of claim 1, wherein some or all of the first through sixth power bonding wires are respectively formed by connecting a plurality of bonding wires in parallel.

10. The smart power module according to claim 1, wherein the outer edges of the upper and lower copper foils are located on the ceramic substrate (17) at a distance from the edge of the ceramic substrate (17).