CN216390928U - Low noise amplifier, related equipment and chip - Google Patents
Low noise amplifier, related equipment and chip Download PDFInfo
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- CN216390928U CN216390928U CN202122798017.4U CN202122798017U CN216390928U CN 216390928 U CN216390928 U CN 216390928U CN 202122798017 U CN202122798017 U CN 202122798017U CN 216390928 U CN216390928 U CN 216390928U
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- H—ELECTRICITY
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- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
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Abstract
The utility model provides a low-noise amplifier, which comprises a bias circuit, an input matching network circuit, an amplifying circuit and a load network circuit, wherein the input matching network circuit, the amplifying circuit and the load network circuit are sequentially connected; the input matching network circuit comprises a first capacitor, a second capacitor, an eighth capacitor and a first inductor; the load network circuit comprises a primary matching circuit module, and the primary matching circuit module comprises a fourth inductor, a sixth inductor and a ninth capacitor. The utility model also provides WiFi 6E communication equipment and a chip. The low-noise amplifier has wide working frequency band and high performance index.
Description
Technical Field
The utility model relates to the field of amplifier circuits, in particular to a low-noise amplifier, WiFi 6E communication equipment and a chip.
Background
At present, in the development of communication technology, a Low Noise Amplifier (LNA) plays an increasingly important role in a communication system, and the LNA is a very important module in a radio frequency front end of the communication system, and is used for processing signals received by an antenna and weakening Noise of a communication module. The performance of the low noise amplifier directly determines the sensitivity of a receiver in the communication system, and then a signal spectrum template, and the like, thereby influencing and determining various performance indexes of the whole communication system. With the proposal of the ultra-wideband WiFi 6E concept, the working bandwidth of the WiFi 6E communication low-noise amplifier is further expanded and is widened from 5.15GHz-5.85GHz to 5.15GHz-7.125 GHz. Due to the ultra-wide working frequency band, WiFi 6E solves the problem of insufficient WiFi spectrum resources again, and provides higher transmission rate, so that the method is very suitable for high-performance application.
The WiFi 6E communication low-noise amplifier in the related art comprises a bias circuit and an input matching network circuit, an amplifying circuit and a load network circuit which are connected in sequence. The input matching network circuit functions to match the input impedance within the operational bandwidth of the LNA to avoid interference with the antenna/rf filter in the communication system. The amplifier circuit has a cascode structure in which a main body is composed of two E _ mode transistors. The impedance characteristics of the load network circuit directly affect the power gain amplitude and the gain flatness within the operating bandwidth of the LNA, and the load network circuit includes an ESD protection circuit, which, in addition to performing an ESD protection function, actually has a large effect on the circuit due to its parasitic capacitance, making it a part of the load matching network.
However, the performance index of the WiFi 6E communication low noise amplifier of the related art is limited by the circuit under the condition of wider operation bandwidth. Wherein the input matching network and the load matching network have narrower bandwidths. In an ultra-wideband environment, a WiFi 6E communication low noise amplifier is some important technical indexes, for example, indexes such as gain, S11, S22, and noise coefficient are seriously deteriorated, and the requirement of WiFi 6E for an ultra-wideband LNA cannot be met.
Therefore, there is a need to provide a new low noise amplifier, related device and chip to solve the above problems.
SUMMERY OF THE UTILITY MODEL
Aiming at the defects of the prior art, the utility model provides a low-noise amplifier with wide working frequency band and high performance index, WiFi 6E communication equipment and a chip.
In order to solve the above technical problem, the present invention provides a low noise amplifier, which includes a bias circuit, and an input matching network circuit, an amplifying circuit and a load network circuit connected in sequence;
the bias circuit is connected with the amplifying circuit and used for providing bias voltage for the amplifying circuit;
the input matching network circuit is used for matching impedance of an externally connected preceding stage circuit with the amplifying circuit;
the load network circuit is used for realizing impedance matching with a post-stage circuit connected with the outside;
the input matching network circuit comprises a first capacitor, a second capacitor, a first inductor and a fifth inductor;
a first end of the first capacitor is used as an input end of the input matching network circuit;
the second end of the first capacitor is respectively connected to the first end of the first inductor and the first end of the fifth inductor;
a second end of the fifth inductor is used as an output end of the input matching network circuit;
the second end of the first inductor is connected to the first end of the second capacitor;
the second end of the second capacitor is connected to the ground;
the load network circuit comprises a primary matching circuit module, and the primary matching circuit module comprises a fourth inductor, a sixth inductor and a ninth capacitor;
the first end of the fourth inductor is used as the input end of the primary matching circuit module;
a second end of the fourth inductor is connected to a first end of the sixth inductor and a first end of the ninth capacitor respectively, and serves as an output end of the first-stage matching circuit module;
a second terminal of the sixth inductor and a second terminal of the ninth capacitor are both connected to ground.
Preferably, the low noise amplifier further includes a third capacitor, a fourth capacitor, an eighth capacitor, a fifth resistor, a sixth resistor, an eighth resistor, a second inductor, a fifth transistor, and a second voltage regulator;
the load network circuit further comprises a third inductor, a seventh inductor, a fifth capacitor, a sixth capacitor, a seventh resistor, a ninth resistor and a fourth transistor;
the amplifying circuit includes a first transistor and a second transistor;
the input end of the input matching network circuit is used as the signal input end of the low noise amplifier;
the output end of the input matching network circuit is respectively connected to the output end of the bias circuit, the first end of the eighth capacitor and the grid electrode of the first transistor;
a second end of the eighth capacitor is connected to ground;
the source electrode of the first transistor is connected to the ground through the second inductor in series, and the drain electrode of the first transistor is connected to the source electrode of the second transistor;
a gate of the second transistor is connected to a first end of the third capacitor, a second end of the fifth resistor and a second end of the sixth resistor respectively;
the drain electrode of the second transistor is respectively connected with the first end of the fourth capacitor, the first end of the fifth capacitor and the second end of the third inductor;
the second end of the third capacitor is connected to the ground; a first end of the fifth resistor is connected to a second end of the fourth capacitor;
a first end of the sixth resistor is connected to a first end of the ninth resistor, a first end of the sixth capacitor and a source of the fifth transistor respectively;
a second end of the ninth resistor is connected to a first end of the third inductor;
a second end of the sixth capacitor is connected to ground;
the drain of the fifth transistor is connected to the positive electrode end of the second voltage-stabilizing source, and the gate of the fifth transistor is connected to the second end of the eighth resistor;
the negative end of the second voltage-stabilizing source is connected to the ground;
a first end of the eighth resistor is connected to a first end of the seventh resistor and serves as a control signal input end of the low noise amplifier;
a second end of the seventh resistor is connected to a gate of the fourth crystal;
the source electrode of the fourth crystal is connected to the second end of the fifth capacitor, and the drain electrode of the fourth crystal is connected to the first end of the seventh capacitor;
the second end of the seventh capacitor is connected to the input end of the first-stage matching circuit module;
the output end of the first-stage matching circuit module is connected to the first end of the seventh inductor;
and the second end of the seventh inductor is used as the signal output end of the low noise amplifier.
Preferably, the bias circuit comprises a first voltage regulator, a third transistor, a first resistor, a second resistor, a third resistor and a fourth resistor;
the negative end of the first voltage-stabilizing source is connected to the ground, and the positive end of the first voltage-stabilizing source is connected to the first end of the first resistor;
a second end of the first resistor is respectively connected to a drain of the third transistor, a first end of the second resistor, a first end of the third resistor and a first end of the fourth resistor;
the source electrode of the third transistor is connected to the ground, and the grid electrode of the third transistor is connected to the second end of the second resistor;
a second end of the third resistor is connected to ground;
and the second end of the fourth resistor is used as the output end of the bias circuit.
Preferably, the one transistor and the two transistors are both E _ mode transistors of GaAs-based EDpHEMT technology, and the four transistors and the five transistors are both D _ mode switching transistors of GaAs-based EDpHEMT technology.
Preferably, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all NMOS transistors.
Preferably, the second inductor L2 is adjustable in parameter, and the ninth resistor is adjustable in parameter.
Preferably, the fourth inductor, the sixth inductor and the ninth capacitor are all adjustable in parameter.
The utility model also provides WiFi 6E communication equipment, and the WiFi 6E communication equipment comprises the low noise amplifier.
The utility model also provides a chip, which comprises the low-noise amplifier, and is made by the GaAs-based EDpHEMT process.
Compared with the prior art, the low-noise amplifier has the advantages that the input matching network circuit is formed by the first capacitor, the second capacitor, the first inductor and the fifth inductor, so that the input matching network circuit forms a two-stage LC filter network, the first capacitor, the second capacitor and the first inductor form a one-stage LC filter network, the fifth inductor and an eighth capacitor connected with the fifth inductor form a two-stage LC filter network, the two-stage LC filter network further expands the bandwidth, and the eighth capacitor is actually formed by the grid/leakage parasitic capacitor of the amplifying circuit. The WiFi 6E communication low-noise amplifier is provided with a primary matching circuit module through the load network circuit, and the primary matching circuit module comprises a fourth inductor, a sixth inductor and a ninth capacitor. The ninth capacitor is a parasitic capacitor of the ESD, the sixth inductor and the ninth capacitor form a parallel resonance circuit, and the parallel resonance circuit and the fourth inductor form a primary matching circuit, so that the bandwidth of the primary matching circuit is further expanded. The circuit structure enables the S11 index, the S22 index and the gain index of the low noise amplifier to meet the performance requirements of WiFi 6E under the ultra-wide working frequency band of 5.15GHz-7.125 GHz. Therefore, the low-noise amplifier, the mobile communication equipment and the chip have wide working frequency band and high performance index.
Drawings
The present invention will be described in detail below with reference to the accompanying drawings. The foregoing and other aspects of the utility model will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings. In the drawings, there is shown in the drawings,
FIG. 1 is a circuit diagram of a low noise amplifier according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of an input matching network circuit of a low noise amplifier according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a first stage matching circuit module of a low noise amplifier according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a second low noise amplifier according to the second embodiment of the present invention;
FIG. 5 is a graph illustrating the reflection coefficient S11 of the LNA according to the embodiment of the present invention;
FIG. 6 is a diagram illustrating the S22 index curve of the LNA in accordance with the embodiment of the present invention;
fig. 7 is a schematic diagram of a gain curve of a low noise amplifier according to an embodiment of the utility model.
Detailed Description
The following detailed description of embodiments of the utility model refers to the accompanying drawings.
The embodiments/examples described herein are specific embodiments of the present invention, are intended to be illustrative of the concepts of the present invention, are intended to be illustrative and exemplary, and should not be construed as limiting the embodiments and scope of the utility model. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include those which make any obvious replacement or modification of the embodiments described herein, and all of which are within the scope of the present invention.
(embodiment one)
The embodiment of the utility model provides a low-noise amplifier 100 which is used for ultra-wideband WiFi 6E communication.
Please refer to fig. 1-3, wherein fig. 1 is a circuit diagram of a low noise amplifier according to an embodiment of the present invention.
The low noise amplifier 100 is applied to a WiFi 6E product with an operating band of 5.15GHz-7.125 GHz.
In this embodiment, the low noise amplifier 100 is manufactured by using a GaAs-based EDpHEMT process.
The low noise amplifier 100 includes a bias circuit 4, and an input matching network circuit 1, an amplifying circuit 2, and a load network circuit 3 connected in sequence.
The bias circuit 4 is used for providing a bias voltage of the amplifying circuit 2, and the bias circuit 4 is connected with the amplifying circuit 2.
The input matching network circuit 1 is used to match the impedance of the externally connected preceding stage circuit with the amplifier circuit 2. The input matching network circuit 1 achieves matching of the input impedance within the operational bandwidth of the LNA to avoid interference with the antenna/rf filter in the communication system.
Referring to fig. 2, fig. 2 is a circuit diagram of an input matching network circuit of a low noise amplifier 100 according to an embodiment of the utility model.
Specifically, the input matching network circuit 1 includes a first capacitor C1, a second capacitor C2, a first inductor L1, and a fifth inductor L5.
The circuit structure of the input matching network circuit 1 is as follows:
a first terminal of the first capacitor C1 serves as an input terminal of the input matching network circuit 1.
The second terminal of the first capacitor C1 is connected to the first terminal of the first inductor L1 and the first terminal of the fifth inductor L5, respectively.
A second terminal of the fifth inductor L5 serves as an output terminal of the input matching network circuit 1.
The second terminal of the first inductor L1 is connected to the first terminal of the second capacitor C2.
The second end of the second capacitor C2 is connected to ground GND.
The input matching network circuit 1 forms a two-stage LC filter network, wherein the first capacitor C1, the second capacitor C2 and the first inductor L1 form a one-stage LC filter network, and the fifth inductor L5 forms a two-stage LC filter network with the gate/drain parasitic capacitor of the transistor of the amplifying circuit 2 connected thereto. The two-stage LC filter network further extends the bandwidth of the low noise amplifier 100.
The amplifying circuit 2 is used for amplifying signals. In the present embodiment, the amplifier circuit 2 is configured by a cascode-structured amplifier circuit including two E _ mode transistors.
The load network circuit 3 is used for realizing impedance matching with a post-stage circuit which is externally connected. The impedance characteristics of the load network circuit 3 directly affect the power gain amplitude and gain flatness within the operating bandwidth of the LNA.
The load network circuit 3 comprises a primary matching circuit module 31.
Referring to fig. 3, fig. 3 is a circuit diagram of a first stage matching circuit module of the low noise amplifier 100 according to an embodiment of the utility model.
Specifically, the primary matching circuit module 31 includes a fourth inductor L4, a sixth inductor L6, and a ninth capacitor C9.
A first terminal of the fourth inductor L4 is used as an input terminal of the primary matching circuit module 31.
A second terminal of the fourth inductor L4 is connected to the first terminal of the sixth inductor L6 and the first terminal of the ninth capacitor C9, respectively, and serves as an output terminal of the primary matching circuit module 31.
A second terminal of the sixth inductor L6 and a second terminal of the ninth capacitor C9 are both connected to ground GND.
The ninth capacitor C9 is a parasitic capacitor of the ESD, the sixth inductor L6 and the ninth capacitor C9 form a parallel resonant circuit, and the parallel resonant circuit and the fourth inductor L4 form a primary matching circuit, so that the bandwidth of the low noise amplifier 100 is further expanded by the primary matching circuit.
(second embodiment)
The low noise amplifier of the second embodiment is one specific circuit structure of the low noise amplifier 100 of the first embodiment.
Referring to fig. 4, fig. 4 is a circuit diagram of a second low noise amplifier according to an embodiment of the utility model.
In the second embodiment, the low noise amplifier 100 further includes a third capacitor C3, a fourth capacitor C4, an eighth capacitor C8, a fifth resistor R5, a sixth resistor R6, an eighth resistor R8, a second inductor L2, a fifth transistor M5, and a second voltage regulator VDC 2. Wherein the eighth capacitor C8 is formed by the gate/drain parasitic capacitance of the E _ mode transistor of the amplifying circuit 2.
In this embodiment, the five-transistor M5 is a D _ mode switching transistor of the GaAs-based EDpHEMT process.
The load network circuit 3 further includes a third inductor L3, a seventh inductor L7, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C6, a seventh resistor R7, a ninth resistor R9, and a fourth transistor M4.
In this embodiment, the fourth transistor M4 is a D _ mode switch transistor of GaAs-based EDpHEMT process.
The amplifying circuit 2 includes a first transistor M1 and a second transistor M2.
In this embodiment, the transistor M1 and the transistor M2 are both E _ mode transistors of GaAs based EDpHEMT technology.
In this embodiment, the bias circuit 4 includes a first voltage regulator VDC1, a third transistor M3, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.
The circuit structure of the bias circuit 4 is as follows:
the negative terminal of the first voltage-stabilizing source VDC1 is connected to the ground GND, and the positive terminal of the first voltage-stabilizing source VDC1 is connected to the first terminal of the first resistor R1.
A second end of the first resistor R1 is connected to the drain of the third transistor M3, the first end of the second resistor R2, the first end of the third resistor R3, and the first end of the fourth resistor R4, respectively.
The source of the third transistor M3 is connected to the ground GND, and the gate of the third transistor M3 is connected to the second end of the second resistor R2.
The second end of the third resistor R3 is connected to ground GND.
A second terminal of the fourth resistor R4 serves as an output terminal of the bias circuit.
In another embodiment, the one transistor M1, the two transistor M2, the three transistor M3, the four transistor M4 and the five transistor M5 are all NMOS transistors. The transistors are all NMOS transistors, so that the circuit is easy to manufacture chips, the manufacture and application of the chips are facilitated, and the cost of the chips can be reduced.
In this embodiment, the first voltage regulator source VDC1 and the second voltage regulator source VDC2 are both made of battery packs.
The circuit structure of the low noise amplifier 100 in the second embodiment is:
the input end of the input matching network circuit 1 serves as a signal input end LNAin of the low noise amplifier 100.
An output terminal of the input matching network circuit 1 is respectively connected to the output terminal of the bias circuit 4, the second terminal of the eighth capacitor C8 and the gate of the first transistor M1.
A second terminal of the eighth capacitor C8 is connected to ground GND.
The source of the first transistor M1 is connected to ground GND by connecting the second inductor L2 in series, and the drain of the first transistor M1 is connected to the source of the second transistor M2.
The gate of the second transistor M2 is connected to the first terminal of the third capacitor C3, the second terminal of the fifth resistor R5 and the second terminal of the sixth resistor R6, respectively.
The drain of the second transistor M2 is connected to the first terminal of the fourth capacitor C4, the first terminal of the fifth capacitor C5 and the second terminal of the third inductor L3, respectively.
A second end of the third capacitor C3 is connected to the ground GND; the first end of the fifth resistor R5 is connected to the second end of the fourth capacitor C4.
A first end of the sixth resistor R6 is connected to a first end of the ninth resistor R9, a first end of the sixth capacitor C6, and a source of the fifth transistor M5, respectively.
A second end of the ninth resistor R9 is connected to a first end of the third inductor L3;
a second terminal of the sixth capacitor C6 is connected to ground GND.
The drain of the fifth transistor M5 is connected to the positive terminal of the second voltage regulator VDC2, and the gate of the fifth transistor M5 is connected to the second terminal of the eighth resistor R8.
The negative terminal of the second regulated power supply VDC2 is connected to ground GND.
A first end of the eighth resistor R8 is connected to a first end of the seventh resistor R7, and serves as a control signal input terminal LNAen of the low noise amplifier 100.
A second terminal of the seventh resistor R7 is connected to the gate of the fourth crystal.
The source of the fourth crystal is connected to the second terminal of the fifth capacitor C5, and the drain of the fourth crystal is connected to the first terminal of the seventh capacitor C6.
A second end of the seventh capacitor C6 is connected to the input end of the primary matching circuit module 31.
The output terminal of the primary matching circuit module 31 is connected to the first terminal of the seventh inductor L7.
A second end of the seventh inductor L7 is used as the signal output end LNAout of the low noise amplifier 100.
The principle of the low noise amplifier 100 for realizing wide working frequency band and high performance index is as follows:
in the second implementation, the input matching network circuit 1 forms a two-stage LC filter network, wherein the first capacitor C1, the second capacitor C2 and the first inductor L1 form a one-stage LC filter network, and the fifth inductor L5 and the eighth capacitor C8 form a two-stage LC filter network. Wherein the eighth capacitor C8 is formed by the gate/drain parasitic capacitance of the first transistor M1 of the amplifying circuit 2.
The two-stage LC filter network further extends the bandwidth of the low noise amplifier 100. Therefore, the reflection coefficient S11 of the low noise amplifier in the frequency range of 5.1GHz-7.1GHz of the input radio frequency signal is less than-10.3 dB.
On the basis, the second inductor L2 is adjustable in parameter. The second inductance L2 of the first transistor M1 is properly reduced to make the reflection coefficient S11 worse within an acceptable range, which leads to a certain increase in the overall gain of the low noise amplifier 100. Therefore, the gain of the low noise amplifier 100 in the frequency range of 5.1GHz to 7.1GHz of the input radio frequency signal is greater than 16.6 dB.
In the second embodiment, in order to solve the ultra-wideband problem, the low noise amplifier 10 adopts two circuit structures:
the first circuit structure is that the ninth resistor R9 is added at the front end of the third inductor L3 for power supply, and an amplifier feedback circuit consisting of the fourth capacitor C4 and the fifth resistor R5 is matched to expand the bandwidth of a frequency band.
The ninth resistor R9 is adjustable in parameter. Adjusting the resistance of the ninth resistor R9 can expand the matching bandwidth and increase the gain flatness.
The second circuit structure is that a primary matching circuit module 31 is disposed in the load network circuit 3, wherein the primary matching circuit module 31 includes a fourth inductor L4, a sixth inductor L6, and a ninth capacitor C9. The sixth inductor L6 and the parasitic capacitor formed by ESD, i.e., the ninth capacitor C9, form a parallel resonant circuit, and this resonant circuit is combined with L4 to form a newly added primary matching circuit. The fourth inductor L4, the sixth inductor L6 and the ninth capacitor C9 are all adjustable in parameter, so that the matching bandwidth can be expanded, and the gain flatness is increased.
The following is the circuit simulation result of the low noise amplifier 10 in the second embodiment:
referring to fig. 5, fig. 5 is a graph illustrating a reflection coefficient S11 of a low noise amplifier according to an embodiment of the utility model.
The reflection coefficient S11 index of the low noise amplifier 100 near the point m14 at the frequency of 5.1GHz is-9.701 dB.
The reflection coefficient S11 index of the low noise amplifier 100 near the point m15 at the frequency of 6.0GHz is-9.627 dB.
The reflection coefficient S11 index of the low noise amplifier 100 near the point m16 at the frequency of 7.1GHz is-10.216 dB.
Referring to fig. 6, fig. 6 is a schematic diagram of an S22 curve of a low noise amplifier according to an embodiment of the utility model.
The S22 index of the low noise amplifier 100 is 13.781dB near the point m17 at the frequency of 5.1GHz of the input radio frequency signal.
The reflection coefficient S22 index of the low noise amplifier 100 is 12.932dB near the point m18 at the frequency of 6.0GHz of the input radio frequency signal.
The reflection coefficient S22 index of the low noise amplifier 100 is 9.474dB near the point m19 at the frequency of 7.1GHz of the input radio frequency signal.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating a gain curve of a low noise amplifier according to an embodiment of the utility model.
The gain index of the low noise amplifier 100 around the point m7 at the frequency of 5.1GHz is 16.683 dB.
The gain index of the low noise amplifier 100 around the point m8 at which the input radio frequency signal is at a frequency of 6.0GHz is 17.745 dB.
The gain index of the low noise amplifier 100 around the point m9 at which the input radio frequency signal is at a frequency of 7.1GHz is 16.632 dB.
By integrating the simulation results, the S11 index, the S22 index and the gain index of the low noise amplifier 100 meet the performance requirements of the WiFi 6E under the ultra-wide working frequency band of 5.15GHz-7.125 GHz.
It should be noted that the related resistors, capacitors, inductors, voltage regulators and transistors used in the present invention are all common components in the field, and have indexes and parameters adjusted according to practical applications, and are not described in detail herein.
The utility model also provides a mobile communication device. The mobile communication device comprises a low noise amplifier 100 as described. The mobile communication device can operate with a wide frequency band and high performance index by using the low noise amplifier 100.
The utility model also provides a chip. The chip includes the low noise amplifier 100. The chip is made by a GaAs-based EDpHEMT process. The chip is because of adopting low noise amplifier 100 can realize that operating frequency bandwidth and performance index are high.
Compared with the prior art, the low-noise amplifier has the advantages that the input matching network circuit is formed by the first capacitor, the second capacitor, the first inductor and the fifth inductor, so that the input matching network circuit forms a two-stage LC filter network, the first capacitor, the second capacitor and the first inductor form a one-stage LC filter network, the fifth inductor and an eighth capacitor connected with the fifth inductor form a two-stage LC filter network, the two-stage LC filter network further expands the bandwidth, and the eighth capacitor is actually formed by the grid/leakage parasitic capacitor of the amplifying circuit. The WiFi 6E communication low-noise amplifier is provided with a primary matching circuit module through the load network circuit, and the primary matching circuit module comprises a fourth inductor, a sixth inductor and a ninth capacitor. The ninth capacitor is a parasitic capacitor of the ESD, the sixth inductor and the ninth capacitor form a parallel resonance circuit, and the parallel resonance circuit and the fourth inductor form a primary matching circuit, so that the bandwidth of the primary matching circuit is further expanded. The circuit structure enables the S11 index, the S22 index and the gain index of the low noise amplifier to meet the performance requirements of WiFi 6E under the ultra-wide working frequency band of 5.15GHz-7.125 GHz. Therefore, the low-noise amplifier, the mobile communication equipment and the chip have wide working frequency band and high performance index.
It should be noted that the above-mentioned embodiments described with reference to the drawings are only intended to illustrate the present invention and not to limit the scope of the present invention, and it should be understood by those skilled in the art that modifications and equivalent substitutions can be made without departing from the spirit and scope of the present invention. Furthermore, unless the context indicates otherwise, words that appear in the singular include the plural and vice versa. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.
Claims (9)
1. A low noise amplifier comprises a bias circuit, an input matching network circuit, an amplifying circuit and a load network circuit which are connected in sequence;
the bias circuit is connected with the amplifying circuit and used for providing bias voltage for the amplifying circuit;
the input matching network circuit is used for realizing impedance matching between an externally connected preceding stage circuit and the amplifying circuit;
the load network circuit is used for realizing impedance matching with a post-stage circuit connected with the outside; it is characterized in that the preparation method is characterized in that,
the input matching network circuit comprises a first capacitor, a second capacitor, a first inductor and a fifth inductor;
a first end of the first capacitor is used as an input end of the input matching network circuit;
the second end of the first capacitor is respectively connected to the first end of the first inductor and the first end of the fifth inductor;
a second end of the fifth inductor is used as an output end of the input matching network circuit;
the second end of the first inductor is connected to the first end of the second capacitor;
the second end of the second capacitor is connected to the ground;
the load network circuit comprises a primary matching circuit module, and the primary matching circuit module comprises a fourth inductor, a sixth inductor and a ninth capacitor;
the first end of the fourth inductor is used as the input end of the primary matching circuit module;
a second end of the fourth inductor is connected to a first end of the sixth inductor and a first end of the ninth capacitor respectively, and serves as an output end of the first-stage matching circuit module;
a second terminal of the sixth inductor and a second terminal of the ninth capacitor are both connected to ground.
2. The low noise amplifier of claim 1,
the low noise amplifier also comprises a third capacitor, a fourth capacitor, an eighth capacitor, a fifth resistor, a sixth resistor, an eighth resistor, a second inductor, a fifth transistor and a second voltage-stabilizing source;
the load network circuit further comprises a third inductor, a seventh inductor, a fifth capacitor, a sixth capacitor, a seventh resistor, a ninth resistor and a fourth transistor;
the amplifying circuit includes a first transistor and a second transistor;
the input end of the input matching network circuit is used as the signal input end of the low noise amplifier;
the output end of the input matching network circuit is respectively connected to the output end of the bias circuit, the first end of the eighth capacitor and the grid electrode of the first transistor;
a second end of the eighth capacitor is connected to ground;
the source electrode of the first transistor is connected to the ground through the second inductor in series, and the drain electrode of the first transistor is connected to the source electrode of the second transistor;
a gate of the second transistor is connected to a first end of the third capacitor, a second end of the fifth resistor and a second end of the sixth resistor respectively;
the drain electrode of the second transistor is respectively connected with the first end of the fourth capacitor, the first end of the fifth capacitor and the second end of the third inductor;
the second end of the third capacitor is connected to the ground; a first end of the fifth resistor is connected to a second end of the fourth capacitor;
a first end of the sixth resistor is connected to a first end of the ninth resistor, a first end of the sixth capacitor and a source of the fifth transistor respectively;
a second end of the ninth resistor is connected to a first end of the third inductor;
a second end of the sixth capacitor is connected to ground;
the drain of the fifth transistor is connected to the positive electrode end of the second voltage-stabilizing source, and the gate of the fifth transistor is connected to the second end of the eighth resistor;
the negative end of the second voltage-stabilizing source is connected to the ground;
a first end of the eighth resistor is connected to a first end of the seventh resistor and serves as a control signal input end of the low noise amplifier;
a second end of the seventh resistor is connected to a gate of the fourth crystal;
the source electrode of the fourth crystal is connected to the second end of the fifth capacitor, and the drain electrode of the fourth crystal is connected to the first end of the seventh capacitor;
the second end of the seventh capacitor is connected to the input end of the first-stage matching circuit module;
the output end of the first-stage matching circuit module is connected to the first end of the seventh inductor;
and the second end of the seventh inductor is used as the signal output end of the low noise amplifier.
3. The low noise amplifier of claim 2, wherein the bias circuit comprises a first regulator, a third transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor;
the negative end of the first voltage-stabilizing source is connected to the ground, and the positive end of the first voltage-stabilizing source is connected to the first end of the first resistor;
a second end of the first resistor is respectively connected to a drain of the third transistor, a first end of the second resistor, a first end of the third resistor and a first end of the fourth resistor;
the source electrode of the third transistor is connected to the ground, and the grid electrode of the third transistor is connected to the second end of the second resistor;
a second end of the third resistor is connected to ground;
and the second end of the fourth resistor is used as the output end of the bias circuit.
4. The lna of claim 3, wherein the one and two transistors are E _ mode transistors of the GaAs based EDpHEMT process, and the four and five transistors are D _ mode switching transistors of the GaAs based EDpHEMT process.
5. The low noise amplifier of claim 3, wherein the one transistor, the two transistors, the three transistors, the four transistors, and the five transistors are all NMOS transistors.
6. The LNA of claim 3, where the second inductor L2 is parametrically adjustable and the ninth resistor is parametrically adjustable.
7. The low noise amplifier of claim 3, wherein the fourth inductor, the sixth inductor, and the ninth capacitor are all parametrically adjustable.
8. A WiFi 6E communication device, characterized in that the WiFi 6E communication device comprises a low noise amplifier as claimed in any one of claims 1-7.
9. A chip for WiFi 6E communication, wherein the chip comprises the low noise amplifier of any one of claims 1-7, and the chip is made by GaAs based EDpHEMT process.
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2022/125266 WO2023082932A1 (en) | 2021-10-18 | 2022-10-14 | Low-noise amplifier, related device and chip |
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| CN202122507578 | 2021-10-18 | ||
| CN2021225075784 | 2021-10-18 |
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| WO (1) | WO2023082932A1 (en) |
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| WO2023082932A1 (en) * | 2021-10-18 | 2023-05-19 | 深圳飞骧科技股份有限公司 | Low-noise amplifier, related device and chip |
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| EP2037573A1 (en) * | 2007-09-17 | 2009-03-18 | Seiko Epson Corporation | Ultra-low power consumption low noise amplifier |
| CN102332867B (en) * | 2011-07-22 | 2014-08-06 | 复旦大学 | Low-noise amplifier with single-end circuit compensation structure |
| CN207475495U (en) * | 2017-09-30 | 2018-06-08 | 成都嘉纳海威科技有限责任公司 | A kind of High-efficiency high-gain Doherty stacks power amplifier |
| CN110719074B (en) * | 2019-09-23 | 2023-06-20 | 航天科工微电子系统研究院有限公司 | Tunable broadband low noise amplifier |
| CN216390928U (en) * | 2021-10-18 | 2022-04-26 | 深圳飞骧科技股份有限公司 | Low noise amplifier, related equipment and chip |
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| WO2023082932A1 (en) * | 2021-10-18 | 2023-05-19 | 深圳飞骧科技股份有限公司 | Low-noise amplifier, related device and chip |
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