CN106849881B - Broadband monolithic integration low-noise amplifier - Google Patents

Broadband monolithic integration low-noise amplifier Download PDF

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CN106849881B
CN106849881B CN201611192369.2A CN201611192369A CN106849881B CN 106849881 B CN106849881 B CN 106849881B CN 201611192369 A CN201611192369 A CN 201611192369A CN 106849881 B CN106849881 B CN 106849881B
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inductor
bias power
stage
power supply
capacitor
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CN106849881A (en
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杨立
王娅妮
毕波
李卫民
张佃伟
文武
李永峰
段冲
侯训平
焦洋
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Mxtronics Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H03F1/48—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
    • H03F1/483—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/372—Noise reduction and elimination in amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Abstract

The invention discloses a broadband monolithic integration low-noise amplifier. The amplifier comprises a first-stage amplifier, a second-stage amplifier, a third-stage amplifier, a two-stage interstage matching and a two-stage three-stage interstage matching. The first-stage amplifier mainly comprises an NMOS tube, a resistor, four inductors, a capacitor and two bias power supplies; the second-stage amplifier mainly comprises an NMOS tube, two resistors, two inductors, a microstrip line and two bias power supplies; the third-stage amplifier mainly comprises an NMOS tube, two resistors, two inductors, a capacitor, a microstrip line and two bias power supplies; the first-stage and second-stage interstage matching mainly comprises a capacitor and an inductor; the two-stage and three-stage interstage matching mainly comprises a capacitor and an inductor. The invention has the characteristics of miniaturization, low noise, high gain, low cost and high reliability.

Description

Broadband monolithic integration low-noise amplifier
Technical Field
The invention belongs to the field of wireless communication, and relates to a broadband monolithic integrated low-noise amplifier.
Background
A low noise amplifier is an amplifier with a very low noise figure. The high-frequency or intermediate-frequency radio frequency amplifier is generally used in high-frequency or intermediate-frequency radio receivers of various radio receivers in the fields of satellite communication, radar communication and the like, and in amplifying circuits of electronic detection equipment so as to improve the sensitivity of the receivers or the electronic detection equipment. In the case of amplifying a weak signal, the noise of the amplifier itself may cause serious interference to the signal, and therefore it is desirable to further reduce the noise to improve the signal-to-noise ratio of the output.
Monolithic Microwave Integrated Circuits (MMICs) are one of the best choices for designing and manufacturing millimeter wave low noise amplifier integrated circuits due to their characteristics of low circuit loss, low noise, wide frequency band, large dynamic range, high power, high additional efficiency, and strong electromagnetic radiation resistance. The existing low noise amplifier has a narrow frequency band, and if the bandwidth is enlarged according to the design method of the existing low noise amplifier, the noise is increased, how to realize low noise and high gain in a wider frequency band and avoid low frequency oscillation is a design difficulty and a key point of the existing low noise amplifier.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the defects of the prior art are overcome, the broadband monolithic integration low-noise amplifier is provided, low noise and high gain are achieved in a wider frequency band, low-frequency oscillation is avoided, and the circuit is stable.
The technical solution of the invention is as follows: a wideband monolithically integrated low noise amplifier, comprising: the amplifier comprises a first-stage amplifier, a second-stage amplifier, a third-stage amplifier, a two-stage interstage matching network and a two-stage three-stage interstage matching network;
the first-stage amplifier comprises an NMOS transistor M1, a resistor R1, an inductor L1, an inductor L2, an inductor L3, an inductor L4, a capacitor C1, a bias power supply VGS1 and a bias power supply VDS 1; the second-stage amplifier (200) comprises an NMOS transistor M2, a resistor R2, a resistor R3, an inductor L5, an inductor L6, a microstrip line TL1, a bias power supply VGS2 and a bias power supply VDS 2; the third-stage amplifier comprises an NMOS transistor M3, a resistor R4, a resistor R5, an inductor L7, an inductor L8, a capacitor C2, a microstrip line TL2, a bias power supply VGS3 and a bias power supply VDS 3; the primary and secondary interstage matching networks comprise a capacitor C3 and an inductor L9; the two-stage interstage matching network comprises a capacitor C4 and an inductor L10;
radio frequency signal RFinThe voltage is input to the grid of an NMOS tube M1 through a series circuit consisting of a capacitor C1 and an inductor L1, the grid of the NMOS tube M1 is connected to the anode of a bias power supply VGS1 through an inductor L2, the source of the NMOS tube M1 is grounded through an inductor L4, the drain of the NMOS tube M1 is divided into two paths, one path is connected to the anode of a bias power supply VDS1 through a series circuit consisting of a resistor R1 and an inductor L3, the other path is connected to the grid of an NMOS tube M2 in a second-stage amplifier through a series circuit consisting of a capacitor C3 and an inductor L9, the cathode of the bias power supply VGS1 and the cathode of the VDS1 are grounded;
the gate of the NMOS transistor M2 is connected to the anode of the bias power source VGS2 through the series circuit of the resistor R2 and the inductor L5, the source of the NMOS transistor M2 is grounded through the microstrip line TL1, the drain of the NMOS transistor M2 is divided into two paths, one of the two paths is connected to the anode of the bias power source VDS2 through the series circuit of the resistor R3 and the inductor L6, the other path is connected to one end of the capacitor C4, the other end of the capacitor C4 is connected to one end of the inductor L10 and the gate of the NMOS transistor M3 in the third-stage amplifier, the other end of the inductor L10 is grounded, the cathode of the bias power source VGS2 and the cathode of the VDS2 are grounded;
the gate of the NMOS transistor M3 is connected to the positive electrode of the bias power supply VGS3 through the series circuit of the resistor R4 and the inductor L7, the source of the NMOS transistor M3 is grounded through the microstrip line TL2, the drain of the NMOS transistor M3 is divided into two paths, one of the two paths is connected to the positive electrode of the bias power supply VDS3 through the series circuit of the resistor R5 and the inductor L8, the other path is connected to one end of the capacitor C2, and the other end of the capacitor C2 outputs a radio frequency signal RF signaloutThe cathodes of the bias supplies VGS3 and VDS3 are grounded.
The single finger grid width of the NMOS tube M1 is 25 μ M, the single cell has 6 finger grid bars, and the total grid width is 150 μ M; the single finger grid width of the NMOS tube M2 is 40 μ M, the single cell has 2 finger grid bars, and the total grid width is 80 μ M; the single finger grid width of the NMOS tube M3 is 75 μ M, the single cell has 2 finger grid bars, and the total grid width is 150 μ M.
The resistance value of the R5 is 50 omega, the output resistor is matched to 50 omega, and no matching circuit is required to be additionally configured.
The bias power sources VGS1, VGS2 and VGS3 have the same voltage, and the bias power sources VDS1, VDS2 and VDS3 have the same voltage.
The wideband monolithically integrated low noise amplifier of the present invention has several significant advantages over conventional designs:
(1) the input end of the first-stage amplifier adopts a noise matching circuit, the circuit structure of the first-stage amplifier is formed by a single inductor, the structure is simple, the chip area is saved, the cost is reduced, and the noise of the low-noise amplifier in the whole bandwidth is lower than 1.8 dB.
(2) The invention adopts a three-stage amplifier circuit structure, designs different transistor structure parameters and obtains stable high gain. The gain of the low noise amplifier is not lower than 19dB in the whole bandwidth, and the gain is stably output by utilizing the interstage matching network, and the gain flatness of the low noise amplifier is only +/-1 dB.
(3) The invention increases the bandwidth through the first-level interstage matching network and the second-level interstage matching network, realizes low noise and high gain under wider bandwidth, the circuit bandwidth is 9GHz, and the highest frequency can reach 14 GHz.
(4) The invention can obtain high gain and low noise by controlling different bias voltages, and the gain flatness of the invention is kept stable and unchanged, which provides convenience for practical operation.
(5) The feedback stages of the second-stage amplifier circuit and the third-stage amplifier circuit are designed by microstrip lines, so that the stability of the circuits is facilitated, the design area is reduced, and the cost is reduced.
Drawings
Fig. 1 is a schematic diagram of a wideband monolithically integrated low noise amplifier circuit according to the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, the wideband monolithic integrated low noise amplifier proposed by the present invention includes five parts: first stage amplifier splitter 100, second stage amplifier splitter 200, third stage amplifier splitter 300, a two-stage interstage matching network splitter 400, and a two-stage interstage matching network splitter 500. The specific circuit structure and connection relationship of each portion are explained as follows.
The first-stage amplifier separation 100 mainly comprises an NMOS transistor M1, a resistor R1, inductors L1, L2, L3 and L4, a capacitor C1, and bias power supplies VGS1 and VDS 1. The connection relationship is radio frequency signal RFinThe signal is input to the gate of M1 through capacitors C1 and L1, the gate of M1 is connected to the anode of VGS1 through L2, the source of M1 is connected to GND2 through L4, the drain of M1 is divided into two paths, one of the two paths is connected to the anode of VDS1 through R1 and L3, the other path is connected to the gate of M2 in the second-stage amplifier splitter 200 through the series circuit of C3 and L9 in the first-stage and second-stage inter-stage matching network 400, the cathode of VGS1 is connected to GND, and the cathode of VDS1 is connected to GND.
The second stage amplifier separation 200 is composed of an NMOS transistor M2, resistors R2 and R3, inductors L5 and L6, a microstrip line TL1, and bias power supplies VGS2 and VDS 2. The grid of M2 is connected to the positive pole of VGS2 through R2, L5, the source of M2 is connected with GND5 through TL1, the drain of M2 is divided into two branches, one branch is connected to the positive pole of VDS2 through R3, L6, the other branch is divided into two branches after passing through C4 in the two-three-stage interstage matching network 500, the first branch is connected with GND7 through L10 in the two-three-stage interstage matching network 500, the second branch is connected to the grid of M3 in the third-stage amplifier separation 300, the negative pole of VGS2 is connected with GND, and the negative pole of VDS2 is connected with GND.
The third stage amplifier separation 300 is composed of an NMOS transistor M3, resistors R4 and R5, inductors L7 and L8, a capacitor C2, a microstrip line TL2, and bias power supplies VGS3 and VDS 3. The connection relationship is as follows: the grid of M3 is connected to the anode of VGS3 through R4 and L7, the source of M3 is connected to GND9 through TL2, the drain of M3 is divided into two paths, one path is connected to the anode of VDS3 through R5 and L8, and the other path outputs radio frequency signal RF through C2outThe negative electrode of VGS3 is connected to GND, and the negative electrode of VDS3 is connected to GND.
In the invention, the single finger grid width of an NMOS (N-channel metal oxide semiconductor) tube M1 is 25 mu M, a single cell has 6 finger grid bars, and the total grid width is 150 mu M; the single finger grid width of the NMOS tube M2 is 40 μ M, the single cell has 2 finger grid bars, and the total grid width is 80 μ M; the single finger grid width of the NMOS tube M3 is 75 μ M, the single cell has 2 finger grid bars, and the total grid width is 150 μ M.
The resistance value of R5 is 50 omega, and the output resistor is matched to 50 omega without additionally configuring a matching circuit.
The voltages of the bias power supplies VGS1, VGS2 and VGS3 are the same and are 0V, and the voltages of the bias power supplies VDS1, VDS2 and VDS3 are the same and are 4V. I.e. actual operation only requires two voltage inputs.
The operating principle of the first stage amplifier splitter 100 is: the input signal flows to the gate of M1 through C1, L1, wherein C1 plays a role of blocking direct current, and C1 and L1 jointly realize the matching of input impedance to 50 omega. From the cascade noise figure equation:
Figure BDA0001187456530000051
where F is the total noise figure of the cascade system, F1Is the noise figure of the first stage amplifier, F2Is the noise figure of the second stage amplifier, F3Is the noise figure of the third stage amplifier, G1Is the gain of the first stage amplifier, G2The gain of the second stage amplifier.
It is known that the first stage amplifier has the greatest effect on the noise of the system and therefore needs to produce the least noise. L1 is single inductance noise matching, and the circuit realizes low noise amplification through L1. Bias supplies VGS1 and VDS1 provide gate and drain voltages for M1, VGS1 is connected to the gate of M1 through L2; VDS1 is connected to the drain of M1 through L3, R1, where R1 acts to improve circuit stability and adjust gain flatness; the L2 and the L3 are used for conducting direct current and alternating current, and protecting a bias power supply. The source of M1 is connected to L4 to improve the stability of the circuit. Both L2 and L4 are large value inductors that limit the bias current into the transistor gate to protect the transistor.
The working principle of the second stage amplifier split 200 is: after M1 converts the input signal into current, the rf signal flows through a secondary interstage matching separation 400 to the gate of M2. Bias power supplies VGS2 and VDS2 provide grid voltage and drain voltage for M2, VGS2 is connected to the grid of M2 through L5 and R2, wherein R2 plays a role in voltage division, reduces M2 grid current Igs2 and protects the grid; VDS2 is connected to the drain of M2 through L6, R3, where R3 acts to improve circuit stability and adjust gain flatness; the L5 and the L6 are used for conducting direct current and alternating current, and protecting a bias power supply. The source of M2 is connected to TL1 to improve the stability of the circuit.
The working principle of the third stage amplifier split 300 is: the output signal of M2 flows through the two-stage interstage matching separation 500 to the gate of M3. Bias power supplies VGS3 and VDS3 provide grid voltage and drain voltage for M3, VGS3 is connected to the grid of M3 through L7 and R4, wherein R4 plays a role in voltage division, reduces M3 grid current Igs3 and protects the grid; VDS3 is connected to the drain of M3 through L8, R5, where R8 acts to improve circuit stability and adjust gain flatness; the L7 and the L8 are used for conducting direct current and alternating current, and protecting a bias power supply. The source of M3 is connected with TL2, the stability of the circuit is improved, the radio frequency signal is output from the drain of M3 through C2, and C2 plays the roles of DC blocking and impedance matching.
A secondary interstage matching 400 is a conjugate matching of the output impedance of the first stage and the input impedance of the second stage, completing the gain matching, and the matching frequency point is 13 GHz. The second-stage interstage matching 500 is conjugate matching of the second-stage output impedance and the third-stage input impedance, gain matching is completed, and the matching frequency point is 14 GHz. The matching frequency points of the last two stages of stages are all higher frequencies, and high-frequency gain can be complemented. By adjusting the capacitance and inductance of the two-stage and two-stage interstage matching 400 and 500, the gain flatness over the entire bandwidth can be adjusted.
The value ranges of L4, TL1 and TL2 are 0.5-1 nH, the values of capacitors C3 and C4 are both smaller than 5pF, and the values of inductors L9 and L10 are both smaller than 10 nH. In the range, the bandwidth of the circuit can be 9GHz, the highest frequency can reach 14GHz, the noise is lower than 1.8dB, the gain is not lower than 19dB, and the gain flatness is only +/-1 dB by adjusting the values of the capacitor, the resistor and the inductor.
Meanwhile, the stability of the circuit meets the requirement that K & gt 1 when the test temperature is minus 55 ℃, 25 ℃ and 85 ℃ respectively.
The invention adopts noise matching to realize low noise; a three-stage amplifier circuit structure is adopted to obtain high gain, and interstage matching is carried out to ensure the gain flatness; the power consumption value of the whole circuit is reduced by adopting proper bias voltage; the selection of the gate width value and the exponent of each stage of transistor ensures the gain and the noise of the single-stage circuit. The circuit has the advantages of low noise, high gain, wide bandwidth and the like.
Those skilled in the art will appreciate that the details of the invention not described in detail in the specification are within the skill of those skilled in the art.

Claims (4)

1. A wideband monolithically integrated low noise amplifier, comprising: the amplifier comprises a first-stage amplifier (100), a second-stage amplifier (200), a third-stage amplifier (300), a two-stage interstage matching network (400) and a two-stage three-stage interstage matching network (500);
the first-stage amplifier (100) comprises an NMOS transistor M1, a resistor R1, an inductor L1, an inductor L2, an inductor L3, an inductor L4, a capacitor C1, a bias power supply VGS1 and a bias power supply VDS 1; the second-stage amplifier (200) comprises an NMOS transistor M2, a resistor R2, a resistor R3, an inductor L5, an inductor L6, a microstrip line TL1, a bias power supply VGS2 and a bias power supply VDS 2; the third-stage amplifier (300) comprises an NMOS transistor M3, a resistor R4, a resistor R5, an inductor L7, an inductor L8, a capacitor C2, a microstrip line TL2, a bias power supply VGS3 and a bias power supply VDS 3; the primary-secondary interstage matching network (400) comprises a capacitor C3 and an inductor L9; the two-stage interstage matching network (500) comprises a capacitor C4 and an inductor L10;
radio frequency signal RFinThe voltage is input to the grid of an NMOS tube M1 through a series circuit consisting of a capacitor C1 and an inductor L1, the grid of the NMOS tube M1 is connected to the anode of a bias power supply VGS1 through an inductor L2, the source of the NMOS tube M1 is grounded through an inductor L4, the drain of the NMOS tube M1 is divided into two paths, one path is connected to the anode of a bias power supply VDS1 through a series circuit consisting of a resistor R1 and the inductor L3, the other path is connected to the grid of the NMOS tube M2 in a second-stage amplifier (200) through a series circuit consisting of the capacitor C3 and the inductor L9, the cathode of the bias power supply VGS1 and the cathode of the VDS1 are grounded;
the gate of the NMOS transistor M2 is connected to the positive electrode of the bias power supply VGS2 through the series circuit of the resistor R2 and the inductor L5, the source of the NMOS transistor M2 is grounded through the microstrip line TL1, and the drain of the NMOS transistor M2 is divided into two paths, wherein one path is connected to the positive electrode of the bias power supply VDS2 through the series circuit of the resistor R3 and the inductor L6, the other path is connected to one end of the capacitor C4, the other end of the capacitor C4 is connected to one end of the inductor L10 and the gate of the NMOS transistor M3 in the third-stage amplifier (300), the other end of the inductor L10 is grounded, the negative electrode of the bias power supply VGS2 and the negative electrode of the VDS2 are grounded;
the gate of the NMOS transistor M3 is connected to the positive electrode of the bias power supply VGS3 through the series circuit of the resistor R4 and the inductor L7, the source of the NMOS transistor M3 is grounded through the microstrip line TL2, the drain of the NMOS transistor M3 is divided into two paths, one of the two paths is connected to the positive electrode of the bias power supply VDS3 through the series circuit of the resistor R5 and the inductor L8, the other path is connected to one end of the capacitor C2, and the other end of the capacitor C2 outputs a radio frequency signal RF signaloutThe cathodes of the bias supplies VGS3 and VDS3 are grounded.
2. A wideband monolithically integrated low noise amplifier according to claim 1, characterized in that: the single finger grid width of the NMOS tube M1 is 25 μ M, the single cell has 6 finger grid bars, and the total grid width is 150 μ M; the single finger grid width of the NMOS tube M2 is 40 μ M, the single cell has 2 finger grid bars, and the total grid width is 80 μ M; the single finger grid width of the NMOS tube M3 is 75 μ M, the single cell has 2 finger grid bars, and the total grid width is 150 μ M.
3. A wideband monolithically integrated low noise amplifier according to claim 1, characterized in that: the resistance value of the R5 is 50 omega, the output resistor is matched to 50 omega, and no matching circuit is required to be additionally configured.
4. A wideband monolithically integrated low noise amplifier according to claim 1, characterized in that: the bias power sources VGS1, VGS2 and VGS3 have the same voltage, and the bias power sources VDS1, VDS2 and VDS3 have the same voltage.
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CN107493079A (en) * 2017-08-07 2017-12-19 电子科技大学 Ku wave band automatic biasing low-noise amplifiers
CN107592081A (en) * 2017-09-08 2018-01-16 中国科学技术大学 A kind of ultra wide band monolithic microwave integrated low-noise amplifier
CN108055009B (en) * 2018-01-31 2024-01-26 成都泰格微电子研究所有限责任公司 Broadband MMIC amplifier
CN209375586U (en) * 2018-11-30 2019-09-10 南京米乐为微电子科技有限公司 A kind of ultra-low noise amplifier
CN109714011A (en) * 2018-12-20 2019-05-03 佛山臻智微芯科技有限公司 A kind of GaAs radio-frequency power amplifier applied in the 5th third-generation mobile communication 28GHz

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