JP2015130558A - amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplifier having improved third-order intermodulation distortion characteristics and capable of achieving downsizing and low power consumption.SOLUTION: An amplifier 10 comprises: a first FET (M1) including a first back gate end B1; a second FET (M2) including a second back gate end B2; a third FET (M3) including a third back gate end B3; a first power terminal PT1 for applying voltage to the first back gate end B1; a second power terminal PT2 for applying voltage to the second back gate end B2; and a third power terminal PT3 for applying voltage to the third back gate end B3. The first to third power terminals (PT1 to PT3) are configured to allow different voltages to be set in the first to third power terminals (PT1 to PT3).

Description

  The present invention relates to an amplifier, and more particularly to a linearization technique for a high-frequency amplifier.

  The high frequency amplifier is used for wireless communication, for example. The high frequency amplifier amplifies a high frequency signal, for example, a modulation signal such as a reception signal or a transmission signal.

  One of the characteristics of a high-frequency amplifier is a linear characteristic. As an index indicating the linear characteristic of an amplifier that amplifies a modulation signal, for example, a third order intermodulation distortion characteristic (IMD3) and a third order input intercept point (IIP3) are known.

  Japanese Patent Laying-Open No. 2006-180492 discloses an amplifier using a multi-gate transistor (MGTR). This amplifier is configured so that the characteristics of a main FET (Field Effect Transistor) and an auxiliary FET are different in order to improve linearity and reduce third-order intermodulation distortion.

JP 2006-180492 A

  In order to configure the amplifier so that the characteristics of the FETs of the main FET and the auxiliary FET are different, Japanese Patent Laid-Open No. 2006-180492 discloses a gate bias voltage (DC voltage applied to the gate terminal) supplied to each FET of the amplifier. ) Are set to different values, or the size of each FET is proposed to be changed.

  When the gate bias voltage of each FET is set to a different value, a DC cut capacitor for separating the gate ends of each FET in a DC manner is provided at the gate end of each FET. However, if each FET includes a DC cut capacitor, the size of the amplifier (for example, the size of the semiconductor chip) increases, and it becomes difficult to reduce the size of the amplifier.

  On the other hand, when changing the FET size, if the power consumption of the FET is not adjusted well, the current consumption increases depending on the FET size. This makes it difficult to reduce the power consumption of the amplifier.

  An object of the present invention is to provide an amplifier that achieves downsizing and low power consumption and has improved third-order intermodulation distortion characteristics.

  In one aspect, the present invention is an amplifier that includes a first FET including a first back gate end, a second FET including a second back gate end, a third FET including a third back gate end, and a first back gate. A first power supply terminal for applying a voltage to the terminal, a second power supply terminal for applying a voltage to the second backgate terminal, and a third power supply terminal for applying a voltage to the third backgate terminal. Prepare. The gate ends of the first to third FETs are commonly connected, the source ends of the first to third FETs are commonly connected, and the drain ends of the first to third FETs are commonly connected. The first to third power supply terminals are configured such that different voltages can be set to the first to third power supply terminals.

  The amplifier having the above configuration includes first to third power supply terminals for applying a voltage to the first to third back gate ends. Further, the first to third power supply terminals are configured to be set to different voltages. Therefore, the amplifier having the above configuration can supply different voltages to the first to third back gate terminals by supplying different voltages to the first to third power supply terminals.

  By supplying an appropriate voltage to each of the first to third back gate ends, the third-order intermodulation distortion characteristic of the amplifier can be improved.

  The amplifiers configured as described above have gate ends connected in common. That is, a DC cut capacitor for separating each gate end in a DC manner is unnecessary.

  According to the present invention, it is possible to provide an amplifier that achieves downsizing and low power consumption and improved third-order intermodulation distortion characteristics.

FIG. 3 is a diagram for explaining a schematic configuration of an amplifier according to the first embodiment. It is a graph which shows the 3rd order intermodulation distortion characteristic (IMD) of an amplifier. It is a graph which shows the gain characteristic of an amplifier. It is a figure which shows typically the cross-section of FET. It is a figure for demonstrating the structure for supplying a different voltage to the back gate end. It is a figure for demonstrating the combination of an amplifier and a switch. It is a figure for demonstrating the communication apparatus using a duplexer. It is a figure for demonstrating the modification of an amplifier. It is a figure for demonstrating an example of a structure of a negative voltage generation circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a diagram for explaining a schematic configuration of an amplifier 10 according to the first embodiment.

  The amplifier 10 includes a transistor M1 that is a first FET, a transistor M2 that is a second FET, and a transistor M3 that is a third FET. Transistor M1, transistor M2, and transistor M3 constitute a plurality of amplifying transistors. That is, the amplifier 10 is an amplifier including a plurality of amplification transistors.

  When the amplifier includes a plurality of amplification stages, the plurality of amplification transistors (transistors M1 to M3) may be used in any amplification stage of the input stage, the interstage, and the output stage.

  The transistors M1 to M3 are, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

  The gate terminal G1 of the transistor M1, the gate terminal G2 of the transistor M2, and the gate terminal G3 of the transistor M3 are connected in common. The source terminal S1 of the transistor M1, the source terminal S2 of the transistor M2, and the source terminal S3 of the transistor M3 are connected in common. The drain terminal D1 of the transistor M1, the drain terminal D2 of the transistor M2, and the drain terminal D3 of the transistor M3 are connected in common. The term “commonly connected” means that a common DC voltage is applied by being electrically connected, for example, DC.

  Each of transistor M1, transistor M2, and transistor M3 includes a back gate end. Specifically, the transistor M1 includes a back gate end (first back gate end) B1. The transistor M2 includes a back gate end (second back gate end) B2. The transistor M3 includes a back gate end (third back gate end) B3. The “back gate” will be described later with reference to FIG.

  The amplifier 10 further includes a power supply terminal PT1, a power supply terminal PT2, and a power supply terminal PT3. The power supply terminal PT1 is a first power supply terminal for applying a voltage to the back gate terminal B1. The power supply terminal PT2 is a second power supply terminal for applying a voltage to the back gate terminal B2. The power supply terminal PT3 is a third power supply terminal for applying a voltage to the back gate terminal B3.

  The power supply terminals PT1 to PT3 are electrically separated from each other by, for example, separate wiring in the semiconductor chip. As a result, the power supply terminal PT1, the power supply terminal PT2, and the power supply terminal PT3 are configured such that different voltages are set. For example, the power supply terminal PT1 is set to the voltage Vb1, the power supply terminal PT2 is set to the voltage Vb2, and the power supply terminal PT3 is set to the voltage Vb3. Even if the power supply terminals PT1 to PT3 are not electrically separated well, it is only necessary that different voltages can be set.

  The source ends S1, S2 and S3 are connected in common and connected to the ground (GND) via the inductance LS. That is, the source terminals S1 to S3 are connected to the ground in a DC manner. The inductance LS provides, for example, an impedance for properly operating the transistors M1 to M3.

  The amplifier 10 further includes a power supply terminal GT1 for supplying a gate bias voltage to the gate terminals G1, G2 and G3 connected in common. The power supply terminal GT1 has a voltage Vbo, for example.

  A resistor Rgb is provided between the gate terminals G1 to G3 and the power supply terminal GT1. By appropriately selecting the resistor Rgb, an appropriate gate bias voltage is supplied to the gate terminals G1, G2, and G3. With the appropriate gate bias voltage, transistors M1, M2 and M3 are operated in the desired bias state.

  Amplifier 10 further includes a transistor MC. The transistor MC is an FET (cascode connection FET) that is cascode-connected to the entirety of a plurality of amplification transistors (transistor M1, transistor M2, and transistor M3). Similarly to the transistors M1 to M3, the transistor MC is formed of, for example, a MOSFET.

  The transistor MC has a source terminal SC for supplying voltage and current to the source terminals S1 to S3. The source end SC is connected to the source ends S1 to S3.

  A voltage is supplied from the power supply terminal GT2 to the gate terminal GC of the transistor MC. Power supply terminal GT2 has voltage VCAS, for example.

  The drain terminal DC of the transistor MC is connected to the power supply VDD via the inductance LD. An appropriate voltage is supplied from the power supply terminal GT2 to the gate terminal GC. An appropriate voltage and current are supplied from the power supply VDD to the transistor MC, and further, an appropriate voltage and current are supplied from the transistor M1 to the transistor M3. Therefore, the transistor MC and the transistors M1 to M3 function as an amplifier. The inductance LD separates the drain end DC and the power supply VDD in a high frequency (RF) manner.

  The amplifier 10 further includes an input terminal 11 and an output terminal 12. The input terminal 11 is a terminal for receiving a signal for the amplifier 10 to amplify. A high frequency signal (RF signal) is input to the input terminal 11. The output terminal 12 is a terminal for outputting the signal amplified by the amplifier 10. An RF signal is output from the output terminal 12. That is, the amplifier 10 is a high frequency power amplifier that amplifies the RF signal.

  A capacitor Cin is provided between the input terminal 11 and the gate terminals G1 to G3 of the transistors M1 to M3. A capacitor Cout is provided between the output terminal 12 and the drain terminal DC of the transistor MC. Cin and Cout are DC cut capacitors. Cin and Cout may be used in the matching circuit.

  With the above configuration, in the amplifier 10, the high-frequency power (RF signal) received by the input terminal 11 is commonly input to the gate terminals G1 to G3 of the transistors M1 to M3. The amplifier 10 amplifies the high frequency power and outputs the amplified high frequency power from the drain terminal DC of the transistor MC. That is, the amplifier 10 is an amplifier that uses a plurality of amplifying transistors (transistors M1 to M3) and is a cascode-connected amplifier that uses a transistor MC.

  In the amplifier 10 according to the first embodiment, the power supply terminals PT1 to PT3 for applying a voltage to the back gate ends B1 to B3 of the transistors M1 to M3 are configured to be able to set different voltages. Since the power supply terminals PT1 to PT3 have different voltages, different voltages are supplied to the back gate terminals B1 to B3, and the characteristics of the amplifier 10 are controlled.

  For example, when the amplifier 10 is used in a communication device that performs wireless communication, the amplifier 10 is used for amplification of a modulated signal (modulated wave). For an amplifier that amplifies a modulation signal, high linear characteristics are often required. For example, a third-order intermodulation distortion characteristic (IMD3: Third Order Intermodulation Distortion) and a third-order input intercept point (IIP3) are known as indexes indicating linear characteristics.

  As a result of the simulation, it has been confirmed that, in the amplifier 10 according to the first embodiment, the linear characteristics of the amplifier 10 are improved when the back gate terminals B1 to B3 have appropriate voltages.

  In order to improve the linear characteristic of the amplifier 10, the voltages at the back gate ends B1 to B3 are, in particular, a positive voltage with respect to the ground, a voltage equal to the ground, and a negative voltage with respect to the ground. Preferably, the voltage is as follows.

  FIGS. 2 and 3 are diagrams for explaining simulation results showing improvement in linear characteristics of an amplifier having the configuration of the amplifier 10 shown in FIG. 1 (hereinafter, this amplifier may also be simply referred to as “amplifier 10”). is there.

  FIG. 2 is a graph showing the third-order intermodulation distortion characteristic (IMD3) of the amplifier. The horizontal axis represents the output power (dBm) of the amplifier, and the vertical axis represents IMD3 (dBc).

  FIG. 2 shows two types of third-order intermodulation distortion characteristics of line A and line B. Line A is the characteristic of the first embodiment, and line B is a comparative example.

  Line A represents the third-order intermodulation distortion characteristics of the amplifier 10 when the back gate terminals B1 to B3 are set to different voltages in the amplifier 10 shown in FIG. Specifically, the back gate end B1 is set to the same voltage as the ground, the back gate end B2 is set to a positive voltage with respect to the ground, and the back gate end B3 is set to a negative voltage with respect to the ground.

  Line B shows the third-order intermodulation distortion characteristic of the amplifier 10 when the back gate terminals B1 to B3 are all set to the same voltage as the ground in the amplifier 10 shown in FIG.

  Note that the other conditions necessary for the simulation, the gate bias voltage to each transistor, the frequency of the power (signal) to be amplified, and the like were the same for the lines A and B. The frequency was selected from the range of about several hundred MHz to several GHz.

  As shown in FIG. 2, it can be seen that the IMD 3 is improved in the first embodiment (line A) than in the comparative example (line B). The amount of improvement varies depending on the output power of the amplifier, but an improvement of IMD3 of 10 dB or more was confirmed in a relatively wide output power range.

  The reason why the linear characteristic of the amplifier is improved in this way is explained as follows. One of the parameters indicating the characteristics of an FET such as the transistor M1 shown in FIG. 1 is a mutual conductance gm. Regarding the third-order intermodulation distortion (IMD3) characteristic, the amount of change in the mutual conductance gm with respect to the level of the voltage (Vgs) between the input of the transistor M1, here the gate G1 and the source S1, influences. Specifically, if the magnitude of gm ″ obtained by second-order differentiation of mutual conductance gm by Vgs with respect to Vgs (hereinafter referred to as “gm ″ −Vgs characteristic”) is constant, the third-order intermodulation distortion characteristic is improved. On the contrary, if the gm ″ −Vgs characteristic is not constant, the third-order intermodulation distortion characteristic is deteriorated.

  In the transistor M1, there are a Vgs range where the gm ″ -Vgs characteristic is substantially constant and a Vgs range where the gm ″ -Vgs characteristic is not constant (the change is large). For example, when a voltage is applied to the back gate B1 of the transistor M1, the range of Vgs in which the gm ″ -Vgs characteristic becomes constant (or approaches constant) shifts. This shift mode can be controlled by the voltage applied to the back gate B1. The same applies to the transistors M2 and M3.

  According to the first embodiment, different voltages are applied to the back gates B1 to B3 of the transistors M1 to M3. Therefore, the gm ″ -Vgs characteristics of the transistors M1 to M3 are individually shifted. If an appropriate voltage is applied to the back gates B1 to B3, the gm ″ -Vgs characteristics of the transistors M1 to M3 cancel each other, and the Vgs range in which the gm ″ -Vgs characteristics are constant can be expanded. As a result, the plurality of amplifying transistors composed of the transistors M1 to M3 have good gm ″ -Vgs characteristics as a whole, that is, gm ″ has a flat characteristic with respect to Vgs, and good third-order intermodulation. Distortion is obtained.

  FIG. 3 is a graph showing gain characteristics of the amplifier. The horizontal axis indicates the output power (dBm) of the amplifier, and the vertical axis indicates the gain (dB).

  As shown in FIG. 3, the gain of the first embodiment (line A) is slightly lower than that of the comparative example (line B), but the amount of decrease is about 0.2 dB at most, which is not a problem. It can be said that it is a level.

  That is, according to the simulation results shown in FIGS. 2 and 3, in the first embodiment, the linear characteristic of the amplifier, that is, the IMD 3 is improved. Further, the basic characteristics (for example, gain characteristics) of other amplifiers are hardly impaired.

  Referring to FIG. 1 again, in the amplifier 10 according to the first embodiment, the gate ends of the transistors M1 to M3 constituting the plurality of amplifying transistors are connected in common. Therefore, for example, a DC cut capacitor for separating each gate end in a DC manner is unnecessary. The characteristics of the amplifier 10 can be controlled by applying a voltage from the back gate terminal B1 to B3. This control does not depend on the size (cell size) of the transistors M1 to M3. Therefore, it is possible to optimize the sizes (cell size and the like) of the transistors M1 to M3 so that current consumption is reduced.

  Therefore, according to the amplifier 10 according to the first embodiment, it is possible to provide an amplifier that achieves miniaturization and low power consumption and improved linear characteristics, for example, third-order intermodulation distortion characteristics.

  Amplifiers such as amplifier 10 are used in a variety of applications. As an example, the amplifier is used to amplify a signal received from a satellite in GPS (Global Positioning System). The amplifier according to each embodiment described later is also used for amplification of a signal in a wireless local area network (WLAN) and a signal in frequency division multiple access (FDMA).

  Here, the back gate ends (B1 to B3) of the transistors M1 to M3 shown in FIG. 1 will be briefly described. In summary, the back gate end is the end of the back gate that forms the body of the FET.

FIG. 4 is a diagram schematically showing a cross-sectional structure of the FET according to the first embodiment.
As shown in FIG. 4, the FET 70 includes a body 71, a source 72, a drain 73, a gate 74, and an insulating film 75.

As an example, the body 71 is formed of a P-type semiconductor substrate. The source 72 and the drain 73 are formed of an N ⁺ type semiconductor. The gate 74 is a metal electrode. Insulating film 75 is, for example, an oxide film, and insulates gate 74 from body 71, source 72, and drain 73.

  The body 71, the source 72, the drain 73, and the gate 74 are electrically accessible. Specifically, the body 71 has a back gate end B that can supply a voltage to the body 71. In order to apply a voltage to the body 71, a voltage is supplied to the back gate terminal B. Similarly, the source 72 has a source end S, the drain 73 has a drain end D, and the gate 74 has a gate end G.

  Each of the back gate terminal B, the gate terminal G, the source terminal S, and the drain terminal D shown in FIG. 4 is respectively connected to, for example, the back gate terminal B1, the gate terminal G1, the source terminal S1, and the drain terminal D1 of the transistor M1 shown in FIG. It may be understood that it corresponds.

  Based on the configuration of the FET 70 described above, the voltage applied to the back gate terminal B1 will be described. For convenience of explanation, it is assumed that the source end S is connected to the ground. That is, the source terminal S has the same voltage (potential) as the ground.

  As shown in FIG. 4, a PN junction is formed between the body 71 and the source 72. Therefore, a voltage can be applied to the back gate terminal B in a range in which an undesired current (leakage current) does not flow from the body 71 toward the source 72. For example, if the FET 70 uses a silicon material, the voltage at the back gate end B can be set within a range not exceeding about 0.7 V which is the threshold voltage of the forward bias of the PN junction (diode). it can. In addition, the voltage at the back gate end B can be set within a range that does not fall below the breakdown voltage of the reverse bias of the PN junction (of the diode).

  That is, the voltage applied to the back gate terminal B (Vb1 to Vb3 in FIG. 1) is preferably higher than the breakdown voltage (negative value) and lower than about 0.7V.

FIG. 4 shows a case where the body 71 is formed of a P-type semiconductor substrate as an example. However, the body 71 may be formed of an N-type semiconductor substrate instead of a P-type semiconductor substrate. When the body 71 is formed of an N-type semiconductor, the source 71 and the drain 73 are formed of a P ⁺ type semiconductor semiconductor. As a result, a PN junction is formed between the source 72 and the body 71. Therefore, it is possible to set the voltage at the back gate end in consideration of the forward bias threshold voltage (diode) of the PN junction and the reverse bias breakdown voltage.

  As described above, in the amplifier 10 shown in FIG. 1, different voltages are supplied to the back gate terminals B1 to B3. This will be described next with reference to FIG.

  FIG. 5 is a diagram for explaining a configuration for supplying different voltages to the back gate ends B1 to B3 of the transistors M1 to M3.

  Compared with the amplifier 10 shown in FIG. 1, the amplifier 10 </ b> A shown in FIG. 5 includes a positive voltage generation circuit 13 and a negative voltage generation circuit 14. The amplifier 10A further includes an inductance Lin.

  The positive voltage generation circuit 13 is configured to be able to generate a positive voltage with reference to ground (GND). The negative voltage generation circuit 14 is configured to be able to generate a negative voltage with respect to the ground. As the positive voltage generation circuit 13 and the negative voltage generation circuit 14, various circuits to which a known technique is applied can be used. An example of the configuration of the negative voltage generation circuit 14 will be described later with reference to FIG.

  The inductance Lin forms an input matching circuit of the amplifier 10A together with the capacitance Cin as necessary.

  In FIG. 5, the power supply terminal PT1 is connected to the ground. Thereby, the power supply terminal PT1 has the same voltage as the ground. The power supply terminal PT2 is connected to the positive voltage generation circuit 13. Thereby, the power supply terminal PT2 has a positive voltage with respect to the ground. The power supply terminal PT3 is connected to the negative voltage generation circuit 14. As a result, the power supply terminal PT3 has a negative voltage with respect to the ground.

  An amplifier 10A illustrated in FIG. 5 includes a positive voltage generation circuit 13 and a negative voltage generation circuit 14. This eliminates the need to provide a negative power source outside the amplifier 10A when the amplifier 10A is used.

  Although not shown in FIG. 5, a resistor may be inserted between the positive voltage generation circuit 13 and the power supply terminal PT2. As a result, the voltage supplied to the back gate terminal B2 is stabilized. Further, an inductance may be inserted between the positive voltage generation circuit 13 and the power supply terminal PT2. As a result, the back gate terminal B2 and the power supply terminal PT2 are separated in a high frequency manner, and the voltage supplied to the back gate terminal B2 is stabilized. Similarly, a resistor and / or an inductance may be inserted between the negative voltage generation circuit 14 and the power supply terminal PT3.

[Embodiment 2]
As described above, the amplifier 10 shown in FIG. 1 and the amplifier 10A shown in FIG. 5 are used in a communication apparatus. In that case, the amplifier is used in combination with a switch, for example.

FIG. 6 is a diagram for explaining a combination of an amplifier and a switch.
Referring to FIG. 6, communication apparatus 100 includes an amplifier 10 </ b> A, a switch 20, and a power amplifier (PA) 30.

  FIG. 6 shows a switch 20 which is an SPDT (Single Pole Double Throw) switch as an example. Switch 20 includes a terminal 21, a terminal 22 and a terminal 23.

  Terminal 21 is connected to an antenna (not shown), for example. The antenna transmits and receives radio frequency (RF) electromagnetic waves. Therefore, high frequency power (transmitted wave) is output from the terminal 21, and high frequency power (received wave) is input to the terminal 21. The transmitted wave and the received wave are modulated waves. Terminal 22 is connected to terminal 11 of amplifier 10A. Terminal 23 is connected to the output of power amplifier 30.

  Referring to FIG. 6, switch 20 includes transistors T1 to T8, resistors R1 to R16, and control terminals CT1 and CT2.

  The transistors T1 to T4 switch the connection state between the terminal 21 and the terminal 22. By arranging the plurality of transistors T1 to T4 between the terminal 21 and the terminal 22, the high-frequency signal applied to each transistor is divided, and the breakdown voltage of the switch 20 is improved.

  Each of the resistors R1 to R4 connects the gate ends of the transistors T1 to T4 and the control terminal CT1. Thereby, the voltage (for example, VCNT1) applied to the control terminal CT1 is applied to the gates of the transistors T1 to T4 via the resistors R1 to R4. When a voltage is applied to the gates of the transistors T1 to T4, the transistors T1 to T4 are turned on, and the terminals 21 and 22 are conducted.

  Each of the resistors R5 to R8 connects the drain ends of the transistors T1 to T4 and the source ends of the transistors T1 to T4, respectively. That is, a path that bypasses the drain and source terminals of the transistors T1 to T4 is configured by the resistors R5 to R8. Thereby, for example, when the transistors T1 to T4 are OFF, the high-frequency signal is always divided through the resistors R1 to R4, so that the breakdown voltage of the switch 20 is improved.

  The transistors T5 to T8 switch the connection state between the terminal 21 and the terminal 23. By arranging the plurality of transistors T5 to T8 between the terminal 21 and the terminal 23, the high-frequency signal applied to each transistor is divided, and the breakdown voltage of the switch 20 is improved.

  Each of the resistors R9 to R12 connects the gate terminals of the transistors T5 to T8 and the control terminal CT2. Thereby, the voltage (for example, VCNT2) applied to the control terminal CT2 is applied to the gates of the transistors T5 to T8 via the resistors R9 to R12. When a voltage is applied to the gates of the transistors T5 to T8, the transistors T1 to T4 are turned on, and the terminals 21 and 23 are conducted.

  Further, the resistors R13 to R16 form a path that bypasses the drain and source terminals of the transistors T5 to T8. Thus, for example, when the transistors T5 to T8 are OFF, the high-frequency signal is always divided through the resistors R13 to R16, so that the breakdown voltage of the switch 20 is improved.

  With the above configuration, the switch 20 can output the received wave received from the terminal 21 from the terminal 22, for example. Further, the switch 20 can output the transmission wave received from the terminal 23 to the terminal 21. The switch 20 is used to switch the transmission operation and the reception operation of the communication device 100, for example, in terms of time.

  The input terminal 11 of the amplifier 10A is connected to the terminal 22 of the switch 20. As a result, the received signal received by the antenna is output to the input terminal 11 of the amplifier 10 </ b> A via the terminals 21 and 22 of the switch 20. The amplifier 10A amplifies the received signal and outputs it to the output terminal 12. Generally, in a communication apparatus, a low noise amplifier (LNA) is used as an amplifier that amplifies received high frequency power. That is, in the communication device 100, the amplifier 10A is used as a low noise amplifier.

  The output of the power amplifier 30 is connected to the terminal 23 of the switch 20. As a result, the transmission signal amplified by the power amplifier 30 is output via the terminals 23 and 21 of the switch 20. The power amplifier 30 may have the same configuration as the amplifier 10A. That is, in the communication device 100, the amplifier 10A may be used as a power amplifier.

  The communication device 100 illustrated in FIG. 6 switches between transmission and reception by the switch 20. Such a communication apparatus is suitably used for communication using a time division duplex (TDD) system, for example. For example, there is a wireless LAN that uses the TDD system. That is, the amplifier 10A is suitably used for a communication device for a wireless LAN.

[Embodiment 3]
FIG. 6 shows a communication apparatus 100 of the type in which transmission and reception are switched, for example, in time by the switch 20. On the other hand, some communication devices are of a type in which transmission and reception are performed simultaneously. In that case, in the communication device, for example, a duplexer (DUP) is used instead of the switch.

FIG. 7 is a diagram for explaining a communication device 100A using a duplexer.
Referring to FIG. 7, communication device 100A includes a duplexer 20A, an amplifier 10A, a power amplifier 30, and an antenna 200.

  The duplexer 20A separates a transmission frequency band signal (transmission signal) and a reception frequency band signal (reception signal). Specifically, the duplexer 20A passes the received signal between the antenna 200 and the amplifier 10A. The duplexer 20 </ b> A allows transmission signals to pass between the power amplifier 30 and the antenna 200.

  The communication device 100A includes a mixer 40, a voltage controlled variable gain amplifier (VGA) 41, a filter 42, an analog-to-digital converter (ADC) 43, and digital signal processing. And a processor (DSP: Digital Signal Processor) 60.

  The received signal is amplified by the amplifier 10A. The amplified received signal is frequency-converted (for example, down-converted) by the mixer 40. The down-converted received signal is adjusted to an appropriate signal level by the VGA 41. An unnecessary component is removed from the received signal adjusted to an appropriate signal level by the filter 42. The reception signal from which unnecessary components are removed is converted into a digital signal by the ADC 43. The received signal converted into the digital signal is processed by the DSP 60.

  Communication device 100 </ b> A further includes a mixer 50, a VGA 51, a filter 52, and a DAC 53.

  The digital transmission signal generated by the DSP 60 is converted into an analog signal by a digital-to-analog converter (DAC) 53. Unnecessary components are removed from the transmission signal converted into the analog signal by the filter 52. The transmission signal from which unnecessary components have been removed is adjusted to an appropriate signal level by the VGA 51. The transmission signal adjusted to an appropriate signal level is frequency-converted (eg, up-converted) by the mixer 50. The upconverted transmission signal is input to the power amplifier 30.

  Communication device 100 </ b> A further includes transmitter 45. The transmitter 45 gives a signal having a predetermined frequency to the mixer 40 and the mixer 50.

  In the communication device 100A shown in FIG. 7, the transmission signal and the reception signal are separated by the duplexer 20A. Such a communication apparatus is preferably used for communication using, for example, a frequency division multiple access (FDMA) system. As a device using the FDMA method, for example, there is a mobile communication terminal using a CDMA (Code Division Multiple Access) method. That is, the amplifier 10A is preferably used for a mobile communication terminal using the CDMA method.

[Modification]
Referring to FIG. 1 again, in the amplifier 10 shown in FIG. 1, a plurality of amplifying transistors are constituted by three transistors M1 to M3. However, the number of transistors constituting the plurality of amplifying transistors is not limited to three. That is, the number of transistors constituting the plurality of amplifying transistors can take various values.

FIG. 8 is a diagram for explaining an amplifier 10D as a modification.
As shown in FIG. 8, the amplifier 10D includes four or more transistors as transistors constituting a plurality of amplification transistors. Specifically, in the amplifier 10D, a plurality of amplifying transistors are configured by n transistors M1 to Mn.

  The gate terminal Gn of the transistor Mn is commonly connected to the gate terminals (G1 to G3, etc.) of other transistors (M1 to M3, etc.). The source end Sn of the transistor Mn is connected in common with the source ends (S1 to S3, etc.) of other transistors (M1 to M3, etc.). The drain end Dn of the transistor Mn is connected in common with the drain ends (D1 to D3) of the other transistors (M1 to M3).

  The transistor Mn includes a back gate end Bn. The amplifier 10D includes a power supply terminal PTn for applying a voltage to the back gate terminal Bn. The power supply terminals PT1 to PTn are configured such that different voltages are set. For example, power supply terminal PTn has voltage Vbn.

  In the amplifier 10D, by appropriately setting the voltage from the power supply terminals PT1 to PTn, the characteristics of the amplifier 10D, for example, the linear characteristics are improved.

  Compared with the amplifier 10 shown in FIG. 1, the amplifier 10D shown in FIG. 8 has a larger number of transistors constituting a plurality of amplifying transistors. Therefore, in the amplifier 10D, many combinations are possible for the voltages applied to the back gate ends B1 to Bn of the transistors M1 to Mn. As a result, the characteristics of the amplifier 10D can be finely controlled.

[Configuration of negative voltage generator]
FIG. 9 is a diagram for explaining an example of the configuration of a negative voltage generation circuit such as the negative voltage generation circuit 14 shown in FIG.

  Referring to FIG. 9, negative voltage generation circuit 14 </ b> A includes an AC power supply 300, a NOT gate (inverter) 301, capacitors 302 and 305, transistors 303 and 304, and an output terminal 306.

  The AC power supply 300 generates AC power (for example, a sine wave) based on the ground (GND). AC power generated by the AC power source 300 is input to the inverter 301. The inverter 301 generates rectangular wave power having positive and negative voltages with reference to the ground in accordance with the cycle of the input AC power. The rectangular wave power generated by the inverter 301 is output toward the capacitor 302.

Capacitors 302 and 305 are charged and discharged by receiving power from inverter 301.
The transistors 303 and 304 are FETs. The gate ends and drain ends of the transistors 303 and 304 are electrically short-circuited. That is, the transistors 303 and 304 function as diodes whose forward direction is from the drain end to the gate end.

  While the voltage of the rectangular wave power from the inverter 301 is positive, the voltage applied between the inverter 301 and the source terminal (ie, ground) of the transistor 303 causes the capacitor 302 to be positive on the inverter 301 side. Charged.

  On the other hand, the capacitor 302 is discharged toward the inverter 301 while the voltage of the rectangular wave power from the inverter 301 is negative. At this time, the capacitor 305 is charged via the transistor 304 so that the transistor 304 side becomes negative. Accordingly, a negative voltage Vss is generated at the output terminal 306.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiment but by the scope of the claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

  PT1, PT2, PT3, PTn power supply terminal, 10, 10A, 10D amplifier, 11 input terminal, 12 output terminal, 13 positive voltage generation circuit, 14 negative voltage generation circuit, 20 switch, 20A duplexer, 21, 22, 23 terminal, 30 power amplifier, 40, 50 mixer, 42, 52 filter, 45 transmitter, 71 body, 72 source, 73 drain, 74 gate, 75 insulating film, 100, 100A communication device, 200 antenna, 300 AC power supply, 301, 302 Inverter, B, B1, B2, B3, Bn Back gate end, CT1, CT2 control terminal, Cin, Cout, 302, 305 capacitor, D1, D2, D3, DC, Dn drain end, G1, G2, G3, GC, Gn gate end, LD, LS inductance, M1, M , MC, Mn, T1~T8,303,304 transistors, R1-R16, Rgb resistance, S1, S2, S3, SC, Sn source terminal, VDD power supply.

Claims (5)

An amplifier,
A first FET including a first back gate end;
A second FET including a second back gate end;
A third FET including a third back gate end;
A first power supply terminal for applying a voltage to the first back gate end;
A second power supply terminal for applying a voltage to the second back gate end;
A third power supply terminal for applying a voltage to the third back gate end,
The gate terminals of the first to third FETs are connected in common,
The source terminals of the first to third FETs are connected in common,
The drain ends of the first to third FETs are connected in common,
The first to third power supply terminals are configured to be capable of setting different voltages to the first to third power supply terminals. The source terminals of the first to third FETs are connected to the ground in a DC manner,
2. The amplifier according to claim 1, wherein at least one of the first to third power terminals has a negative voltage with respect to the ground.   The first power terminal has a positive voltage with respect to the ground, the second power terminal has the same voltage as the ground, and the third power terminal has the negative voltage. Amplifier.   The amplifier according to claim 2, further comprising a negative voltage generation circuit for supplying the negative voltage to the at least one power supply terminal among the first to third power supply terminals. The amplifier is
A cascode connection FET that is cascode-connected to the entirety of the first to third FETs;
The cascode connection FET has a source terminal for supplying voltage and current to the drain terminals of the first to third FETs,
High frequency power is commonly input to the gate terminals of the first to third FETs,
The amplifier according to any one of claims 2 to 4, wherein the amplifier amplifies the high-frequency power and outputs the amplified high-frequency power from a drain end of the fourth FET.

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