CN114024512B - Ultra-wideband low noise amplifier of frequency division duplex - Google Patents
Ultra-wideband low noise amplifier of frequency division duplex Download PDFInfo
- Publication number
- CN114024512B CN114024512B CN202111181320.8A CN202111181320A CN114024512B CN 114024512 B CN114024512 B CN 114024512B CN 202111181320 A CN202111181320 A CN 202111181320A CN 114024512 B CN114024512 B CN 114024512B
- Authority
- CN
- China
- Prior art keywords
- capacitor
- frequency
- inductor
- broadband
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000008878 coupling Effects 0.000 claims abstract description 38
- 238000010168 coupling process Methods 0.000 claims abstract description 38
- 238000005859 coupling reaction Methods 0.000 claims abstract description 38
- 239000003990 capacitor Substances 0.000 claims description 152
- 230000003321 amplification Effects 0.000 claims description 84
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 84
- 230000000903 blocking effect Effects 0.000 claims description 37
- 238000003780 insertion Methods 0.000 claims description 11
- 230000037431 insertion Effects 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000004891 communication Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 4
- 238000011160 research Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
- H03F1/48—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
- H03F1/483—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers with field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/36—Indexing scheme relating to amplifiers the amplifier comprising means for increasing the bandwidth
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
Abstract
The invention provides an ultra-wideband low-noise amplifier with frequency division duplex, and belongs to the technical field of radio frequency integrated circuits. The amplifier adopts a coupling line as a frequency division duplexer, and simultaneously outputs input signals through a high-frequency path and a low-frequency path, and simultaneously introduces a multi-stage amplifying stage and a matching network to realize the control of gain fluctuation and the matching of impedance, so that the amplifier can work in two different ultra-wideband frequency bands simultaneously. According to the technical scheme, the low-noise amplifier achieves a noise coefficient smaller than 1.5dB and a gain fluctuation smaller than 3dB in two ultra-wide frequency bands of low frequency bands of 2.5 GHz-5 GHz and high frequency bands of 5 GHz-18 GHz, and the gain fluctuation of a high-frequency output signal and a low-frequency output signal is smaller than 3dB.
Description
Technical Field
The invention belongs to the technical field of radio frequency integrated circuits, and particularly relates to an ultra-wideband low-noise amplifier with frequency division duplexing.
Background
With the development of radio frequency integrated circuits and electronic information industry, the integration level of wireless communication terminals is higher and higher, and the standards of communication technology are also richer. However, in the present wireless communication era, the communication frequency band is crowded, the communication modes coexist, and the receiving architecture for a single frequency band cannot meet daily demands gradually. Therefore, multimode and multiband are one of the main trends of the rf front-end chip. Conventional multimode, multiband rf receivers often employ multiple receive chains to implement multiple wireless communication applications, and the more operating bands such a receiver requires, the more receive chains, thereby increasing the area and cost of the rf receiver.
For this problem, there are currently two conventional approaches to solving it. The first mode is a multiplexing mode, namely, the receiver adopts an ultra-wideband low noise amplifier to replace a plurality of traditional narrowband low noise amplifiers (Hu Jianquan, key technical research on multi-octave ultra-wideband receiver chip.2020, electronic technology university), and for communication signals of different frequency bands, the receiver multiplexes the ultra-wideband low noise amplifier to meet the communication requirement, however, the receiver can only communicate in one frequency band at the same time, and the requirement of multi-frequency band simultaneous communication is difficult to meet; in addition, the noise of the current ultra-wideband low-noise amplifier is also high. Another approach is that the receiver uses a dual-band low noise amplifier, which can communicate in two frequency bands simultaneously (Tang Xu liters, applied to research on reconfigurable radio frequency receiving front-end chips in wideband wireless communication systems.2019, university of eastern south), but the existing dual-band low noise amplifier is often narrowband, the band-pass frequency band is fixed, and it is difficult to support the reception of more than two multi-frequency signals. In summary, both the above solutions have drawbacks, and the wideband low noise amplifier is difficult to communicate with multiple frequency bands at the same time, and the narrowband dual-band low noise amplifier has limited communication frequency bands for satisfying signals, so that the supported communication protocols are limited.
Therefore, how to realize the design of the wideband frequency division duplex low noise amplifier, that is, how to realize the design of a wideband dual-band low noise amplifier, namely, how to realize the simultaneous operation of dual-band signals by one wideband dual-band low noise amplifier, and how to support the frequency bands of a plurality of communication protocols by each frequency band, becomes a research key point.
Disclosure of Invention
In view of the problems existing in the background art, an object of the present invention is to provide an ultra wideband low noise amplifier for frequency division duplexing. The amplifier adopts a coupling line as a frequency division duplexer, and simultaneously outputs input signals through a high-frequency path and a low-frequency path, and simultaneously introduces a multi-stage amplifying stage and a matching network to realize the control of gain fluctuation and the matching of impedance, so that the amplifier can work in two different ultra-wideband frequency bands simultaneously.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
an ultra-wideband low noise amplifier of frequency division duplex comprises a bias network, an input blocking capacitor, a wideband input matching network, a wideband input amplifying stage, a first wideband interstage matching network, a wideband intermediate amplifying stage, a second wideband interstage matching network, a duplexer, a third wideband interstage matching network group, a wideband output amplifying stage group, a wideband output stage matching network group and an output blocking capacitor group which are sequentially connected in series;
the third broadband interstage matching network group consists of a high-frequency interstage matching network and a low-frequency interstage matching network, the broadband output amplification stage group consists of a high-frequency broadband output amplification stage group and a low-frequency broadband output amplification stage, and the broadband output stage matching network group consists of a high-frequency output matching network and a low-frequency output matching network; the high-frequency broadband output amplification stage group is formed by connecting a first high-frequency broadband output amplification stage, a high-frequency broadband output amplification stage interstage matching network and a second high-frequency broadband output amplification stage in series; the output blocking capacitor group consists of a high-frequency output blocking capacitor and a low-frequency output blocking capacitor;
the input blocking capacitor is used for blocking an input signal and outputting the signal; the broadband input matching network is used for matching the signal source impedance with the input impedance of the low-noise amplifier; the broadband input amplification stage is used for amplifying an input signal at the cost of less than 1dB noise figure without considering gain fluctuation of the input amplification stage; the first broadband interstage matching network is used for matching the output impedance of the broadband input amplification stage with the input impedance of the broadband intermediate amplification stage; the broadband intermediate amplification stage is used for further amplifying the signals amplified by the broadband input amplification stage, so that noise caused by the insertion loss of the duplexer and the active circuits of the broadband output amplification stage group is suppressed; the second broadband interstage matching network is used for matching the output impedance of the broadband intermediate amplification stage and the input impedance of the duplexer; the duplexer is used for dividing an input radio frequency signal into a high-frequency signal and a low-frequency signal for output; the third broadband interstage matching network group is used for matching duplex output impedance and broadband output amplification stage group input impedance; the broadband output amplification stage group is used for compensating gain fluctuation brought by the broadband input amplification stage and the broadband intermediate amplification stage; the output blocking capacitor group is used for blocking output signals and outputting the signals; the bias network is used for providing bias voltage for the transistor.
Further, the diplexer is a coupled line-based frequency division diplexer; by providing a bypass-to-ground capacitance at the through-and coupling-or through-and isolation-ends of the coupled line, the port of the coupled line plus the bypass capacitance is equivalent to a short-circuit ground for high frequency signals.
Further, when the direct-pass end and the coupling end of the coupling line are respectively connected to the bypass capacitor, and the port impedances of the input end and the isolation end are matched, the isolation end is a high-frequency signal output port, high-frequency signals can flow out from the isolation end with insertion loss smaller than 1dB, and low-frequency signals can flow out from the direct-pass end with insertion loss smaller than 1 dB; when the direct end and the isolation end of the coupling line are respectively connected into the bypass capacitor, and the input end is matched with the coupling end port, the coupling end is a high-frequency signal output port, high-frequency signals can flow out from the coupling end with insertion loss smaller than 1dB, and low-frequency signals can flow out from the direct end with insertion loss smaller than 1 dB.
Further, the boundary frequency point of the low frequency and the high frequency can be changed by adjusting the capacitance value of the bypass capacitor connected in parallel with the port of the coupling line, and when the capacitance value is increased, the boundary frequency point can move to the high frequency.
Further, the bias network comprises a first bias resistor Rg1, a second bias resistor Rg2, a third bias resistor Rg3, a fourth bias resistor Rg4, a fifth bias resistor Rg5 and a sixth bias resistor Rg6; the input blocking capacitor is a first capacitor C1; the broadband input matching network comprises a first inductor L1, a second inductor L2, a third inductor L3 and a second capacitor C2; the broadband input amplification stage comprises a first transistor M1, a second transistor M2, a fourth inductor L4, a third capacitor C3 and a first feedback resistor Rf1; the first broadband interstage matching network comprises a fifth inductor L5, a fourth capacitor C4, a fifth capacitor C5, a sixth inductor L6, a seventh inductor L7 and an eighth inductor L8; the broadband intermediate amplification stage comprises a third transistor M3, a sixth capacitor C6, a second feedback resistor Rf2 and a ninth inductor L9; the second broadband interstage matching network comprises a tenth inductor L10 and a seventh capacitor C7; the high-frequency interstage matching network comprises a twelfth inductor L12 and a thirteenth inductor L13, and the low-frequency interstage matching network and the low-frequency output matching network are both eleventh inductors L11; the first-stage high-frequency broadband output amplification stage comprises a fourth transistor M4, a fourteenth inductor L14, a fifth transistor M5, a tenth capacitor C10 and a third feedback resistor Rf3; the high-frequency broadband output amplification stage interstage matching network comprises an eleventh capacitor C11 and a sixteenth inductor L16; the second-stage high-frequency broadband output amplification stage comprises a sixth transistor M6, a twelfth capacitor C12, a fourth feedback resistor Rf4 and a seventeenth inductor L17, and the low-frequency broadband output amplification stage is a transmission line; the high-frequency output matching network comprises a thirteenth capacitor C13, a fourteenth capacitor C14, an eighteenth inductor L18 and a nineteenth inductor L19; the low-frequency output blocking capacitor is a fifteenth capacitor C15, and the high-frequency output blocking capacitor is a thirteenth capacitor C13;
wherein one end of the first capacitor C1 is an input end of a radio frequency signal, the other end of the first capacitor C1 is connected with one end of the first inductor L1, the other end of the first inductor L1 is connected with one end of the second capacitor C2 and one end of the second inductor L2, the other end of the second inductor L2 is connected with a grid electrode of the first transistor M1, one end of the third capacitor C3 and one end of the first bias resistor, a source electrode of the first transistor M1 is connected with one end of the third inductor L3, a drain electrode of the first transistor M1 is connected with one end of the fourth inductor L4, the other end of the fourth inductor L4 is connected with a source electrode of the second transistor M2, a grid electrode of the second transistor M2 is connected with one end of the second bias resistor Rg2, a drain electrode of the second transistor M2 is connected with one end of the first feedback resistor Rf1, one end of the fifth inductor L5 and one end of the fourth capacitor C4, the other end of the first feedback resistor Rf1 is connected with one end of the third capacitor C3, the other end of the fourth capacitor C4 is connected with one end of a sixth inductor L6, the other end of the sixth inductor L6 is connected with one end of a fifth capacitor C5 and one end of a seventh inductor L7, the other end of the seventh inductor L7 is connected with the grid electrode of a third transistor M3, one end of the sixth capacitor C6 and one end of a first bias resistor, the source electrode of the third transistor M3 is connected with one end of an eighth inductor L8, the drain end of the third transistor M3 is connected with one end of a ninth inductor L9, one end of a tenth inductor L10 and one end of a seventh capacitor C7, the other end of the ninth inductor L9 is connected with one end of a second feedback resistor Rf2, the other end of the second feedback resistor Rf2 is connected with the sixth capacitor C6, one end of the seventh capacitor C7 is connected with the input end of a coupling line, the direct end of the coupling line is connected with one end of an eleventh inductor L11, one end of the eighth capacitor C8 and one end of the fifteenth capacitor, the other end of the fifteenth capacitor is connected with a low-frequency output end out2, the isolation end of the coupling line is connected with one end of a ninth capacitor, the coupling end of the coupling line is connected with one end of a twelfth inductor L12, the other end of the twelfth inductor L12 is connected with the grid electrode of a fourth transistor M4, one end of a tenth capacitor C10 and one end of a fourth bias resistor, the source electrode of the fourth transistor M4 is connected with one end of a thirteenth capacitor L13, the drain electrode of the fourth transistor M4 is connected with one end of a fourteenth inductor L14, the other end of the fourteenth inductor L14 is connected with the source electrode of a fifth transistor M5, the grid electrode of the fifth transistor M5 is connected with one end of a fifth bias resistor Rg2, the drain electrode of the fifth transistor M5 is connected with one end of a third feedback resistor Rf3, one end of a fifteenth inductor L15 and one end of an eleventh capacitor C11, the other end of the thirteenth capacitor C3 is connected with one end of the tenth capacitor C10, the other end of the eleventh capacitor C11 is connected with the thirteenth capacitor C11, the grid electrode of the sixth transistor M6 is connected with the thirteenth capacitor C6, the drain electrode of the sixteenth capacitor M6 is connected with the seventeenth capacitor C13, the seventeenth capacitor C13 is connected with the seventeenth end of the nineteenth capacitor C4, and the seventeenth capacitor C is connected with the seventeenth capacitor C13, and the seventeenth capacitor C is connected with the seventeenth capacitor C1, and the seventeenth capacitor is connected with the seventeenth capacitor, the seventeenth capacitor and the one 13.
The mechanism of the invention is as follows: in order to realize the noise coefficient smaller than 1.5dB on the ultra-wide frequency band covering the high frequency band and the low frequency band, the broadband input amplification stage only carries out the broadband minimum noise matching without considering gain fluctuation, and the gain fluctuation is compensated by the post-stage circuit; the intermediate amplifying stage raises the signal gain to suppress post-stage noise; the coupling line is used as a frequency division duplexer, the ultra-wideband is divided into a high frequency band and a low frequency band to be output simultaneously by adjusting the length of the coupling line and a bypass capacitor, and gain fluctuation of a high-frequency output signal is compensated simultaneously; the output amplifier stage further compensates for gain fluctuations.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
the technical scheme of the invention realizes that the low-noise amplifier realizes the simultaneous output of an input signal through a high-frequency path and a low-frequency path by introducing a frequency division duplexer based on a coupling line and setting an output amplification stage to compensate gain fluctuation; according to the technical scheme, the low-noise amplifier achieves a noise coefficient smaller than 1.5dB and a gain fluctuation smaller than 3dB in two ultra-wide frequency bands of low frequency bands of 2.5 GHz-5 GHz and high frequency bands of 5 GHz-18 GHz, and the gain fluctuation of a high-frequency output signal and a low-frequency output signal is smaller than 3dB.
Drawings
Fig. 1 is a schematic diagram of the topology of the frequency division duplex ultra wideband low noise amplifier of the present invention.
Fig. 2 is a circuit configuration diagram of an ultra wideband low noise amplifier according to embodiment 1 of the present invention.
Fig. 3 is a noise figure simulation diagram of an ultra wideband low noise amplifier according to embodiment 1 of the present invention.
Fig. 4 is a gain simulation diagram of an ultra wideband low noise amplifier according to embodiment 1 of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the embodiments and the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent.
The topological structure diagram of the ultra-wideband low noise amplifier with frequency division duplex is shown in figure 1, and the ultra-wideband low noise amplifier comprises a bias network, an input blocking capacitor, a wideband input matching network, a wideband input amplification stage, a first wideband interstage matching network, a wideband intermediate amplification stage, a second wideband interstage matching network, a duplexer, a third wideband interstage matching network group, a wideband output amplification stage group, a wideband output stage matching network group and an output blocking capacitor group which are sequentially connected in series;
the third broadband interstage matching network group consists of a high-frequency interstage matching network and a low-frequency interstage matching network, the broadband output amplification stage group consists of a high-frequency broadband output amplification stage group and a low-frequency broadband output amplification stage, and the broadband output stage matching network group consists of a high-frequency output matching network and a low-frequency output matching network; the high-frequency broadband output amplification stage group is formed by connecting a first high-frequency broadband output amplification stage, a high-frequency broadband output amplification stage interstage matching network and a second high-frequency broadband output amplification stage in series; the output blocking capacitor group consists of a high-frequency output blocking capacitor and a low-frequency output blocking capacitor.
The input blocking capacitor is used for blocking an input signal and outputting the signal; the broadband input matching network is used for matching the signal source impedance with the input impedance of the low-noise amplifier; the broadband input amplification stage is used for amplifying an input signal at the cost of less than 1dB noise figure without considering gain fluctuation of the input amplification stage; the first broadband interstage matching network is used for matching the output impedance of the broadband input amplification stage with the input impedance of the broadband intermediate amplification stage; the broadband intermediate amplification stage is used for further amplifying the signals amplified by the broadband input amplification stage, so that noise caused by the insertion loss of the duplexer and the active circuits of the broadband output amplification stage group is suppressed; the second broadband interstage matching network is used for matching the output impedance of the broadband intermediate amplification stage and the input impedance of the duplexer; the duplexer is used for dividing an input radio frequency signal into a high-frequency signal and a low-frequency signal for output; the third broadband interstage matching network group is used for matching duplex output impedance and broadband output amplification stage group input impedance; the broadband output amplification stage group is used for compensating gain fluctuation brought by the broadband input amplification stage and the broadband intermediate amplification stage; the output blocking capacitor group is used for blocking output signals and outputting the signals; the bias network is used for providing bias voltage for the transistor.
Example 1
An ultra-wideband low noise amplifier with frequency division duplex is shown in fig. 2, wherein the input blocking capacitor is a first capacitor C1;
the broadband input matching network comprises inductors L1, L2, L3 and C2, the inductors L1 and L2 are connected between an input blocking capacitor C1 and the grid electrode of a transistor M1 in series, the capacitor C2 is connected between the common end of the L1 and L2 and the ground, and the inductor L3 is connected between the source electrode of the transistor M1 and the ground in series;
the broadband input amplification stage comprises a cascode structure with an intermediate inductor and formed by a transistor M1, an inductor L4 and a transistor M2 and a feedback loop formed by a capacitor C3 and a feedback resistor Rf1, wherein the drain electrode of the transistor M1, the inductor L4 and the source electrode of the transistor M2 are sequentially connected in series, and the capacitor C3 and the feedback resistor Rf1 are connected in series between the grid electrode of the transistor M1 and the drain electrode of the transistor M2;
the first broadband interstage matching network comprises inductors L5, L6, L7 and L8, capacitors C4 and C5, the inductor L5 is connected between the drain electrode of the transistor M2 and a power supply VDD in series, the C4, L6 and L7 are connected between the drain electrode of the transistor M2 and the grid electrode of the transistor M3 in series, the C5 is connected between the common end of the L6 and the L7 and the ground, and the inductor L8 is connected between the source electrode of the transistor M3 and the ground in series;
the broadband intermediate amplification stage comprises a feedback loop formed by a transistor M3 and a capacitor C6, a feedback resistor Rf2 and an inductor L9, wherein the source electrode of the transistor M3 is connected with the inductor L8 in series, and the capacitor C6, the capacitor Rf2 and the inductor L9 are connected between the grid electrode and the drain electrode of the transistor M3 in series;
the second broadband interstage matching network comprises an inductor L10 and a capacitor C7, wherein the inductor L10 is connected between the drain electrode of the transistor M4 and the power supply VDD in series, and the capacitor C7 is connected between the drain electrode of the transistor M4 and the input end of the duplexer in series;
the duplexer comprises a coupling line, C8 and C9, wherein the input end of the coupling line is connected with C7 in series, the direct end of the coupling line is connected with C8 in series and grounded, the isolation end of the coupling line is connected with C9 in series and the coupling end of the coupling line is connected with L12 in series;
the high-frequency interstage matching network comprises L12 and L13, an inductor L12 is connected between the coupling end of the coupling line and the grid electrode of the transistor M4 in series, and the inductor L13 is connected between the source electrode of the transistor M4 and the ground in series;
the first-stage high-frequency broadband output amplification stage comprises a common-source common-gate structure with an intermediate inductance, which is composed of a transistor M4, an inductance L14 and a transistor M5, and a feedback loop, which is composed of a capacitor C10 and a feedback resistor Rf3, wherein the drain electrode of the transistor M4, the inductance L14 and the source electrode of the transistor M5 are sequentially connected in series, and the capacitors C10 and Rf3 are connected in series between the grid electrode of the transistor M4 and the drain electrode of the transistor M5;
the high-frequency broadband output amplification stage interstage matching network comprises C11 and L16, a capacitor C11 is connected between the drain end of the transistor M5 and the grid electrode of the transistor M6 in series, and an inductor L16 is connected between the source electrode of the transistor M6 and the ground in series;
the second-stage high-frequency broadband output amplification stage comprises a feedback loop formed by a transistor M6 and a capacitor C12, a feedback resistor Rf4 and an inductor L17, wherein the source electrode of the transistor M6 is connected with the inductor L16 in series, and the capacitors C12, rf4 and the inductor L17 are connected between the grid electrode and the drain electrode of the transistor M6 in series;
the high-frequency output matching network comprises C13, C14, L18 and L19, an inductor L18 is connected between the drain electrode of the transistor M6 and the power supply voltage in series, a capacitor C13 and L19 is connected between the drain electrode of the transistor M6 and the output port RFout1 in series, and a capacitor C14 is connected between the common terminal of the C13 and L19 and the ground;
the high-frequency output blocking capacitor is C13;
the low-frequency interstage matching network and the low-frequency output matching network are L11, and the inductor L11 is connected between the straight-through end of the coupling line and the ground in series;
the low frequency broadband output amplifier stage is a transmission line because the gain of the low frequency signal is large enough to avoid further amplification at the output amplifier stage;
the low frequency output dc blocking capacitance is C15.
The noise figure simulation diagram of the ultra wideband low noise amplifier is shown in fig. 3, and the gain simulation diagram is shown in fig. 4.
As can be seen from FIG. 3, the noise coefficient of the amplifier is smaller than 1.1dB in the low frequency band (2.5 GHz-5 GHz), and smaller than 1.4dB in the high frequency band (5 GHz-18 GHz); as can be seen from FIG. 4, the gain fluctuation range is 24.4-25.3 dB in the low frequency range from 2.5GHz to 5GHz, and the gain fluctuation range is 24.2-26.2 dB in the low frequency range from 5GHz to 18 GHz. Therefore, the invention realizes the simultaneous amplification and output of two ultra-wideband signals, and can realize very small noise coefficient and gain fluctuation in each frequency band.
While the invention has been described in terms of specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.
Claims (4)
1. The ultra-wideband low noise amplifier is characterized by comprising a bias network, an input blocking capacitor, a wideband input matching network, a wideband input amplification stage, a first wideband interstage matching network, a wideband intermediate amplification stage, a second wideband interstage matching network, a duplexer, a third wideband interstage matching network group, a wideband output amplification stage group, a wideband output stage matching network group and an output blocking capacitor group which are sequentially connected in series;
the third broadband interstage matching network group consists of a high-frequency interstage matching network and a low-frequency interstage matching network, the broadband output amplification stage group consists of a high-frequency broadband output amplification stage group and a low-frequency broadband output amplification stage, and the broadband output stage matching network group consists of a high-frequency output matching network and a low-frequency output matching network; the high-frequency broadband output amplification stage group is formed by connecting a first high-frequency broadband output amplification stage, a high-frequency broadband output amplification stage interstage matching network and a second high-frequency broadband output amplification stage in series; the output blocking capacitor group consists of a high-frequency output blocking capacitor and a low-frequency output blocking capacitor;
the input blocking capacitor is used for blocking an input signal and outputting the signal; the broadband input matching network is used for matching the signal source impedance with the input impedance of the low-noise amplifier; the broadband input amplification stage is used for amplifying an input signal without considering gain fluctuation of the input amplification stage; the first broadband interstage matching network is used for matching the output impedance of the broadband input amplification stage with the input impedance of the broadband intermediate amplification stage; the broadband intermediate amplification stage is used for further amplifying the signals amplified by the broadband input amplification stage, so that noise caused by the insertion loss of the duplexer and the active circuits of the broadband output amplification stage group is suppressed; the second broadband interstage matching network is used for matching the output impedance of the broadband intermediate amplification stage and the input impedance of the duplexer; the duplexer is used for dividing an input radio frequency signal into a high-frequency signal and a low-frequency signal for output; the third broadband interstage matching network group is used for matching duplex output impedance and broadband output amplification stage group input impedance; the broadband output amplification stage group is used for compensating gain fluctuation brought by the broadband input amplification stage and the broadband intermediate amplification stage; the output blocking capacitor group is used for blocking output signals and outputting the signals; the bias network is used for providing bias voltage for the transistor;
the bias network comprises a first bias resistor Rg1, a second bias resistor Rg2, a third bias resistor Rg3, a fourth bias resistor Rg4, a fifth bias resistor Rg5 and a sixth bias resistor Rg6; the input blocking capacitor is a first capacitor C1; the broadband input matching network comprises a first inductor L1, a second inductor L2, a third inductor L3 and a second capacitor C2; the broadband input amplification stage comprises a first transistor M1, a second transistor M2, a fourth inductor L4, a third capacitor C3 and a first feedback resistor Rf1; the first broadband interstage matching network comprises a fifth inductor L5, a fourth capacitor C4, a fifth capacitor C5, a sixth inductor L6, a seventh inductor L7 and an eighth inductor L8; the broadband intermediate amplification stage comprises a third transistor M3, a sixth capacitor C6, a second feedback resistor Rf2 and a ninth inductor L9; the second broadband interstage matching network comprises a tenth inductor L10 and a seventh capacitor C7; the high-frequency interstage matching network comprises a twelfth inductor L12 and a thirteenth inductor L13, and the low-frequency interstage matching network and the low-frequency output matching network are both eleventh inductors L11; the first high-frequency broadband output amplification stage comprises a fourth transistor M4, a fourteenth inductor L14, a fifth transistor M5, a tenth capacitor C10 and a third feedback resistor Rf3; the high-frequency broadband output amplification stage interstage matching network comprises an eleventh capacitor C11 and a sixteenth inductor L16; the second high-frequency broadband output amplification stage comprises a sixth transistor M6, a twelfth capacitor C12, a fourth feedback resistor Rf4 and a seventeenth inductor L17, and the low-frequency broadband output amplification stage is a transmission line; the high-frequency output matching network comprises a thirteenth capacitor C13, a fourteenth capacitor C14, an eighteenth inductor L18 and a nineteenth inductor L19; the low-frequency output blocking capacitor is a fifteenth capacitor C15, and the high-frequency output blocking capacitor is a thirteenth capacitor C13;
wherein one end of the first capacitor C1 is an input end of a radio frequency signal, the other end of the first capacitor C1 is connected with one end of the first inductor L1, the other end of the first inductor L1 is connected with one end of the second capacitor C2 and one end of the second inductor L2, the other end of the second inductor L2 is connected with a grid electrode of the first transistor M1, one end of the third capacitor C3 and one end of the first bias resistor, a source electrode of the first transistor M1 is connected with one end of the third inductor L3, a drain electrode of the first transistor M1 is connected with one end of the fourth inductor L4, the other end of the fourth inductor L4 is connected with a source electrode of the second transistor M2, a grid electrode of the second transistor M2 is connected with one end of the second bias resistor Rg2, a drain electrode of the second transistor M2 is connected with one end of the first feedback resistor Rf1, one end of the fifth inductor L5 and one end of the fourth capacitor C4, the other end of the first feedback resistor Rf1 is connected with one end of the third capacitor C3, the other end of the fourth capacitor C4 is connected with one end of a sixth inductor L6, the other end of the sixth inductor L6 is connected with one end of a fifth capacitor C5 and one end of a seventh inductor L7, the other end of the seventh inductor L7 is connected with the grid electrode of a third transistor M3, one end of the sixth capacitor C6 and one end of a first bias resistor, the source electrode of the third transistor M3 is connected with one end of an eighth inductor L8, the drain end of the third transistor M3 is connected with one end of a ninth inductor L9, one end of a tenth inductor L10 and one end of a seventh capacitor C7, the other end of the ninth inductor L9 is connected with one end of a second feedback resistor Rf2, the other end of the second feedback resistor Rf2 is connected with the sixth capacitor C6, one end of the seventh capacitor C7 is connected with the input end of a coupling line, the direct end of the coupling line is connected with one end of an eleventh inductor L11, one end of the eighth capacitor C8 and one end of the fifteenth capacitor, the other end of the fifteenth capacitor is connected with a low-frequency output end out2, the isolation end of the coupling line is connected with one end of a ninth capacitor, the coupling end of the coupling line is connected with one end of a twelfth inductor L12, the other end of the twelfth inductor L12 is connected with the grid electrode of a fourth transistor M4, one end of a tenth capacitor C10 and one end of a fourth bias resistor, the source electrode of the fourth transistor M4 is connected with one end of a thirteenth capacitor L13, the drain electrode of the fourth transistor M4 is connected with one end of a fourteenth inductor L14, the other end of the fourteenth inductor L14 is connected with the source electrode of a fifth transistor M5, the grid electrode of the fifth transistor M5 is connected with one end of a fifth bias resistor Rg2, the drain electrode of the fifth transistor M5 is connected with one end of a third feedback resistor Rf3, one end of a fifteenth inductor L15 and one end of an eleventh capacitor C11, the other end of the thirteenth capacitor C3 is connected with one end of the tenth capacitor C10, the other end of the eleventh capacitor C11 is connected with the thirteenth capacitor C11, the grid electrode of the sixth transistor M6 is connected with the thirteenth capacitor C6, the drain electrode of the sixteenth capacitor M6 is connected with the seventeenth capacitor C13, the seventeenth capacitor C13 is connected with the seventeenth end of the nineteenth capacitor C4, and the seventeenth capacitor C is connected with the seventeenth capacitor C13, and the seventeenth capacitor C is connected with the seventeenth capacitor C1, and the seventeenth capacitor is connected with the seventeenth capacitor, the seventeenth capacitor and the one 13.
2. The frequency division duplex ultra wideband low noise amplifier of claim 1, wherein the diplexer is a coupled line based frequency division diplexer; by providing a bypass-to-ground capacitance at the through-and coupling-or through-and isolation-ends of the coupled line, the port of the coupled line plus the bypass capacitance is equivalent to a short-circuit ground for high frequency signals.
3. The ultra wideband low noise amplifier of claim 2, wherein when the direct end and the coupling end of the coupling line are respectively connected to the bypass capacitor, and the input end and the isolation end are impedance matched, the isolation end is a high frequency signal output port, the high frequency signal will flow out from the isolation end with less than 1dB insertion loss, and the low frequency signal will flow out from the direct end with less than 1dB insertion loss; when the direct end and the isolation end of the coupling line are respectively connected into the bypass capacitor, and the input end is matched with the coupling end port, the coupling end is a high-frequency signal output port, high-frequency signals can flow out from the coupling end with insertion loss smaller than 1dB, and low-frequency signals can flow out from the direct end with insertion loss smaller than 1 dB.
4. The ultra wideband low noise amplifier of frequency division duplex according to claim 2, wherein the demarcation frequency point of the low frequency and the high frequency is changed by adjusting the capacitance of a bypass capacitor connected in parallel to the port of the coupling line, and the demarcation frequency point moves toward the high frequency when the capacitance increases.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111181320.8A CN114024512B (en) | 2021-10-11 | 2021-10-11 | Ultra-wideband low noise amplifier of frequency division duplex |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111181320.8A CN114024512B (en) | 2021-10-11 | 2021-10-11 | Ultra-wideband low noise amplifier of frequency division duplex |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114024512A CN114024512A (en) | 2022-02-08 |
| CN114024512B true CN114024512B (en) | 2023-07-21 |
Family
ID=80055787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111181320.8A Active CN114024512B (en) | 2021-10-11 | 2021-10-11 | Ultra-wideband low noise amplifier of frequency division duplex |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114024512B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113676145B (en) * | 2021-07-27 | 2023-07-21 | 电子科技大学 | Broadband low-noise amplifier with reconfigurable frequency band |
| CN114553155B (en) * | 2022-04-22 | 2022-08-16 | 成都嘉纳海威科技有限责任公司 | Ultra-wideband radio frequency amplifier covering fundamental frequency |
| CN114759882B (en) * | 2022-05-06 | 2022-12-09 | 广东工业大学 | Dual-frequency coupling low-noise amplification circuit and amplifier |
| US11742807B1 (en) | 2023-02-14 | 2023-08-29 | Guangdong University Of Technology | Dual-band coupling low-noise amplifying circuit and amplifier |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106712725A (en) * | 2016-11-03 | 2017-05-24 | 南京邮电大学 | Ultra wideband high-gain low noise amplifier based on monolithic microwave integrated circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7609115B2 (en) * | 2007-09-07 | 2009-10-27 | Raytheon Company | Input circuitry for transistor power amplifier and method for designing such circuitry |
| CN110034738B (en) * | 2019-04-26 | 2023-04-28 | 南京理工大学 | Ultra-wideband low-noise amplifier based on improved impedance matching network |
| CN112583369B (en) * | 2019-09-27 | 2023-04-07 | 天津大学 | Dual-frequency millimeter wave low-noise amplifier |
| CN111404492B (en) * | 2020-04-30 | 2024-07-19 | 华南理工大学 | Broadband flat gain variable gain low noise amplifier |
| CN113206644B (en) * | 2021-03-24 | 2022-05-27 | 电子科技大学 | High-efficiency distributed power amplifier with reconfigurable bandwidth |
| CN113381713A (en) * | 2021-06-07 | 2021-09-10 | 武汉大学 | Dual-band low-noise amplifier based on reconfigurable inductor |
-
2021
- 2021-10-11 CN CN202111181320.8A patent/CN114024512B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106712725A (en) * | 2016-11-03 | 2017-05-24 | 南京邮电大学 | Ultra wideband high-gain low noise amplifier based on monolithic microwave integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114024512A (en) | 2022-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114024512B (en) | Ultra-wideband low noise amplifier of frequency division duplex | |
| CN101282110B (en) | Low-power consumption single-ended input difference output low-noise amplifier | |
| CN111106804B (en) | Millimeter wave ultra-wideband high-gain low-power-consumption low-noise amplification chip circuit | |
| CN106712725A (en) | Ultra wideband high-gain low noise amplifier based on monolithic microwave integrated circuit | |
| CN113114116B (en) | Radio frequency low noise amplifier | |
| CN108336976B (en) | Multi-band low-noise amplifier and amplifying method | |
| CN211209671U (en) | Millimeter wave ultra-wideband high-gain low-power-consumption low-noise amplifier chip circuit | |
| CN111293999B (en) | Broadband reconfigurable power amplifier and radar system | |
| CN206195723U (en) | Ultra wide band high -gain low -noise amplifier based on monolithic microwave integrated circuit | |
| CN108322191B (en) | Multi-band low-noise amplifier and amplification method | |
| CN112583369B (en) | Dual-frequency millimeter wave low-noise amplifier | |
| CN110034738B (en) | Ultra-wideband low-noise amplifier based on improved impedance matching network | |
| CN109525203B (en) | Intermediate frequency amplifier based on GaAs pHEMT process | |
| CN113381713A (en) | Dual-band low-noise amplifier based on reconfigurable inductor | |
| CN114785286B (en) | Ultra-wideband passive down-conversion mixer | |
| CN115765634A (en) | Power amplifying circuit | |
| CN117713702A (en) | Low-power consumption low-gain variation stability enhanced low-noise amplifier | |
| CN111884615B (en) | High-order broadband input impedance matching network and application thereof | |
| CN117375544A (en) | Ultra-wideband distributed low-noise amplifier with triple cascade structure | |
| CN218829863U (en) | Dual-band power amplification module and radio frequency power amplifier | |
| CN113904635B (en) | High third-order intermodulation point field effect transistor radio frequency amplifier | |
| CN113676145B (en) | Broadband low-noise amplifier with reconfigurable frequency band | |
| CN106936399B (en) | A kind of consumption high gain high linearity broadband low-noise amplifier | |
| CN209844918U (en) | High-octave ultra-wideband input matching circuit for low-noise amplifier | |
| CN110113013B (en) | High octave ultra-wideband input matching circuit for low noise amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |