CN214101479U - Digital image processing system based on FPGA and double DSPs - Google Patents

Abstract

The utility model provides a digital image processing system based on FPGA and double DSP, which comprises an FPGA unit, an interface control unit and a DSP unit; the FPGA unit is respectively connected with the interface control unit and the DSP unit; the DSP unit comprises a data processing DSP module and an external control DSP module which are connected with the FPGA unit; the utility model discloses on current FPGA combines DSP to carry out image processing's basis, additionally add a DSP module, use the FPGA unit as image data's receiving and dispatching unit and image data's preprocessing unit, realize analog video signal output, realize faster and further complicated image processing algorithm through a DSP module, combine another DSP module to carry out special peripheral hardware control, increase the speed of control response.

Description

Digital image processing system based on FPGA and double DSPs

Technical Field

The utility model belongs to the technical field of digital image processing, specifically speaking relates to a digital image processing system based on FPGA and two DSP.

Background

With the continuous development of science and technology, digital image processing technology is widely applied to the fields of aerospace, communication, medicine, industrial production and the like. Digital image processing is characterized by a large amount of data to be processed and time-consuming processing. In a real-time image processing system, how to complete the processing of a large amount of information data within a limited time, meet the real-time requirement of the system, and can quickly respond to the control of the peripheral equipment after the digital image processing is always a problem.

With the continuous development of electronic technology in recent years, the appearance of a high-performance programmable logic unit FPGA and a digital signal processor DSP solves the problems of large data processing amount, low processing speed and the like of digital images. The FPGA is a semi-custom circuit, and the FPGA can realize the flow processing of digital image signals. The DSP is a special digital processing chip, has high speed, flexibility, programmability and low power consumption, and is widely applied to the fields of digital image processing, voice processing, signal processing and the like. At present, the digital image processing modes mainly adopted in the market are three types: the FPGA realizes digital image processing, the DSP realizes digital image processing, and the FPGA and the DSP realize digital image processing. The complex digital image processing algorithm is difficult to realize by adopting a single FPGA, the flexibility is poor, and the real-time performance is guaranteed. A single DSP is adopted to realize a complex algorithm of digital image processing, but the real-time performance cannot be guaranteed, and the FPGA + DSP structure is a mainstream mode at present to realize the image processing, can guarantee the complex algorithm and the real-time performance, but has slow response to external control.

There is a need for a digital image processing design with fast digital image processing speed, high real-time performance, and fast response to external control.

SUMMERY OF THE UTILITY MODEL

The utility model discloses to prior art's above-mentioned demand, a digital image processing system based on FPGA and two DSP is proposed, combine DSP to carry out image processing's basis at current FPGA, additionally add a DSP module, use the FPGA unit as image data's the receiving and dispatching unit and the preprocessing unit of image data, realize analog video signal output, realize faster and further complicated image processing algorithm through a DSP module, combine another DSP module to carry out special peripheral control, increase the speed of control response.

The utility model discloses specifically realize the content as follows:

the utility model provides a digital image processing system based on FPGA and double DSP, which comprises an FPGA unit, an interface control unit, a DSP unit, a clock unit and a power management unit;

the FPGA unit is respectively connected with the interface control unit and the DSP unit;

the DSP unit comprises a data processing DSP module connected with the FPGA unit through an EMIF, a GPIO, an SRIO and a UART bus and an external control DSP module connected with the FPGA unit through an EMIF, a GPIO and a UART bus;

the interface control unit comprises a first video coding module, a second video coding module, a first serializer/deserializer, a second serializer/deserializer, an ADC (analog-to-digital converter) module, an OC (open circuit) gate module, an RS232 bus module and an RS422 bus module; the FPGA unit is respectively connected with the input end of the first video coding module, the input end of the second video coding module, the input end of the first deserializer, the output end of the second deserializer, the output end of the ADC module, the input end of the OC door module, the RS232 bus module and the RS422 bus module;

the interface control unit also comprises a first signal conditioning unit connected with the output end of the first video coding module and a second signal conditioning unit connected with the input end of the ADC module;

the first signal conditioning unit is a differential signal amplifying circuit; the second signal conditioning unit is a circuit for converting differential signals into single ends;

the OC door module is a PWM signal driving circuit;

the clock unit is respectively connected with the FPGA unit, the peripheral control DSP module and the data processing DSP module; and the power supply management unit is respectively connected with the FPGA unit, the interface control unit and the DSP unit.

In order to better realize the utility model discloses, furtherly, the FPGA unit adopts XC7K325T-2FFG900I chip to carry on first FLASH module, first DDR3 module and the module that resets on XC7K325T-2FFG900I chip.

In order to better realize the utility model, further, the data processing DSP module comprises a TMS320C6674 chip, and a second FLASH module, a second DDR3 module and a second reset module mounted on the TMS320C6674 chip;

the 16-bit EMIF address line interface, the UART interface, the I2C interface, the SPI interface and 16 GPIO interfaces comprising GPIO 0-GPIO 15 interfaces of the TMS320C6674 chip are respectively connected with an XC7K325T-2FFG900I chip of the FPGA unit.

In order to better realize the utility model, furthermore, the peripheral control DSP module adopts a TMS320F28335 chip, and a third FLASH module and a third reset module are also carried on the TMS320F28335 chip;

the 16bit EMIF address line interface, the UART interface and the 16 GPIO interfaces of the TMS320F28335 chip are respectively connected with the XC7K325T-2FFG900I chip of the FPGA unit; the 16 GPIO interfaces of the TMS320F28335 chip are a GPIO0 interface, a GPIO2 interface, GPIO 12-15 interfaces, a GPIO20 interface, a GPIO21 interface, a GPIO34 interface and GPIO 48-54 interfaces respectively.

In order to better realize the utility model, further, the first video coding module adopts an ADV7391BCPZ chip to form a video coding circuit; the second video coding module adopts MAX9247 chip

In order to better realize the utility model discloses, furtherly, first serializer deserializer and second serializer are CML video interface circuit, adopt TLK1501IRCP chip.

In order to better realize the utility model discloses, further, the OC door module is PWM signal drive circuit, adopts the SNJ5407W chip.

In order to better implement the present invention, the second DDR3 module includes four IS43TR16512BL-107MBLI SDRAM chips, and the four IS43TR16512BL-107MBLI SDRAM chips jointly constitute a memory expansion unit of the TMS320C6674 chip.

In order to better realize the utility model, further, the first DDR3 module includes a slice of IS43TR16512BL-107MBLI SDRAM chip, the IS43TR16512BL-107MBLI SDRAM chip of the first DDR3 module constitutes the memory expansion unit of XC7K325T-2FFG900I chip of FPGA unit.

In order to better realize the utility model discloses, furtherly, RS422 bus module sets up 5 way RS422 serial ports communication interface of being connected with the FPGA unit to adopt RS-422 bus transceiver MAX3490ESA to realize RS422 interface level conversion.

Compared with the prior art, the utility model have following advantage and beneficial effect:

the utility model provides a digital image processing system based on FPGA and two DSP, on current FPGA combines DSP to carry out image processing's basis, additionally add a DSP module, use the FPGA unit as image data's receiving and dispatching unit and image data's preprocessing unit, realize analog video signal output, realize faster and further complicated image processing algorithm through a DSP module, combine another DSP module to carry out special peripheral hardware control, increase the speed of control response.

Drawings

Fig. 1 is a block diagram of a system module of the present invention;

fig. 2 is a schematic circuit diagram of the serializer of the present invention;

FIG. 3 is a schematic circuit diagram of a video encoding module;

FIG. 4 IS a schematic diagram of an IS43TR16512BL-107MBLI SDRAM chip circuit employed by the DDR3 module;

FIG. 5 is a schematic circuit diagram of an RS422 module;

FIG. 6 is a circuit schematic diagram of a FLASH module;

FIG. 7 is a schematic diagram of a JTAG port circuit;

FIG. 8 is a schematic diagram of a PWM signal driving circuit of the OC gate module;

FIG. 9 is a circuit schematic of an LVDS video interface output;

fig. 10 is a schematic diagram of a circuit using a phase locked loop CDCM61004 for the clock.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only some embodiments of the present invention, but not all embodiments, and therefore should not be considered as limitations to the scope of protection. Based on the embodiments in the present invention, all other embodiments obtained by the staff of ordinary skill in the art without creative work belong to the protection scope of the present invention.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example 1:

the embodiment provides a digital image processing system based on an FPGA and double DSPs, as shown in FIG. 1, comprising an FPGA unit, an interface control unit, a DSP unit, a clock unit and a power management unit;

the FPGA unit is respectively connected with the interface control unit and the DSP unit;

the DSP unit comprises a data processing DSP module connected with the FPGA unit through an EMIF, a GPIO, an SRIO and a UART bus and an external control DSP module connected with the FPGA unit through an EMIF, a GPIO and a UART bus;

the interface control unit comprises a first video coding module, a second video coding module, a first serializer/deserializer, a second serializer/deserializer, an ADC (analog-to-digital converter) module, an OC (open circuit) gate module, an RS232 bus module and an RS422 bus module; the FPGA unit is respectively connected with the input end of the first video coding module, the input end of the second video coding module, the input end of the first deserializer, the output end of the second deserializer, the output end of the ADC module, the input end of the OC door module, the RS232 bus module and the RS422 bus module;

the interface control unit also comprises a first signal conditioning unit connected with the output end of the first video coding module and a second signal conditioning unit connected with the input end of the ADC module;

the first signal conditioning unit is a differential signal amplifying circuit; the second signal conditioning unit is a circuit for converting differential signals into single ends;

the OC door module is a PWM signal driving circuit;

the clock unit is respectively connected with the FPGA unit, the peripheral control DSP module and the data processing DSP module; and the power supply management unit is respectively connected with the FPGA unit, the interface control unit and the DSP unit.

The working principle is as follows: the utility model provides a digital image processing system based on FPGA and two DSP, on current FPGA combines DSP to carry out image processing's basis, additionally add a DSP module, use the FPGA unit as image data's receiving and dispatching unit and image data's preprocessing unit, realize analog video signal output, realize faster and further complicated image processing algorithm through data processing DSP module, combine peripheral hardware control DSP module to carry out special peripheral hardware control, increase the speed of control response.

Example 2:

on the basis of the foregoing embodiment 1, in order to better implement the present invention, further, as shown in fig. 1, the FPGA unit employs an XC7K325T-2FFG900I chip, and a first FLASH module, a first DDR3 module, and a reset module are mounted on the XC7K325T-2FFG900I chip. The first FLASH module initializes the FPGA based on the SPI FLASH, and after the power is on, the FPGA automatically reads the configuration file stored in the SPI FLASH.

In order to better realize the utility model, further, the data processing DSP module comprises a TMS320C6674 chip, and a second FLASH module, a second DDR3 module and a second reset module mounted on the TMS320C6674 chip;

the 16-bit EMIF address line interface, the UART interface, the I2C interface, the SPI interface and 16 GPIO interfaces comprising GPIO 0-GPIO 15 interfaces of the TMS320C6674 chip are respectively connected with an XC7K325T-2FFG900I chip of the FPGA unit.

In order to better realize the utility model, furthermore, the peripheral control DSP module adopts a TMS320F28335 chip, and a third FLASH module and a third reset module are also carried on the TMS320F28335 chip;

the 16bit EMIF address line interface, the UART interface and the 16 GPIO interfaces of the TMS320F28335 chip are respectively connected with the XC7K325T-2FFG900I chip of the FPGA unit; the 16 GPIO interfaces of the TMS320F28335 chip are a GPIO0 interface, a GPIO2 interface, GPIO 12-15 interfaces, a GPIO20 interface, a GPIO21 interface, a GPIO34 interface and GPIO 48-54 interfaces respectively.

The working principle is as follows: the embodiment adopts a K7 series XC7K325T-2FFG900I chip produced by Xilinx company as a main controller, and the chip has a large amount of storage resources and abundant DSP resources. The controller mainly completes the functions of digital image data receiving and sending, digital image preprocessing, DDR3 cache, EMIF communication, image PAL display, character superposition and the like; the image data is preprocessed through the FPGA unit, and the image preprocessing function carries out algorithm processing such as median filtering and edge sharpening on the image data and then outputs the processed image data to the TMS320C6674 chip through the SRIO. The image preprocessing is realized in a pipeline mode, input image data are respectively stored in 3 double-port RAMs of software, three lines of data are read each time to form a 3 multiplied by 3 window for calculation, median filtering is used for comparing middle values in 9 pixel points, edge sharpening is composed of a Gaussian filter and a high-pass filter, and the first column of the preprocessed data is replaced by line number values.

DSP chips TMS320C6674ACYPA and TMS320F28335ZJZS which are introduced by Texas Instruments (TI) are adopted by design. The TMS320C6674ACYPA has the maximum main frequency of 1.25GHZ, supports an external memory interface EMIF and a 64-Bit DDR3 interface, has the maximum data reading rate of 1600MHz, and supports a 4X mode SRIO high-speed interface. TMS320F28335ZJZS master frequency 150MHZ, built-in on-chip memory, BOOT ROM space (8 Kx 16), support 3-path UART, support maximum 18-path PWM signal; and data interaction between the DSP unit and the FPGA is realized through the SRIO and the EMIF bus. The FPGA and the TMS320C6674ACYPA are interconnected by an SRIO high-speed bus (X4, 3.125Gbps), and 16bit EMIF (address line 24 bits), UART, I2C, SPI and 16 GPI0(GPIO 0-GPIO 15) interfaces of the TMS320C6674ACYPA are introduced into the FPGA; introducing 16bit EMIF, UART and 16 GPI0(0, 2, 12-15, 20, 21, 34, 48-54) interfaces of TMS320F28335ZJZS into the FPGA;

the FPGA selects a K7 series XC7K325T-2FFG900I chip produced by Xilinx company as a main controller, the chip has larger logic resources and IO resources compared with an XC7A200T _2FFG484I chip produced by an A7 series, more complex data image processing and more peripheral control can be completed, and the XC7K325T-2FFG900I has sufficient logic resources and can improve the speed of digital image processing by adopting a resource speed changing mode and ensure the real-time performance of the digital image processing. As the space of configuration FLASH required by larger logic resources of XC7K325T-2FFG900I is also increased, the FLASH is S25FL256SAGMFIR01 produced by SPANSION, the storage space of the chip is 256Mb, and the capacity of the chip is twice of that of M25P 128.

TMS320C6674ACYPA produced by TI company selected by DSP is different from TMS320C6672ACYPA in that 6674 has 4 CPU cores, 6672 has 2 CPU cores, the number of the cores of 6674 is one time of 6672, 6674 and 6672 process the same data, 6674 consumes shorter time, therefore 6674 can be selected to improve the data processing capability, the real-time performance of digital image processing is more guaranteed, the total storage capacity of 4 pieces of external DDR3 of TMS320C6674 is 4GB, compared with TMS320C6672ACYPA in 2 pieces of DDR3, the memory space is expanded by 1 time, and more data can be cached.

The FPGA and the TMS320F28335ZJZS are directly connected with 4 GPIO ports to be PWM control signals, and the FPGA is only used as a channel to realize the PWM external output of the TMS320F28335 ZJZS. TMS320F28335ZJZS passes through GPIO output PWM signal, and FPGA switches to corresponding pin, and the frequency and the duty cycle of PWM signal are carried out the configuration by TMS320F28335 ZJZS.

The DSP unit selects SPI Flash to realize program storage and starting, the level of a TMS320C6674ACYPA external design interface is 1.8V, as shown in FIG. 6, the model of a second Flash module is MT25QU128ABA8ESF, the storage capacity is 128Mbits, and the power supply voltage is 1.8V. The level of an external design interface of the DSP28335 is 3.3V, the model of the FLASH is MT25QL128ABA8ESF, the storage capacity is 128Mbits, and the power supply voltage is 3.3V.

The DSP JTAG debugging signal of the DSP unit is connected to the debugging interface connector, and the JTAG signal driving of the DSP unit is weak, so that the JTAG connection is unstable or can not be connected if the JTAG cable is too long. Moreover, JTAG is led out to the connector to be used for external debugging, and in order to ensure the working reliability of the JTAG external interface, a Buffer circuit is designed on the JTAG external interface part, so that the JTAG signal driving capability is enhanced, and simultaneously, the DSP device damage caused by external signal misconnection or ESD is avoided. The JTAG port circuit schematic is shown in FIG. 7.

Other parts of this embodiment are the same as those of embodiment 1, and thus are not described again.

Example 3:

in this embodiment, based on any one of the above embodiments 1-2, as shown in fig. 3, in order to better implement the present invention, further, the first video coding module adopts an ADV7391BCPZ chip to form a video coding circuit.

The working principle is as follows: the video encoder of the embodiment selects ADV7391BCPZ manufactured by ADI company, the chip supports Composite (CVBS), S-video (YC) or component (YPrPb/RGB) analog output of Standard Definition (SD) or High Definition (HD) video formats, the video format output this time is CVBS, image data generates valid video data according to ITU-rbt.656 video standard interface, and horizontal blanking, vertical blanking and control words are written into the ADV7391 data interface.

Other parts of this embodiment are the same as any of embodiments 1-2 described above, and thus are not described again.

Example 4:

on the basis of any one of the above embodiments 1-3, as shown in fig. 2, in order to better implement the present invention, further, the first serializer and the second serializer are CML video interface circuits, and a TLK1501IRCP chip is adopted.

The working principle is as follows: the FPGA receives CML image data input from the outside, and performs data analysis according to technical requirements to obtain complete digital image data. CML digital image input resolution ratio 640 x 512, 14bit/8bit hybrid transmission, 8bit and 14bit analyzed out are respectively stored in 2 asynchronous FIFO with depth of 1024, and generate line field effective signal, 8bit image data is written into the first DDR3 for buffer storage, 14bit image data is processed image preprocessing. And the CML video interface circuit performs row number verification according to the initial data packet and the end data packet, and performs 0 complementing treatment after row loss occurs.

The FPGA expands the received CML image resolution of 640 x 512 to 720 x 576 images, complementing 0 points, with the original image in the middle of 720 x 576. The ADV7391 register is configured via the I2C bus, and the ADV7391 is configured for YCrCb input EAV/SAV and CVSB/Y-C output modes. The active video data, horizontal blanking, vertical blanking and control word write ADV7391 data interface are generated according to the ITU-r bt.656 video standard interface, and the ADV7391 outputs an analog video signal.

Other parts of this embodiment are the same as any of embodiments 1 to 3, and thus are not described again.

Example 5:

in this embodiment, on the basis of any one of the above embodiments 1 to 4, as shown in fig. 8, in order to better implement the present invention, further, the OC gate module is a PWM signal driving circuit, and an SNJ5407W chip is adopted.

The working principle is as follows: the design selects SNJ5407W produced by TI company to realize PWM signal drive, the output of SNJ5407W is a ground open signal, and the additional pull-up resistor meets the output of 5V level.

Other parts of this embodiment are the same as any of embodiments 1 to 4, and thus are not described again.

Example 6:

based on any one of the above embodiments 1 to 5, as shown in fig. 4, in order to better implement the present invention, further, the second DDR3 module includes four IS43TR16512BL-107MBLI SDRAM chips, and the four IS43TR16512BL-107MBLI SDRAM chips jointly constitute a memory expansion unit of the TMS320C6674 chip. The design selects four IS43TR16512BL-107MBLI (512M 16 bit) SDRAM of ISSI company to realize the expansion of DSP6674 memory, the storage capacity can reach 8Gbytes, the data bit width IS 64bit, the working speed can reach 800MHz, DDR3 IS mainly used for operating application program of TMS320C6674 chip

In order to better realize the utility model, further, the first DDR3 module includes a slice of IS43TR16512BL-107MBLI SDRAM chip, the IS43TR16512BL-107MBLI SDRAM chip of the first DDR3 module constitutes the memory expansion unit of XC7K325T-2FFG900I chip of FPGA unit.

Other parts of this embodiment are the same as any of embodiments 1 to 5, and thus are not described again.

Example 7:

on the basis of any one of the above embodiments 1-6, as shown in fig. 5, in order to better implement the present invention, further, the RS422 bus module is provided with 5 paths of RS422 serial port communication interfaces connected with the FPGA unit, and the RS-422 bus transceiver MAX3490ESA is adopted to implement RS422 interface level conversion.

The working principle is as follows: 5 paths of RS422 serial port communication are designed, and the level conversion of the RS422 interface is realized by an RS-422 bus transceiver MAX3490ESA produced by Maxim company. The highest speed of the chip can reach 12 Mbps.

Other parts of this embodiment are the same as any of embodiments 1 to 6, and thus are not described again.

Example 8:

on the basis of any one of the above embodiments 1-7, in order to better implement the present invention, further, as shown in fig. 9, the second video coding module of the present design adopts two paths of LVDS video interface outputs, and the second video coding module specifically selects the MAX9247 chip produced by MAXIM corporation, which is a digital video parallel-serial converter, serializes 27 bits of parallel data into a serial data stream. The 18-bit video data and the 9-bit control data are encoded and multiplexed onto the serial interface, thereby reducing the serial data rate. The chip is powered by 3.3V, and a clock is generated inside the FPGA.

As shown in fig. 10, the design can output 2 paths of 156.25MHz clocks and 4 paths of 100MHz clocks, which are respectively supplied to the FPGA and the DSP6674, and the clocks adopt phase-locked loop CDCM61004 to realize the chip supporting LVPECL, LVDS, LVCMOS level output, and can provide 4 paths of differential or 8 paths of single-end output.

The above is only the preferred embodiment of the present invention, not to the limitation of the present invention in any form, all the technical matters of the present invention all fall into the protection scope of the present invention to any simple modification and equivalent change of the above embodiments.

Claims (10)

1. A digital image processing system based on FPGA and double DSP is characterized by comprising an FPGA unit, an interface control unit, a DSP unit, a clock unit and a power management unit;

the FPGA unit is respectively connected with the interface control unit and the DSP unit;

the DSP unit comprises a data processing DSP module connected with the FPGA unit through an EMIF, a GPIO, an SRIO and a UART bus and an external control DSP module connected with the FPGA unit through an EMIF, a GPIO and a UART bus;

the interface control unit comprises a first video coding module, a second video coding module, a first serializer/deserializer, a second serializer/deserializer, an ADC (analog-to-digital converter) module, an OC (open circuit) gate module, an RS232 bus module and an RS422 bus module; the FPGA unit is respectively connected with the input end of the first video coding module, the input end of the second video coding module, the input end of the first deserializer, the output end of the second deserializer, the output end of the ADC module, the input end of the OC door module, the RS232 bus module and the RS422 bus module;

the interface control unit also comprises a first signal conditioning unit connected with the output end of the first video coding module and a second signal conditioning unit connected with the input end of the ADC module;

the first signal conditioning unit is a differential signal amplifying circuit; the second signal conditioning unit is a circuit for converting differential signals into single ends;

the OC door module is a PWM signal driving circuit;

the clock unit is respectively connected with the FPGA unit, the peripheral control DSP module and the data processing DSP module; and the power supply management unit is respectively connected with the FPGA unit, the interface control unit and the DSP unit.

2. The FPGA and dual-DSP based digital image processing system of claim 1, wherein the FPGA unit employs an XC7K325T-2FFG900I chip and a first FLASH module, a first DDR3 module and a reset module are mounted on the XC7K325T-2FFG900I chip.

3. The digital image processing system based on the FPGA and the double-DSP as claimed in claim 2, wherein the data processing DSP module comprises a TMS320C6674 chip, and a second FLASH module, a second DDR3 module and a second reset module mounted on the TMS320C6674 chip;

the 16-bit EMIF address line interface, the UART interface, the I2C interface, the SPI interface and 16 GPIO interfaces comprising GPIO 0-GPIO 15 interfaces of the TMS320C6674 chip are respectively connected with an XC7K325T-2FFG900I chip of the FPGA unit.

4. The digital image processing system based on the FPGA and the dual-DSP as claimed in claim 2, wherein the peripheral control DSP module adopts a TMS320F28335 chip, and a third FLASH module and a third reset module are also carried on the TMS320F28335 chip;

the 16bit EMIF address line interface, the UART interface and the 16 GPIO interfaces of the TMS320F28335 chip are respectively connected with the XC7K325T-2FFG900I chip of the FPGA unit; the 16 GPIO interfaces of the TMS320F28335 chip are a GPIO0 interface, a GPIO2 interface, GPIO 12-15 interfaces, a GPIO20 interface, a GPIO21 interface, a GPIO34 interface and GPIO 48-54 interfaces respectively.

5. The digital image processing system based on FPGA and dual DSP as claimed in claim 1, wherein said first video coding module adopts ADV7391BCPZ chip to form video coding circuit; the second video coding module adopts a MAX9247 chip.

6. The digital image processing system based on FPGA and dual DSP as claimed in claim 1, wherein said first serializer deserializer and said second serializer are CML video interface circuits using TLK1501IRCP chip.

7. The FPGA and dual-DSP based digital image processing system of claim 1, wherein the OC gate module is a PWM signal driving circuit, and adopts a SNJ5407W chip.

8. The FPGA and dual-DSP based digital image processing system as recited in claim 3, wherein the second DDR3 module comprises four IS43TR16512BL-107MBLI SDRAM chips, the four IS43TR16512BL-107MBLI SDRAM chips together forming a memory expansion unit in the TMS320C6674 chip.

9. The FPGA and dual-DSP based digital image processing system of claim 2, wherein the first DDR3 module comprises an IS43TR16512BL-107MBLI SDRAM chip, and the IS43TR16512BL-107MBLI SDRAM chip of the first DDR3 module constitutes a memory expansion unit of an XC7K325T-2FFG900I chip of an FPGA unit.

10. The digital image processing system based on FPGA and dual DSP as claimed in claim 1, wherein said RS422 bus module is provided with 5-way RS422 serial port communication interface connected with FPGA unit, and RS422 interface level conversion is realized by RS-422 bus transceiver MAX3490 ESA.

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