CN207909123U - A kind of CAN bus and PCIE bus interface conversion equipments - Google Patents
A kind of CAN bus and PCIE bus interface conversion equipments Download PDFInfo
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- CN207909123U CN207909123U CN201820404032.1U CN201820404032U CN207909123U CN 207909123 U CN207909123 U CN 207909123U CN 201820404032 U CN201820404032 U CN 201820404032U CN 207909123 U CN207909123 U CN 207909123U
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Abstract
A kind of CAN bus with PCIE bus interface conversion equipments is connected and composed by PCI E control circuits, IIC control circuits, CAN control circuits；Wherein, the input terminal of the output termination IIC control circuits of PCI E control circuits；The input terminal of the output termination CAN control circuits of PCI E control circuits.A kind of CAN bus and PCIE bus interface conversion equipments have the advantages that circuit is simple, the realization of at low cost and pure hardware circuit, may be used on the field of CAN communication and PCI Express bus extensions.
Description
Technical field
The utility model belongs to interface converter technique field, and in particular to turns to a kind of CAN bus and PCIE bus interface
Changing device.
Background technology
PCI Express buses are a kind of advanced buses, and PCI Express equipment can support hot-swappable, PCI
The transmission speed of Express buses is higher, is 250MB/s~4GB/s；PCI Express buses support dual transfer mode；With
This also supports heat exchange characteristics etc. simultaneously.The advantages of by PCI Express buses, especially transmission speed, are high, and performance is stablized,
To be used widely.Common PCI Express buses are extended applied to PC machine, embedded device extension etc..
As a kind of advanced bus, CAN bus circuit relatively early CAN bus occurs, has connecting line few, stability compared with
Height, communication distance is remote, is widely used in measurement by people, control, in data transmission.Currently, realizing PCI Express buses
CAN communication device is accessed to be mainly the following：First, using PCI Express bus peripheral hardwares, single chip circuit and CAN drive
Dynamic circuit is realized；Second is that using PCI Express bus peripheral hardwares, digital signal processor circuit and CAN driving circuits come
It realizes；Third, using PCI Express bus peripheral hardwares, FPGA circuitry and CAN driving circuits are realized.However, these are realized
Method has some shortcomings：Circuit is more complicated；It needs software program to participate in, needs to control by software program；It is of high cost.
Invention content
The technical problem to be solved by the utility model is to overcome above-mentioned PCI Express bus access CAN communications to fill
The deficiency set provides a kind of CAN bus and PCIE bus interface conversion equipments.A kind of CAN bus turns with PCIE bus interface
Changing device has the advantages that circuit is simple, at low cost and pure hardware circuit is realized.
Solve the above problems the technical solution adopted is that：
The utility model uses integrated circuit U3 (CH382SSP), receives the PCI-E data sent from connector J2, warp
Integrated circuit U3 processing is crossed, and converts the PCI-E data of reception to IIC data and preserves, and the PCI-E data of reception are converted
It is exported for serial data；Using integrated circuit U5 (CSM100), U6 carries out the serial port protocol conversion process in 2 channels, by serial ports number
It is changed into CAN data, and from CAN data on connector J3, J4 outputs；Using button SW1, integrated circuit U1 (CD4051), U4,
The storage selection for carrying out IIC data selects integrated circuit U2 memories to carry out data storage when button SW1 is not press, when
When button SW1 is pressed, the memory of piece external expansion is selected to carry out data storage, data are extended from connector J1.
Description of the drawings
Fig. 1 is the electrical principle block diagram of the utility model.
Fig. 2 is the electronic circuit schematic diagram of PCI-E control circuits in Fig. 1, IIC control circuits, CAN control circuits.
Specific implementation mode
The utility model is described in further details with reference to the accompanying drawings and examples, but the utility model is not limited to this
A little embodiments.
Embodiment 1
In Fig. 1, a kind of CAN bus of the utility model and PCIE bus interface conversion equipment by PCI-E control circuits,
IIC control circuits, CAN control circuits connect and compose, wherein the input of the output termination IIC control circuits of PCI-E control circuits
End；The input terminal of the output termination CAN control circuits of PCI-E control circuits.
In fig. 2, the PCI-E control circuits of the present embodiment are by capacitance C1, C2, C3, C4, C5, no source crystal oscillator Y1, resistance
R1, R2, R3, R4, connector J2, integrated circuit U3 are connected and composed；Wherein, the model CH382SSP of integrated circuit U3, capacitance
The pin 26 of the 1 connecting connector J2 of pin of C5, connects the pin 1 of integrated circuit U3；The pin 14 of connector J2 meets integrated circuit U3
Pin 11；The pin 15 of connector J2 connects the pin 12 of integrated circuit U3；The pin of the 2 connecting connector J2 of pin of capacitance C3
21；The pin 20 of the 2 connecting connector J2 of pin of capacitance C4；The pin 24 of connector J2 connects the pin 5 of integrated circuit U3；Connector
The pin 23 of J2 connects the pin 6 of integrated circuit U3；The pin 1 of capacitance C1 connects the pin 17 of integrated circuit U3, connects the pin of Y1
1；The pin 2 of capacitance C2 connects the pin 18 of integrated circuit U3, connects the pin 2 of Y1；The pin 1 of capacitance C3 connects integrated circuit U3's
Pin 15；The pin 1 of capacitance C4 connects the pin 14 of integrated circuit U3；The pin 36 of the 17 connecting connector J2 of pin of connector J2；
The pin 31 of the 30 connecting connector J2 of pin of connector J2；The pin 1 of resistance R2 connects the pin 10 of integrated circuit U3；Resistance R3's
Pin 2 connects the pin 62 of integrated circuit U3；The pin 2 of resistance R4 connects the pin 63 of integrated circuit U3；The pin 2 of C1, C2's draws
Foot 1, the pin 2 of C5, the pin 4 of connector J2, the pin 7 of connector J2, the pin 13 of connector J2, the pin of connector J2
The pin 18 of 16, connector J2, the pin 19 of connector J2, the pin 22 of connector J2, the pin 25 of connector J2, connector
The pin 33 of J2, the pin 2 of R2, the pin 1 of R3, the pin 1 of R4, the pin 3 of integrated circuit U3, the pin 8 of integrated circuit U3,
The pin 9 of integrated circuit U3, the pin 16 of integrated circuit U3, the pin 33 of integrated circuit U3, the pin 48 of integrated circuit U3, collection
At the pin 56 of circuit U 3, the pin 61 of integrated circuit U3 is grounded；The pin 8 of connector J2, the pin 10 of connector J2, connection
The pin 27 of device J2, the pin 28 of connector J2, the pin 2 of integrated circuit U3, the pin 19 of integrated circuit U3, integrated circuit U3
Pin 49 meet 3V；The pin 4 of integrated circuit U3, the pin 7 of integrated circuit U3, the pin 13 of integrated circuit U3, integrated circuit
The pin 32 of U3, the pin 47 of integrated circuit U3 meet 1 pin 8V；The pin 1 of connector J2, the pin 2 of connector J2, connection
The pin 35 of the pin 34 of device J2, connector J2 meets+12V.
IIC control circuits are the integrated circuit U1, U2, U4 by button SW1, resistance R1, and connector J1 is connected and composed；Wherein,
The pin 1 of the model AT24C02 of the model CD4051 of integrated circuit U1, U4, integrated circuit U2, connector J1 connect integrated electricity
The pin 14 of road U1；The pin 2 of connector J1 connects the pin 14 of integrated circuit U4；The pin 2 of resistance R1 connects the pin 2 of SW1, connects
The pin 11 of integrated circuit U1 connects the pin 11 of integrated circuit U4；The pin 13 of integrated circuit U1 connects the pin of integrated circuit U2
6；The pin 5 of integrated circuit U2 connects the pin 13 of integrated circuit U4；The pin 1 of resistance R1, the pin 8 of integrated circuit U1 integrate
The pin 1 of circuit U 2, the pin 2 of integrated circuit U2, the pin 3 of integrated circuit U2, the pin 4 of integrated circuit U2, integrated circuit
The pin 7 of U2, the pin 8 of integrated circuit U4, the pin 3 of connector J1, the pin 6 of integrated circuit U1, integrated circuit U1's draws
Foot 9, the pin 10 of integrated circuit U1, the pin 6 of integrated circuit U4, the pin 9 of integrated circuit U4, the pin 10 of integrated circuit U4
Ground connection；The pin 16 of the pin 16 of integrated circuit U1, integrated circuit U4 meets 5V；The pin 1 of button SW1, integrated circuit U2's draws
Foot 8 meets 3V；The pin 7 of the pin 7 of integrated circuit U1, integrated circuit U4 meets -5V.
CAN control circuits are the integrated circuit U5 by resistance R5, R6, U6, connector J3, and J4 is connected and composed；Wherein, it integrates
The pin 1,3 of circuit U 5, the model CSM100 of U6, integrated circuit U5 meets 5V；The pin 2,6 of integrated circuit U5 is grounded；It is integrated
One end of the 7 connecting resistance R5 of pin of circuit U 5, the pin 2 of connecting connector J3；The 8 connecting resistance R5's of pin of integrated circuit U5 is another
End, the pin 1 of connecting connector J3；The pin 1,3 of integrated circuit U6 meets 5V；The pin 2,6 of integrated circuit U6 is grounded；Integrated circuit
One end of the 7 connecting resistance R6 of pin of U6, the pin 2 of connecting connector J4；The other end of the 8 connecting resistance R6 of pin of integrated circuit U6,
The pin 1 of connecting connector J4.
The operation principle of the utility model is as follows：
Work as system electrification, circuit enters working condition, when having data transmission in PCI Express buses, first, carries out
PCI Express data receivers：Data-signal is exported from the pin 14,15 of connector J2, is input to the pin of integrated circuit U3
11,12；Clock signal is exported from from the pin 23,24 of connector J2, is input to the pin 5,6 of integrated circuit U3, integrated circuit
The model CH382SSP of U3, it realizes the processing of PCI Express buses, PCI Express bus datas is changed into serial ports
Bus data, serial data are exported from the pin 53 of integrated circuit U3, are input to the pin 5 of integrated circuit U5；Serial data from
The pin 50 of integrated circuit U3 exports, and is input to the pin 5 of integrated circuit U6.
Secondly, the CAN data for carrying out 2 channels are sent：Data-signal is input to the pin 5 of integrated circuit U5, integrated circuit
The model CSM100 of U5, it is protocol processing chip, realizes serial data being changed into CAN data, by integrated circuit U5
Processing, data-signal from the pin 7,8 of integrated circuit U5 export, be input to connector J3, from connector J3 export CAN numbers
It is believed that number；Data-signal is input to the pin 5 of integrated circuit U6, and the model CSM100 of integrated circuit U6, it is protocol processes
Chip is realized serial data being changed into CAN data, and by the processing of integrated circuit U6, data-signal is from integrated circuit U6's
Pin 7,8 exports, and is input to connector J4, and CAN data-signals are exported from connector J4.
Finally, the storage of iic bus data is carried out：The processing of PCI Express buses is realized by integrated circuit U3, by PCI
Express bus datas are changed into iic bus data, and data-signal is exported from the pin 21 of integrated circuit U3, is input to integrated
Circuit U 1, the pin 3 of U4, the model CD4051 of integrated circuit U1, U4, it is analog switch chip, realizes the switching of circuit,
Its switching is controlled by button SW1, when button SW1 is not press, integrated circuit U2 memories is selected to carry out data storage, this
When, data-signal is exported from the pin 13 of integrated circuit U4, is input to the pin 5 of integrated circuit U2, the model of integrated circuit U2
For AT24C02, it is data storage, by the processing of integrated circuit U2, is stored data into address location；Work as button
When SW1 is pressed, the memory of piece external expansion is selected to carry out data storage, at this point, pin 14 of the data-signal from integrated circuit U4
Output, is input to the pin 2 of connector J1, and IIC data are exported from connector J1.
Claims (4)
1. a kind of CAN bus and PCIE bus interface conversion equipments, it is characterised in that：It is controlled with PCI-E control circuits, IIC
Circuit, CAN control circuits；Wherein, the input terminal of the output termination IIC control circuits of PCI-E control circuits；PCI-E control electricity
The input terminal of the output termination CAN control circuits on road.
2. a kind of CAN bus according to claim 1 and PCIE bus interface conversion equipments, it is characterised in that described
PCI-E control circuits, are the resistance R1, R2, R3, R4 by capacitance C1, C2, C3, C4, C5, no source crystal oscillator Y1, and connector J2 is integrated
Circuit U 3 connects and composes；Wherein, the pin of the 1 connecting connector J2 of pin of the model CH382SSP of integrated circuit U3, capacitance C5
26, connect the pin 1 of integrated circuit U3；The pin 14 of connector J2 connects the pin 11 of integrated circuit U3；The pin 15 of connector J2
Connect the pin 12 of integrated circuit U3；The pin 21 of the 2 connecting connector J2 of pin of capacitance C3；The 2 connecting connector J2 of pin of capacitance C4
Pin 20；The pin 24 of connector J2 connects the pin 5 of integrated circuit U3；The pin 23 of connector J2 connects drawing for integrated circuit U3
Foot 6；The pin 1 of capacitance C1 connects the pin 17 of integrated circuit U3, connects the pin 1 of Y1；The pin 2 of capacitance C2 meets integrated circuit U3
Pin 18, connect the pin 2 of Y1；The pin 1 of capacitance C3 connects the pin 15 of integrated circuit U3；The pin 1 of capacitance C4 connects integrated
The pin 14 of circuit U 3；The pin 36 of the 17 connecting connector J2 of pin of connector J2；The 30 connecting connector J2 of pin of connector J2
Pin 31；The pin 1 of resistance R2 connects the pin 10 of integrated circuit U3；The pin 2 of resistance R3 connects the pin 62 of integrated circuit U3；
The pin 2 of resistance R4 connects the pin 63 of integrated circuit U3；The pin 2 of C1, the pin 1 of C2, the pin 2 of C5, connector J2's draws
Foot 4, the pin 7 of connector J2, the pin 13 of connector J2, the pin 16 of connector J2, the pin 18 of connector J2, connector
The pin 19 of J2, the pin 22 of connector J2, the pin 25 of connector J2, the pin 33 of connector J2, the pin 2 of R2, R3's
Pin 1, the pin 1 of R4, the pin 3 of integrated circuit U3, the pin 8 of integrated circuit U3, the pin 9 of integrated circuit U3 integrate electricity
The pin 16 of road U3, the pin 33 of integrated circuit U3, the pin 48 of integrated circuit U3, the pin 56 of integrated circuit U3 integrate electricity
The pin 61 of road U3 is grounded；The pin 8 of connector J2, the pin 10 of connector J2, the pin 27 of connector J2, connector J2's
The pin 49 of pin 28, the pin 2 of integrated circuit U3, the pin 19 of integrated circuit U3, integrated circuit U3 meets 3V；Integrated circuit U3
Pin 4, the pin 7 of integrated circuit U3, the pin 13 of integrated circuit U3, the pin 32 of integrated circuit U3, integrated circuit U3's
Pin 47 meets 1 pin 8V；The pin 1 of connector J2, the pin 2 of connector J2, the pin 34 of connector J2, connector J2's
Pin 35 meets+12V.
3. a kind of CAN bus according to claim 1 and PCIE bus interface conversion equipments, it is characterised in that described
CAN control circuits, are the integrated circuit U5 by resistance R5, R6, U6, connector J3, and J4 is connected and composed；Wherein, integrated circuit U5,
The pin 1,3 of the model CSM100 of U6, integrated circuit U5 meet 5V；The pin 2,6 of integrated circuit U5 is grounded；Integrated circuit U5's
One end of 7 connecting resistance R5 of pin, the pin 2 of connecting connector J3；The other end of the 8 connecting resistance R5 of pin of integrated circuit U5, in succession
Connect the pin 1 of device J3；The pin 1,3 of integrated circuit U6 meets 5V；The pin 2,6 of integrated circuit U6 is grounded；Integrated circuit U6's draws
One end of 7 connecting resistance R6 of foot, the pin 2 of connecting connector J4；The other end of the 8 connecting resistance R6 of pin of integrated circuit U6, connects in succession
The pin 1 of device J4.
4. a kind of CAN bus according to claim 1 and PCIE bus interface conversion equipments, it is characterised in that described
IIC control circuits, are the integrated circuit U1, U2, U4 by button SW1, resistance R1, and connector J1 is connected and composed；Wherein, electricity is integrated
The pin 1 of the model AT24C02 of the model CD4051 of road U1, U4, integrated circuit U2, connector J1 connect integrated circuit U1's
Pin 14；The pin 2 of connector J1 connects the pin 14 of integrated circuit U4；The pin 2 of resistance R1 connects the pin 2 of SW1, connects integrated electricity
The pin 11 of road U1 connects the pin 11 of integrated circuit U4；The pin 13 of integrated circuit U1 connects the pin 6 of integrated circuit U2；It is integrated
The pin 5 of circuit U 2 connects the pin 13 of integrated circuit U4；The pin 1 of resistance R1, the pin 8 of integrated circuit U1, integrated circuit U2
Pin 1, the pin 2 of integrated circuit U2, the pin 3 of integrated circuit U2, the pin 4 of integrated circuit U2, integrated circuit U2's draws
Foot 7, the pin 8 of integrated circuit U4, the pin 3 of connector J1, the pin 6 of integrated circuit U1, the pin 9 of integrated circuit U1, collection
It is grounded at the pin 10 of the pin 10 of circuit U 1, the pin 6 of integrated circuit U4, the pin 9 of integrated circuit U4, integrated circuit U4；
The pin 16 of the pin 16 of integrated circuit U1, integrated circuit U4 meets 5V；The pin 8 of the pin 1 of button SW1, integrated circuit U2 connects
3V；The pin 7 of the pin 7 of integrated circuit U1, integrated circuit U4 meets -5V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820404032.1U CN207909123U (en) | 2018-03-24 | 2018-03-24 | A kind of CAN bus and PCIE bus interface conversion equipments |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820404032.1U CN207909123U (en) | 2018-03-24 | 2018-03-24 | A kind of CAN bus and PCIE bus interface conversion equipments |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207909123U true CN207909123U (en) | 2018-09-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820404032.1U Expired - Fee Related CN207909123U (en) | 2018-03-24 | 2018-03-24 | A kind of CAN bus and PCIE bus interface conversion equipments |
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| CN (1) | CN207909123U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109634894A (en) * | 2018-12-06 | 2019-04-16 | 英业达科技有限公司 | Data converting circuit and data transfer device |
-
2018
- 2018-03-24 CN CN201820404032.1U patent/CN207909123U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109634894A (en) * | 2018-12-06 | 2019-04-16 | 英业达科技有限公司 | Data converting circuit and data transfer device |
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| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180925 Termination date: 20190324 |
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| CF01 | Termination of patent right due to non-payment of annual fee |