CN218866471U

CN218866471U - Multifunctional chip circuit based on CPU

Info

Publication number: CN218866471U
Application number: CN202222808418.8U
Authority: CN
Inventors: 吴进智
Original assignee: Suzhou Yuankong Electronic Technology Co ltd
Current assignee: Suzhou Yuankong Electronic Technology Co ltd
Priority date: 2022-10-24
Filing date: 2022-10-24
Publication date: 2023-04-14
Anticipated expiration: 2032-10-24

Abstract

The patent of the utility model discloses a multifunctional chip circuit based on CPU, multifunctional chip circuit includes: the system comprises a domestic processor, a plurality of conversion modules and a plurality of connection modules, wherein the conversion modules are connected with the domestic processor through a first interface and connected with one connection module through a second interface; the type of the first interface is different from that of the second interface; the conversion module is used for receiving a first signal from the domestic processor through the first interface, converting the first signal into a second signal and sending the second signal to the connected connection module through the second interface, wherein the type of the first signal is different from that of the second signal; the types of the second signals supported by the second interfaces of different conversion modules are different, so that different connection devices can be accessed, different functions of the localization CPU are realized, such as display, storage, connection with peripheral equipment and the like of the localization CPU, and different requirements of users on products are met.

Description

Multifunctional chip circuit based on CPU

Technical Field

The application relates to the field of computers, in particular to a multifunctional chip circuit based on a CPU.

Background

In the field of computer modules for interactive tablets, central Processing Units (CPUs) are mostly processors produced by international INTEL (INTEL) or AMD semiconductor, usa. The processor has high function integration level and can support functions of display, network, hard disk, USB, audio, time sequence control and the like.

With the development of technology, the demand of a domestic CPU for a computer module in an interactive tablet is increasing. However, the functional integration of domestic CPUs is much lower than that of foreign CPUs. Therefore, when a domestic CPU is deployed in a computer module, it is imperative to configure a corresponding circuit to implement functions such as display, network, hard disk, USB, audio, and timing control.

SUMMERY OF THE UTILITY MODEL

The patent of the utility model provides a multifunctional chip circuit for realize a plurality of functions such as demonstration, storage, external memory hard disk and power management in the localization CPU chip circuit.

In a first aspect, a multi-function chip circuit is disclosed, the multi-function chip circuit comprising: the system comprises a domestic processor, a plurality of conversion modules and a plurality of connection modules, wherein the conversion modules are connected with the domestic processor through a first interface and connected with one connection module through a second interface; the conversion module is used for receiving a first signal from the domestic processor through the first interface, converting the first signal into a second signal and sending the second signal to the connected connection module through the second interface, wherein the type of the first signal is different from that of the second signal; the second interfaces of different conversion modules support different types of second signals.

Optionally, in a possible implementation, the first interface is a PCIe interface.

Optionally, in a possible implementation manner, the plurality of conversion modules include a first conversion module, and a second interface of the first conversion module is an HDMI interface; the first conversion module is used for converting PCIe signals received by the PCIe interface into HDMI signals and outputting the HDMI signals to the connection module through the HDMI interface.

Optionally, the first conversion module is an MXM graphics card.

In the implementation mode, the first conversion module, such as the MXM display card, is arranged between the domestic processor and the connection module, so that the connection between the domestic processor and the peripheral display equipment with the HDMI port, such as a display screen, can be realized, and the display function on the domestic CPU is realized.

Optionally, in another possible implementation manner, the plurality of conversion modules include a second conversion module, and a second interface of the second conversion module is a SATA interface; the second conversion module is used for converting the PCIe signal received by the PCIe interface into a SATA interface signal and outputting the SATA interface signal to the connection module.

Optionally, the storage unit is a SATA hard disk.

In the implementation mode, the second conversion module is arranged between the domestic processor and the connection module, and can convert signals transmitted by a PCIe interface into signals of the SATA interface, so that the function of externally connecting the SATA hard disk on the domestic CPU is realized.

Optionally, in another possible implementation manner, the plurality of conversion modules include a third conversion module, and a second interface of the third conversion module is a USB interface; the third conversion module is used for converting the PCIe signal received by the PCIe interface into a USB interface signal and outputting the USB interface signal to the connection module through the USB interface.

Optionally, the multifunctional chip circuit further includes a USB HUB module, the USB HUB module is connected to the third conversion module, and the USB HUB module includes at least one USB interface; the third conversion module is further configured to connect to at least one USB device through at least one USB interface of the USB HUB module.

In this implementation, the third conversion module is arranged between the domestic processor and the connection module, and the third conversion module can convert PCIe interface signals into signals supporting a USB interface, thereby implementing a function of connecting other USB terminal devices through the USB interface on the domestic CPU.

Optionally, in another possible implementation manner, the multifunctional chip circuit further includes a power module and a logic circuit, where the power module is connected to the domestic processor through a power supply interface, the power module is further connected to the logic circuit, and the logic circuit is configured to generate and send at least one control signal to the power module; the power module is used for receiving at least one control signal and supplying power to the domestic processor through the power supply interface.

Optionally, the logic circuit is a complex programmable logic device CPLD.

In the implementation mode, the logic circuit is arranged, and the logic circuit is used for generating a set of switch time sequence to control the power supply condition of each power module in the power module, so that the power time sequence management function on the domestic CPU is realized.

The utility model provides a pair of multifunctional chip circuit through set up a plurality of conversion modules between localization CPU and linking module, and a plurality of conversion modules possess and convert first signal into different second signals to can insert different connecting device, thereby realize localization CPU's different functions, for example including localization CPU's function such as demonstration, storage, be connected with peripheral equipment, satisfy the different demands of user to the product.

Drawings

Fig. 1 is a circuit diagram of an SOC system produced by a foreign manufacturer according to an embodiment of the present disclosure;

FIG. 2 is a block diagram of a multi-functional chip circuit according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of another circuit based on a localized CPU chip according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another circuit based on a localized CPU chip according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a circuit based on a localized CPU chip according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a circuit based on a localized CPU chip according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a circuit based on a localized CPU chip according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a circuit based on a domestic CPU chip according to an embodiment of the present disclosure.

Detailed Description

The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts belong to the protection scope of the present disclosure.

Referring to fig. 1, a circuit diagram of an SOC system manufactured by a foreign manufacturer is shown, where the SOC system (or called a system on chip) includes a plurality of functional interfaces for connecting different functional modules, such as a network unit, a storage unit, a display unit, a USB connection unit, a power management unit, and the like.

A transmission link exists between each functional unit and an interface of the SOC system, such as establishing a network link between the SOC and the network unit, establishing a storage link between the SOC and the storage unit, establishing a display link between the SOC and the display unit, establishing a USB link between the SOC and the USB connection unit, and the like.

However, the currently-made processing chip, such as a soar CPU, only supports the transmission of the High-speed Serial computer expansion Bus standard (PCIe) or the PCI-Express Bus, and does not support the connection function of other interfaces, such as a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB), a Serial Advanced Technology Attachment (SATA) Interface, and the like, so that the corresponding functions of the devices connected to the HDMI Interface, the USB Interface, and the SATA Interface cannot be realized, and the requirement of the multifunctional chip cannot be satisfied.

The technical solution of the embodiment of the present disclosure is to solve the technical problem that the CPU in the home-made chip cannot provide functions such as display, storage, external memory and hard disk, and the circuit structure provided in this embodiment is described in detail below.

Referring to fig. 2, an embodiment of the present application provides a multi-function chip circuit, including: the system comprises a domestic processor 10, a plurality of conversion modules 20 and a plurality of connection modules 30, wherein the plurality of conversion modules 20 comprise a first conversion module to an nth conversion module, similarly, the plurality of connection modules comprise a first connection module, a second connection module to an nth connection module, n is a positive integer, and n is greater than or equal to 1.

Each conversion module is connected with the domestic processor 10 through a first interface and is connected with one connection module through a second interface; the type of the first interface and the type of the second interface are different.

For example, as shown in fig. 3, the domestic processor 10 is a domestic CPU 100, the conversion module 200 includes a first interface 21 and a second interface 22, and the conversion module 200 is configured to receive a first signal from the domestic CPU 100 through the first interface 21, convert the first signal into a second signal, and send the second signal to the connected connection module 300 through the second interface 22, where the type of the first signal is different from that of the second signal.

In addition, the second interfaces of different conversion modules support different types of second signals. For example, fig. 2 includes n conversion modules corresponding to n second interfaces, and the types of the second interfaces in the n second interfaces are not completely the same. For example, if one or more of the second interfaces supports HDMI type signals, some of the second interfaces support USB or SATA signaling.

The chip circuit provided by the embodiment has the advantages that the plurality of conversion modules are arranged between the domestic CPU and the connection module, and the plurality of conversion modules are provided with the second signals for converting the first signals into the different second signals, so that different connection devices can be accessed, different functions of the domestic CPU are realized, for example, the functions of displaying, storing, connecting with peripheral equipment and the like of the domestic CPU are included, and different requirements of users on products are met.

Various embodiments of these functions are described in detail below.

In the multifunctional chip circuit, each of the plurality of conversion modules 20 includes a first interface, the first interface is a PCIe interface, each conversion module is connected to the domestic CPU 100 through the PCIe interface, and a PCIe bus is connected between the conversion module 200 and the domestic CPU 100.

Optionally, in a possible implementation, the plurality of conversion modules 20 includes a first conversion module 201, as shown in fig. 4, the first interface 21 of the first conversion module 201 is a PCIe interface, and the second interface 22 is an HDMI interface. The first conversion module 201 is configured to convert a PCIe signal received by the PCIe interface into a signal supporting HDMI transmission, and output the signal to the connection module 300 through the HDMI interface. Further, the connection module 300 is an HDMI connector 301.

Optionally, the first conversion module 201 is an MXM graphics card, and a first interface 21 of the MXM graphics card is connected to the domestic CPU 100 and supports PCIe bus transmission. The second interface 22 of the MXM video card is connected to the HDMI connector 301, and the MXM video card is used to transmit a display channel such as an HDMI signal or a DP signal back to the localization CPU 100, so as to provide a display output function for the chip circuit.

Peripheral devices such as a display screen, a smart screen, a television and the like can be connected through the HDMI connector 301.

The MXM (Mobile PCI Express Module) is a set of equipment interfaces designed for a graphic processor based on a PCI-Express interface, is positioned in different types of terminal products, is commonly established by nVidia and a plurality of notebook computer manufacturers, adopts a communication protocol compatible with the PCI-Express, and can be used for all drawing cores supporting the PCI-Express specification and chip sets supporting the PCI-Express drawing interface. In addition, the manufacturer can provide MXM display card products with different grades according to different requirements of users.

In this embodiment, the connection between the localization CPU and the HDMI connector is realized by providing the first conversion module, such as an MXM graphics card, so as to provide the localization CPU with a function of connecting devices such as a display screen, a smart screen, and a television.

In another embodiment, the plurality of conversion modules 20 includes a second conversion module 202, as shown in fig. 5, the second conversion module 202 includes a first interface 21 and a second interface 22, and the first interface 21 is a PCIe interface and the second interface 22 is a SATA interface.

The first interface 21 is configured to connect to the localization CPU 100, and receive at least one PCIe signal transmitted by the localization CPU 100; the second interface (SATA interface) is used to connect a storage unit, which may be a kind of connection module. The second conversion module 202 is configured to convert the PCIe signal received by the PCIe interface into a signal of the SATA interface, and transmit the signal to the storage unit through the SATA interface.

The storage unit is a storage medium, such as an SATA Hard Disk, and the storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, HDD), a Solid-State Drive (SSD), or the like, and the storage medium may further include a combination of the above memories.

In this embodiment, the second conversion module 202 is configured to convert the PCIe protocol into the SATA protocol, that is, convert the PCIe signal received by the first interface 21 into a SATA signal, and output the SATA signal to the SATA hard disk 302 through the second interface 22, thereby implementing a function of externally connecting the SATA hard disk to the localization CPU.

In another embodiment, as shown in fig. 6, the plurality of conversion modules 20 further includes a third conversion module 203, the first interface 21 of the third conversion module 203 is a PCIe interface, and the second interface 22 is a USB interface for connecting to the USB connector 303.

In this embodiment, the third conversion module 203 is configured to convert a PCIe signal received by the PCIe interface into a USB signal that can be transmitted by a USB, and output the USB signal to the connection module through the USB interface, so as to implement a function of connecting other USB terminal devices through the USB interface on the domestic CPU 100.

Optionally, the third conversion module 203 is connected to one or more USB terminal devices, for example, as shown in fig. 7, the circuit further includes a universal serial bus HUB (USB HUB), or USB HUB module. The USB HUB module is connected to the third conversion module 203.

The USB HUB module includes at least one USB interface, which is a device capable of extending a USB interface into multiple USB interfaces and enabling the USB interfaces to be used simultaneously, and the third converting module is connected to at least one USB device through at least one USB interface of the USB HUB module, for example, through a second interface 22 of the third converting module and the first USB connector, and through the USB HUB module and the second USB connector.

The first USB connector and the second USB connector are used for connecting other USB equipment.

In another embodiment, as shown in fig. 8, the multi-function chip circuit further includes: a power module 40 and a logic circuit 50, wherein the power module 40 includes a third interface 41 and a fourth interface 42. The power module 40 is connected with the domestic CPU 100 through a third interface 41; the power module 40 is connected to the logic circuit 50 through the fourth interface 42.

Further, the third interface 41 is a power supply interface, and the fourth interface 42 is an interface for transmitting/receiving a driving signal.

The logic circuit 50 is configured to generate and send at least one control signal to the fourth interface 42 of the power module 40, and after the power module 40 receives the at least one control signal, the power module is enabled to supply power to the domestic CPU 100 through the third interface 41.

Optionally, the power module 40 includes at least one power module, and each power module includes a third interface 41 and a fourth interface 42 for connecting the localization CPU 100 and the logic circuit 50.

The logic circuit 50 is configured to enable at least one power module in the power module 40, program timing control of the power module according to actual requirements, and send at least one control signal, such as a high level signal, to the power module 40 through at least one fourth interface 42, so as to control the power modules to be turned on. Enabling at least one power module to supply power to the domestic CPU 100 through at least one third interface 41.

Optionally, the logic circuit 50 is a Complex Programmable Logic Device (CPLD) or other modules/devices including CPLD functions, which is not limited in this embodiment.

In this embodiment, a logic circuit is provided, and a set of switch timing sequence is generated by the logic circuit to control the power supply condition of each power module in the power module, so that the localization processor chip and the Super I/O are used in a matching manner, and the power timing sequence management function on the localization CPU is realized.

The Super I/O is also called I/O chip and is responsible for providing serial and parallel interfaces, floppy disk drives, keyboard and mouse and other control interfaces.

On the hardware level, the multifunctional chip circuit provided by the embodiment can be applied to electronic equipment with localization requirements, and the electronic equipment comprises but is not limited to an intelligent interactive tablet, a mobile phone, a notebook computer, wearable equipment and the like.

Further, the electronic device may include a processor and a memory, wherein the processor and the memory are connected by a bus or other means. Further, the Processor may be a domestic CPU, or may be another general-purpose Processor, such as a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, a discrete hardware component, or a combination thereof.

The memory, which is a non-transitory computer-readable storage medium, may be used to store non-transitory software programs, non-transitory computer-executable programs, and modules.

The utility model provides a multifunctional chip circuit based on localization CPU, has solved the current mutual dull and stereotyped field of intelligence and has lacked the problem of localization module, through setting up a plurality of conversion module and a plurality of connection module, realizes localization chip CPU's multiple functions.

While various embodiments of the present disclosure have been described, it should be understood that various modifications and adaptations thereof may occur to one skilled in the art without departing from the principles of the present disclosure and are intended to be within the scope of the present disclosure.

Claims

1. A multi-function chip circuit, comprising: a domestic processor, a plurality of conversion modules and a plurality of connection modules, wherein,

the conversion module is connected with the domestic processor through a first interface and is connected with a connection module through a second interface; the type of the first interface is different from the type of the second interface;

the conversion module is used for receiving a first signal from the domestic processor through the first interface, converting the first signal into a second signal and sending the second signal to a connected connection module through the second interface, wherein the type of the first signal is different from that of the second signal; the second interface of different conversion modules supports different types of second signals.

2. The multifunction chip circuit of claim 1, wherein the first interface is a PCIe interface.

3. The multi-functional chip circuit according to claim 2, wherein the plurality of conversion modules includes a first conversion module, and a second interface of the first conversion module is an HDMI interface;

the first conversion module is used for converting PCIe signals received by the PCIe interface into HDMI signals and outputting the HDMI signals to the connection module through the HDMI interface.

4. The multifunction chip circuit of claim 2, wherein said plurality of conversion modules includes a second conversion module, a second interface of said second conversion module being a SATA interface;

the second conversion module is used for converting the PCIe signal received by the PCIe interface into a SATA interface signal and outputting the SATA interface signal to the connection module.

5. The multi-function chip circuit of claim 2, wherein the plurality of conversion modules includes a third conversion module, and the second interface of the third conversion module is a USB interface;

the third conversion module is used for converting PCIe signals received by the PCIe interface into USB interface signals and outputting the USB interface signals to the connection module.

6. The multi-function chip circuit according to claim 5, further comprising a USB HUB module, wherein the USB HUB module is connected to the third conversion module, and wherein the USB HUB module comprises at least one USB interface;

the third conversion module is further configured to connect to at least one USB device through at least one USB interface of the USB HUB module.

7. The multi-function chip circuit according to any one of claims 1 to 6, further comprising a power module and a logic circuit, wherein the power module is connected to the domestic processor through a power interface, and the power module is further connected to the logic circuit;

the logic circuit is used for generating and sending at least one control signal to the power supply module;

the power supply module is used for receiving the at least one control signal and supplying power to the domestic processor through the power supply interface.

8. The multifunction chip circuit of claim 7, wherein the logic circuit is a Complex Programmable Logic Device (CPLD).