CN214043630U - Multi-level integrated circuit composite substrate chip - Google Patents
Multi-level integrated circuit composite substrate chip Download PDFInfo
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- CN214043630U CN214043630U CN202120281391.4U CN202120281391U CN214043630U CN 214043630 U CN214043630 U CN 214043630U CN 202120281391 U CN202120281391 U CN 202120281391U CN 214043630 U CN214043630 U CN 214043630U
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- Prior art keywords
- integrated circuit
- heat dissipation
- layer
- electric
- active carbon
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- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 239000002131 composite material Substances 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 65
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 51
- 230000017525 heat dissipation Effects 0.000 claims abstract description 45
- 230000006835 compression Effects 0.000 claims abstract description 43
- 238000007906 compression Methods 0.000 claims abstract description 43
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 35
- 239000011229 interlayer Substances 0.000 claims abstract description 23
- 238000002844 melting Methods 0.000 claims description 22
- 230000008018 melting Effects 0.000 claims description 22
- 238000003466 welding Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 10
- 238000009825 accumulation Methods 0.000 abstract description 3
- 238000001816 cooling Methods 0.000 abstract description 3
- 239000012943 hotmelt Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003889 chemical engineering Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
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Abstract
The utility model discloses a multi-level integrated circuit composite substrate chip, which comprises a middle electric layer, a heat dissipation interlayer and an integrated circuit layer, wherein the middle electric layer consists of an insulating cover, a conductive tube and a conductive ring, the heat dissipation interlayer consists of an active carbon compression frame and an active carbon compression grid, the integrated circuit layer consists of an integrated circuit board and an electric connecting sheet, firstly, the heat dissipation is facilitated through the effect of a plurality of conductive tubes, the cooling effect of the middle electric layer, the heat dissipation interlayer and the integrated circuit layer is improved, in addition, the integrated circuit layer can be butted with the electric connecting sheet for facilitating the electric circulation, secondly, the matching effect of the active carbon compression frame and the active carbon compression grid is utilized for heat dissipation, the electrostatic accumulation is effectively reduced, the electric stability of the middle electric layer and the integrated circuit layer is improved, and finally, the integrated circuit layer is designed to be outmost, not only good heat dissipation also avoids with middle electric property layer direct contact, has effectively avoided electric property interference's problem.
Description
Technical Field
The utility model relates to a chip technology field especially relates to a multilayer level integrated circuit composite substrate chip.
Background
The package Substrate is Substrate (SUB for short). The substrate can provide the effects of electric connection, protection, support, heat dissipation, assembly and the like for the chip so as to realize the purposes of multi-pin, reduction of the volume of a packaged product, improvement of electric performance and heat dissipation, ultrahigh density or multi-chip modularization. The package substrate should belong to the interdisciplinary technology, and it relates to the knowledge of electronics, physics, chemical engineering, etc.
According to the above, the substrate in the prior art mostly adopts a compression integrated structure, and the structure not only has poor heat dissipation and stable influence, but also has influence on electrical performance, and simultaneously has the problems of easy generation of static accumulation and interference on normal operation of chips. Therefore, in view of the above drawbacks, it is necessary to design a multi-level integrated circuit composite substrate chip.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that will solve lies in: a multi-level integrated circuit composite substrate chip is provided to solve the problems of the background art.
In order to solve the technical problem, the technical scheme of the utility model is that: a multi-level integrated circuit composite substrate chip comprises a middle electric layer, a heat dissipation interlayer and an integrated circuit layer, wherein the middle electric layer consists of an insulating cover, a conductive tube and a conductive ring, the heat dissipation interlayer consists of an active carbon compression frame and an active carbon compression grid, the integrated circuit layer consists of an integrated circuit board and an electric connecting sheet, the heat dissipation interlayer is fixedly arranged at the upper end and the lower end of the middle electric layer, the heat dissipation interlayer and the middle electric layer are connected by hot melting, the integrated circuit layer is fixedly arranged at the upper end and the lower end of the middle electric layer, the integrated circuit layer and the middle electric layer are connected by hot melting, the integrated circuit layer and the heat dissipation interlayer are connected by hot melting, the number of the conductive tubes is a plurality of pieces, the conductive tubes are uniformly distributed in the insulating cover, the conductive tubes and the insulating cover are connected by hot melting, the conductive ring is fixedly arranged at the middle end of the outer wall of the conductive tube, conductive ring and conductive tube integrated into one piece, active carbon compression frame set firmly both ends about the insulating boot, active carbon compression frame and insulating boot adopt the hot melt to be connected, active carbon compression net set firmly inside active carbon compression frame, active carbon compression net and active carbon compression frame integrated into one piece, integrated circuit board set firmly both ends about the conductive tube outer wall, integrated circuit board and conductive tube adopt the hot melt to be connected, just integrated circuit board and active carbon compression frame adopt the hot melt to be connected, electric connection piece quantity be a plurality of, the electric connection piece set firmly on integrated circuit board, electric connection piece and integrated circuit board adopt welded connection, just electric connection piece and conductive tube adopt welded connection.
Further, the insulating boot inside still be equipped with and dodge the chamber, dodge the chamber for hollow cavity, dodge intracavity portion still set firmly a plurality of quantity's electric connecting wire, electric connecting wire and insulating boot adopt the hot melt to be connected, just electric connecting wire and conductive loop adopt welded connection, the insulating boot front end still set firmly a plurality of quantity electric connection socket, electric connection socket and insulating boot adopt the hot melt to be connected, just electric connection socket and electric connecting wire adopt the hot melt to be connected.
Furthermore, the upper end and the lower end of the outer wall of the conductive tube are fixedly provided with limiting check rings, the limiting check rings are connected with the conductive tube in a hot melting mode, and the limiting check rings are connected with the integrated circuit board in a hot melting mode.
Furthermore, a plurality of heat dissipation holes are arranged inside the active carbon compression frame and the active carbon compression grid, and the heat dissipation holes are through holes.
Further, the integrated circuit board is internally provided with a plurality of mounting holes, the mounting holes are circular through holes, and the mounting holes are connected with the conductive tubes in a tight fit manner.
Compared with the prior art, the multi-level integrated circuit composite substrate chip has the following advantages:
1. at first, through the effect of the conductive tubes of a plurality of quantities, not only do benefit to the heat dissipation, improved the cooling effect on middle electric property layer, heat dissipation interlayer and integrated circuit layer, also can dock with the electric connection piece in addition, the electric property circulation of being convenient for.
2. Secondly, by the cooperation of active carbon compression frame and active carbon compression net, not only do benefit to the heat dissipation, also effectively reduced static and piled up, improved the electric property stability of middle electric property layer and integrated circuit layer.
3. And finally, because the integrated circuit layer is designed on the outermost layer, the heat dissipation performance is good, the direct contact with the middle electric layer is also avoided, and the problem of electric interference is effectively avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a front view of a multi-level integrated circuit composite substrate chip;
FIG. 2 is a top view of a multi-level integrated circuit composite substrate chip;
FIG. 3 is a cross-sectional view of a multi-level integrated circuit composite substrate chip taken along line A;
FIG. 4 is a perspective view of a multi-level integrated circuit composite substrate chip;
FIG. 5 is a perspective view of a multi-level integrated circuit composite substrate chip in an isolated state;
FIG. 6 is an enlarged perspective view of the intermediate electrical layer;
FIG. 7 is an enlarged perspective view of the heat sink;
fig. 8 is an enlarged perspective view of an integrated circuit layer.
The heat dissipation structure comprises a middle electric layer 1, a heat dissipation interlayer 2, an integrated circuit layer 3, an insulating cover 4, a conductive tube 5, a conductive ring 6, an active carbon compression frame 7, an active carbon compression grid 8, an integrated circuit board 9, an electric connection sheet 10, an avoidance cavity 401, an electric connection line 402, an electric connection socket 403, a limit check ring 501, a heat dissipation hole 701 and a mounting hole 901.
The following detailed description will be further described in conjunction with the above-identified drawings.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the concepts underlying the described embodiments, however, it will be apparent to one skilled in the art that the described embodiments may be practiced without some or all of these specific details, and in other cases well-known process steps have not been described in detail.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
As shown in fig. 1, 2, 3, 4, 5, 6, 7, 8, a multi-level integrated circuit composite substrate chip comprises a middle electrical layer 1, a heat dissipation interlayer 2, an integrated circuit layer 3, an insulating cover 4, a conductive tube 5, a conductive ring 6, an activated carbon compression frame 7, an activated carbon compression grid 8, an integrated circuit board 9, and an electrical connection sheet 10, wherein the heat dissipation interlayer 2 is fixedly arranged at the upper and lower ends of the middle electrical layer 1, the heat dissipation interlayer 2 is connected with the middle electrical layer 1 by thermal melting, the integrated circuit layer 3 is fixedly arranged at the upper and lower ends of the middle electrical layer 1, the integrated circuit layer 3 is connected with the middle electrical layer 1 by thermal melting, the integrated circuit layer 3 is connected with the heat dissipation interlayer 2 by thermal melting, the conductive tubes 5 are a plurality of pieces, the conductive tubes 5 are uniformly distributed inside the insulating cover 4, the conductive tubes 5 are connected with the insulating cover 4 by thermal melting, the conductive ring 6 is fixedly arranged at the middle end of the outer wall of the conductive tube 5, the conductive ring 6 and the conductive tube 5 are integrally formed, the active carbon compression frame 7 is fixedly arranged at the upper end and the lower end of the insulation cover 4, the active carbon compression frame 7 is connected with the insulation cover 4 by hot melting, the active carbon compression grid 8 is fixedly arranged in the active carbon compression frame 7, the active carbon compression grid 8 and the active carbon compression frame 7 are integrally formed, the integrated circuit board 9 is fixedly arranged at the upper end and the lower end of the outer wall of the conductive tube 5, the integrated circuit board 9 is connected with the conductive tube 5 by hot melting, the integrated circuit board 9 is connected with the active carbon compression frame 7 by hot melting, the number of the electric connection sheets 10 is a plurality of pieces, the electric connecting sheet 10 is fixedly arranged on the integrated circuit board 9, the electric connecting sheet 10 is connected with the integrated circuit board 9 in a welding mode, and the electric connecting sheet 10 is connected with the conductive tube 5 in a welding mode;
the multi-level integrated circuit composite substrate chip has the following functions;
A. the conductive tubes 5 with a plurality of numbers are arranged in the middle electric layer 1, so that heat dissipation is facilitated, external air flow can conveniently pass through the conductive tubes 5 to take away heat, the cooling effect of the middle electric layer 1, the heat dissipation interlayer 2 and the integrated circuit layer 3 is improved, and in addition, the conductive tubes 5 can also be butted with the electric connection sheets 10 on the integrated circuit board 9, so that electric circulation is facilitated;
B. the heat dissipation interlayer 2 is positioned between the middle electric layer 1 and the integrated circuit layer 3, so that heat dissipation is facilitated, meanwhile, by means of the activated carbon adsorption effect of the activated carbon compression frame 7 and the activated carbon compression grids, the electrostatic accumulation is effectively reduced, and the electric stability of the middle electric layer 1 and the integrated circuit layer 3 is improved;
C. the integrated circuit layer 3 is arranged on the outermost layer, and is separated by the heat dissipation interlayer 2, so that the heat dissipation performance is good, and the problem that the integrated circuit layer is easily subjected to electrical interference due to direct contact with the intermediate electrical layer 1 is avoided;
an avoidance cavity 401 is further arranged in the insulating cover 4, the avoidance cavity 401 is a hollow cavity, a plurality of electric connecting wires 402 are fixedly arranged in the avoidance cavity 401, the electric connecting wires 402 are connected with the insulating cover 4 in a hot melting mode, the electric connecting wires 402 are connected with the conductive rings 6 in a welding mode, a plurality of electric connecting sockets 403 are fixedly arranged at the front end of the insulating cover 4, the electric connecting sockets 403 are connected with the insulating cover 4 in a hot melting mode, and the electric connecting sockets 403 are connected with the electric connecting wires 402 in a hot melting mode;
it should be noted that the avoidance cavity 401 can avoid the conductive ring 6 and the electrical connection line 402, and is also beneficial to heat dissipation inside the insulating cover 4, so that electrical stability is promoted, the electrical connection line 402 can butt the conductive ring 6 with the electrical connection socket 403, and the electrical connection socket 403 can butt with a wire socket in the prior art, so that the substrate chip is electrified and butted for use;
the upper end and the lower end of the outer wall of the conductive tube 5 are fixedly provided with limiting check rings 501, the limiting check rings 501 are connected with the conductive tube 5 in a hot melting manner, and the limiting check rings 501 are connected with the integrated circuit board 9 in a hot melting manner;
it should be noted that the limiting retainer ring 501 can limit and support the integrated circuit board 9, so that the connection effect of the integrated circuit board 9 and the conductive tube 5 is improved, and the connection firmness of the whole among the middle electrical layer 1, the heat dissipation interlayer 2 and the integrated circuit layer 3 is enhanced;
a plurality of heat dissipation holes 701 are further arranged inside the active carbon compression frame 7 and the active carbon compression grid 8, and the heat dissipation holes 701 are through holes;
it should be noted that the heat dissipation holes 701 facilitate the heat inside the active carbon compression frame 7 and the active carbon compression grid 8 to overflow, and improve the heat dissipation effect in the region between the middle electrical layer 1, the heat dissipation interlayer 2 and the integrated circuit layer 3;
a plurality of mounting holes 901 are further formed in the integrated circuit board 9, the mounting holes 901 are circular through holes, and the mounting holes 901 are connected with the conductive tubes 5 in a tight fit manner;
it should be noted that the mounting hole 901 can avoid the conductive tubes 5, so that the integrated circuit board 9 can be conveniently buckled outside a plurality of conductive tubes 5, and the smart mounting of the integrated circuit layer 3 and the middle electrical layer 1 is realized.
Claims (5)
1. A multi-level integrated circuit composite substrate chip is characterized by comprising an intermediate electric layer, a heat dissipation interlayer and an integrated circuit layer, wherein the intermediate electric layer is composed of an insulating cover, a conductive tube and a conductive ring, the heat dissipation interlayer is composed of an active carbon compression frame and an active carbon compression grid, the integrated circuit layer is composed of an integrated circuit board and an electric connecting sheet, the heat dissipation interlayer is fixedly arranged at the upper end and the lower end of the intermediate electric layer, the integrated circuit layer and the heat dissipation interlayer are connected by hot melting, the number of the conductive tubes is a plurality of pieces, the conductive tubes are uniformly distributed in the insulating cover, the conductive ring is fixedly arranged at the middle end of the outer wall of the conductive tube, the active carbon compression frame is fixedly arranged at the upper end and the lower end of the insulating cover, and the active carbon compression grid is fixedly arranged in the active carbon compression frame, the integrated circuit board is fixedly arranged at the upper end and the lower end of the outer wall of the conductive tube, the integrated circuit board is connected with the activated carbon compression frame in a hot melting mode, the number of the electric connection pieces is a plurality of pieces, the electric connection pieces are fixedly arranged on the integrated circuit board, and the electric connection pieces are connected with the conductive tube in a welding mode.
2. The multi-level integrated circuit composite substrate chip as claimed in claim 1, wherein an avoiding cavity is further disposed inside the insulating cover, a plurality of electrical connection wires are further fixedly disposed inside the avoiding cavity, the electrical connection wires and the conductive rings are connected by welding, a plurality of electrical connection sockets are further fixedly disposed at the front end of the insulating cover, and the electrical connection sockets and the electrical connection wires are connected by hot melting.
3. The multi-level integrated circuit composite substrate chip as claimed in claim 1, wherein the upper and lower ends of the outer wall of the conductive tube are further fixedly provided with a limiting retainer ring, and the limiting retainer ring is connected with the integrated circuit board by thermal melting.
4. The multi-level integrated circuit composite substrate chip of claim 1, wherein the activated carbon compression frame and the activated carbon compression grid are further provided with a plurality of heat dissipation holes therein.
5. The multi-level integrated circuit composite substrate chip of claim 1, wherein the integrated circuit board further comprises a plurality of mounting holes, and the mounting holes are tightly connected to the conductive tubes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120281391.4U CN214043630U (en) | 2021-02-01 | 2021-02-01 | Multi-level integrated circuit composite substrate chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120281391.4U CN214043630U (en) | 2021-02-01 | 2021-02-01 | Multi-level integrated circuit composite substrate chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214043630U true CN214043630U (en) | 2021-08-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120281391.4U Expired - Fee Related CN214043630U (en) | 2021-02-01 | 2021-02-01 | Multi-level integrated circuit composite substrate chip |
Country Status (1)
| Country | Link |
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| CN (1) | CN214043630U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420655A (en) * | 2022-01-19 | 2022-04-29 | 深圳市卓朗微电子有限公司 | Multi-level integrated circuit composite substrate chip |
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2021
- 2021-02-01 CN CN202120281391.4U patent/CN214043630U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420655A (en) * | 2022-01-19 | 2022-04-29 | 深圳市卓朗微电子有限公司 | Multi-level integrated circuit composite substrate chip |
| CN114420655B (en) * | 2022-01-19 | 2022-11-11 | 深圳市卓朗微电子有限公司 | Multi-level integrated circuit composite substrate chip |
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|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20210824 |
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| CF01 | Termination of patent right due to non-payment of annual fee |