CN212113686U - Packaging structure - Google Patents
Packaging structure Download PDFInfo
- Publication number
- CN212113686U CN212113686U CN202020348296.7U CN202020348296U CN212113686U CN 212113686 U CN212113686 U CN 212113686U CN 202020348296 U CN202020348296 U CN 202020348296U CN 212113686 U CN212113686 U CN 212113686U
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- China
- Prior art keywords
- chip
- silica gel
- semiconductor module
- bonding
- gel layer
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- 238000004806 packaging method and process Methods 0.000 title abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000000741 silica gel Substances 0.000 claims abstract description 25
- 229910002027 silica gel Inorganic materials 0.000 claims abstract description 25
- 239000004593 Epoxy Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 24
- 239000003822 epoxy resin Substances 0.000 claims description 21
- 229920000647 polyepoxide Polymers 0.000 claims description 21
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229920001296 polysiloxane Polymers 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 14
- 238000007711 solidification Methods 0.000 abstract description 7
- 230000008023 solidification Effects 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 5
- 230000008569 process Effects 0.000 description 10
- 239000000499 gel Substances 0.000 description 8
- 238000001721 transfer moulding Methods 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000003292 glue Substances 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 238000000465 moulding Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000000748 compression moulding Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 238000004080 punching Methods 0.000 description 3
- 229920002379 silicone rubber Polymers 0.000 description 3
- 239000004945 silicone rubber Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
Images
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to an packaging structure technical field, concretely relates to packaging structure, this packaging structure, include: the semiconductor module and the silica gel layer are packaged outside the semiconductor module; this embodiment adopts to have elastic silica gel layer after the solidification to replace prior art's epoxy plastic-sealed material to realize when ambient temperature changes, having elastic silica gel layer after the solidification can not cause the damage to the chip at expend with heat and contract with cold's in-process, finally guarantees the stability of chip performance.
Description
Technical Field
The utility model relates to an packaging structure technical field, concretely relates to packaging structure.
Background
The manufacturing process of the existing packaging structure is as follows: firstly, assembling a semiconductor module: the method comprises the steps of connecting metal wires such as aluminum wires, copper wires or gold wires to metallization layers on the surfaces of chips, pins of a substrate and the two chips in a lead bonding mode to realize electrical interconnection, and then plastically packaging the semiconductor modules by using materials such as epoxy resin on the outer sides of the semiconductor modules to protect the semiconductor modules.
However, since the thermal expansion coefficients of the epoxy resin molding compound and the chip are not matched, and the epoxy resin molding compound is rigid after being cured, the chip is damaged by the stress released by the cured epoxy resin molding compound when the external temperature changes.
SUMMERY OF THE UTILITY MODEL
An object of this application is to provide a packaging structure to when ambient temperature changes among the solution prior art, the stress of epoxy resin molding compound release after the solidification will cause the damage to the chip.
Technical scheme (I)
In order to achieve the above object, a package structure includes: the semiconductor module and encapsulate in the silica gel layer of semiconductor module outside.
Optionally, the coverage of the silica gel layer at least includes: a chip and a bonding wire of the semiconductor module.
Optionally, the outer side of the silica gel layer is further provided with an epoxy resin layer.
Optionally, the epoxy resin layer is encapsulated on the silicone layer.
Optionally, the epoxy resin layer is arranged at the edge of the substrate to form a glue blocking wall, and the silica gel layer is arranged in the glue blocking wall.
Optionally, the semiconductor module includes: the chip is welded in the middle of the substrate and electrically connected with the substrate through a bonding lead, and the lead frame is welded at the edge of the substrate.
Optionally, the number of the chips is at least two, and the at least two chips are electrically connected through bonding wires.
Optionally, the substrate is configured as a DBC substrate or an IMS substrate.
Optionally, the bonding wire is provided as a bonding alloy wire.
(II) advantageous effects
Compared with the prior art, the utility model, following beneficial effect has:
the utility model provides a packaging structure, include: the semiconductor module and the silica gel layer are packaged outside the semiconductor module; this embodiment adopts to have elastic silica gel layer after the solidification to replace prior art's epoxy plastic-sealed material to realize when ambient temperature changes, having elastic silica gel layer after the solidification can not cause the damage to the chip at expend with heat and contract with cold's in-process, finally guarantees the stability of chip performance.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained without inventive exercise, wherein:
fig. 1 is a schematic structural diagram of an embodiment of a package structure in the present invention;
FIG. 2 is a schematic diagram of steps A-D of a method of fabricating the package structure of FIG. 1;
fig. 3 is a schematic structural diagram of another embodiment of the package structure of the present invention;
fig. 4 is a schematic diagram of steps a-D of the method of manufacturing the package structure of fig. 3.
In the figure: 1. a semiconductor module; 2. a silica gel layer; 3. a chip; 4. bonding a lead; 5. an epoxy resin layer; 6. a substrate; 7. a lead frame.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
The invention will be described in further detail with reference to the following drawings and embodiments:
as shown in fig. 1, 2, 3 and 4, the present application provides a package structure including: the semiconductor module comprises a semiconductor module 1 and a silica gel layer 2 which is encapsulated outside the semiconductor module 1; preferably, the package structure of the present embodiment is a DIP IPM package structure, wherein a layer of silicone gel is formed outside the semiconductor module 1 by a hydraulic Compression molding process lcm (liquid Compression molding); this embodiment adopts to have elastic silica gel layer 2 after the solidification to replace prior art's epoxy plastic envelope material to realize when ambient temperature changes, having elastic silica gel layer 2 after the solidification can not cause the damage to chip 3 at expend with heat and contract with cold's in-process, finally guarantees the stability of 3 performances of chip.
According to the utility model discloses an embodiment, as shown in FIG. 1, in order to strengthen packaging structure's mechanical strength, the outside on silica gel layer 2 still is equipped with epoxy layer 5, and silica gel layer 2's coverage includes at least: in the embodiment, the silicon gel layer 2 is firstly arranged on the outer sides of the devices such as the chip 3 and the bonding lead 4, and then the epoxy resin layer 5 is formed on the outer side of the silicon gel layer 2, so that the semiconductor module 1 is subjected to plastic package treatment on the outer side of the silicon gel layer 2, and on one hand, the bonding lead 4, especially a bonding gold wire, can be prevented from being impacted by resin flow, and thus bad phenomena such as wire punching and the like can be avoided; on the other hand, when the external temperature changes, under the buffer action of the silica gel layer 2, the mechanical stress of the epoxy resin plastic package material on the chip 3 in the process of expansion with heat and contraction with cold is reduced, and the temperature resistance degree of the silica gel is higher.
According to an embodiment of the present invention, as shown in fig. 1, the epoxy resin layer 5 is encapsulated on the silicone rubber layer 2, and specifically, a plastic encapsulation layer of epoxy resin is formed on the outer side of the silicone rubber layer 2 by using a Transfer Molding process (Transfer Molding) on the outer side of the silicone rubber layer 2; the coverage of the silica gel layer 2 at least comprises: in the present embodiment, the silicon gel layer 2 is first disposed on the outer sides of the chip 3, the bonding wire 4, and other devices by a hydraulic compression Molding process (LCM), and then the epoxy resin layer 5 is formed on the outer layer of the silicon gel layer 2 by a Transfer Molding process (Transfer Molding), so as to mold the semiconductor module 1 on the outer side of the silicon gel layer 2.
According to an embodiment of the present invention, the semiconductor module 1 includes: the chip 3 is welded in the middle of the substrate 6, the chip 3 is electrically connected with the substrate 6 through a bonding lead 4, and the lead frame 7 is welded at the edge of the substrate 6.
According to an embodiment of the present invention, the chips 3 are arranged to be at least two, and at least two chips 3 are electrically connected through the bonding wires 4, wherein the bonding wires can be bonding aluminum wires or bonding alloy wires, the bonding aluminum wires have higher strength, but the bonding alloy wires and the bonding aluminum wires with the same length and diameter have more current carrying capacity, preferably, the bonding wires are bonding alloy wires, exemplarily, as can be seen from fig. 1 and 2A, the chips 3 are arranged to be three, the first chip 3 and the second chip 3 are electrically connected through the bonding aluminum wires from left to right, and the second chip 3 and the third chip 3 are electrically connected through the bonding gold wires; when the chips are connected through the bonding gold wire, the bonding gold wire is impacted by flowing of the straight epoxy resin, so that the phenomenon of poor line punching is stronger, and the silica gel layer and the epoxy resin layer are combined by adopting the scheme, so that the problem of line punching of the bonding gold wire between the chips is better solved.
According to an embodiment of the present invention, in order to avoid using a more complicated carrier and improve the efficiency of the bonding, it is preferable that the substrate 6 is configured as a DBC substrate or an IMS substrate and other heat dissipation substrates, so as to realize the die bonding and wire bonding in the form of a full-page multiple unit.
The manufacturing method of the present embodiment:
step 1: as shown in fig. 2A, the chip 3 is soldered on the substrate 6 and wire bonding is performed;
step 2: as shown in fig. 2B, a silicone gel layer 2 is molded on at least the outer sides of the chip 3 and the bonding wires 4 by a hydraulic Compression molding (lcm) process;
and step 3: as shown in fig. 2C, the lead frame 7 is soldered on the substrate 6, thereby completing the assembly of the semiconductor module 1;
and 4, step 4: as shown in fig. 2D, a layer of epoxy resin Molding layer is molded on the outer side of the semiconductor module 1 by Transfer Molding (Transfer Molding) process on the outer side of the silicone layer 2, and finally the package structure is prepared.
According to the utility model discloses a further embodiment, as shown in fig. 3, epoxy layer 5 sets up and forms in the edge of base plate and keep off gluey wall, silica gel layer 2 set up in keep off in the gluey wall.
The manufacturing method of the present embodiment:
step 1: as shown in fig. 4A, first, the lead frame 7 is soldered on the substrate 6;
step 2: as shown in fig. 4B, an epoxy resin layer 5 is formed at the edge of the substrate 6 by using a Transfer Molding process (Transfer Molding), the epoxy resin layer 5 serves as a glue blocking wall, and the shape of the glue blocking wall is not particularly limited as long as the glue blocking wall functions as a blocking silicone, and the specific shape is determined according to the specific Molding process, and the glue blocking wall is bowl-shaped as shown in the figure;
and step 3: as shown in fig. 4C, the chip 3 is soldered on the substrate 6 in the bowl-shaped epoxy layer 5, and wire bonding is performed;
and 4, step 4: as shown in fig. 4D, the bowl-shaped epoxy resin layer 5 is filled with the silica gel layer 2 by using a dispensing process, and at least the upper chip 3 and the bonding wire 4 are wrapped, so that the package structure is manufactured.
The embodiments in the present description are all described in a progressive manner, and some of the embodiments are mainly described as different from other embodiments, and the same and similar parts among the embodiments can be referred to each other.
In the description of the present invention, it should be noted that the terms "upper", "lower", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying importance; the words "bottom" and "top", "inner" and "outer" refer to directions toward and away from, respectively, a particular component geometry.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; the communication may be direct, indirect via an intermediate medium, or internal to both elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
The above description is only for the preferred embodiment of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.
Claims (6)
1. A package structure, comprising: the semiconductor module comprises a semiconductor module (1) and a silica gel layer (2) which is encapsulated at the outer side of the semiconductor module (1); an epoxy resin layer (5) is arranged on the outer side of the silica gel layer (2); epoxy layer (5) set up and form at the edge of base plate and keep off gluey wall, silica gel layer (2) set up in keep off in the gluey wall.
2. The encapsulation structure according to claim 1, wherein the coverage of the silicone layer (2) comprises at least: a chip (3) and a bonding wire (4) of the semiconductor module (1).
3. The package structure according to claim 1, wherein the semiconductor module (1) comprises: base plate (6), chip (3) and lead frame (7), chip (3) weld in the middle part of base plate (6), just chip (3) through bonding wire (4) with base plate (6) electric connection, lead frame (7) weld in the edge of base plate (6).
4. The package structure according to claim 3, wherein the number of the chips (3) is at least two, and at least two of the chips (3) are electrically connected by bonding wires (4).
5. The package structure according to claim 3, characterized in that the substrate (6) is provided as a DBC substrate or an IMS substrate.
6. The encapsulation structure according to claim 4, characterized in that the bonding wires (4) are provided as bonding aluminum wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020348296.7U CN212113686U (en) | 2020-03-18 | 2020-03-18 | Packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020348296.7U CN212113686U (en) | 2020-03-18 | 2020-03-18 | Packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212113686U true CN212113686U (en) | 2020-12-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020348296.7U Active CN212113686U (en) | 2020-03-18 | 2020-03-18 | Packaging structure |
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| Country | Link |
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| CN (1) | CN212113686U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111326481A (en) * | 2020-03-18 | 2020-06-23 | 珠海格力电器股份有限公司 | Packaging structure |
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2020
- 2020-03-18 CN CN202020348296.7U patent/CN212113686U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111326481A (en) * | 2020-03-18 | 2020-06-23 | 珠海格力电器股份有限公司 | Packaging structure |
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