CN210778556U

CN210778556U - Integrated circuit packaging structure

Info

Publication number: CN210778556U
Application number: CN201922342303.2U
Authority: CN
Inventors: 凌瑞林
Original assignee: Shanghai Zhiyue Automation Technology Co ltd
Current assignee: Ling Qianhe
Priority date: 2019-12-23
Filing date: 2019-12-23
Publication date: 2020-06-16
Anticipated expiration: 2029-12-23

Abstract

The application provides a packaging structure of an integrated circuit, which comprises an upper substrate 1, a lower substrate 2, an element 3 and an intermediate filling layer 21 of the integrated circuit; the upper metal layer 4 of the upper substrate 1 is a heat dissipation layer of the whole integrated circuit; the lower metal layer 5 of the upper substrate 1 is interconnected with the elements 3 and the lower substrate 2 by bonding pads 6, 7, 8; the upper substrate 1 and the lower substrate 2 are interconnected through the gold immersion 17 and 18; the upper metal layer 9 of the lower substrate 2 is interconnected with the element 3 through pads 11, 12; the upper metal layer 9 and the lower metal layer 10 of the lower substrate 2 are interconnected through the through holes 19 and 20; the bonding pads 13, 14, 15, 16 on the lower metal layer 10 of the lower substrate 2 are external bonding pads of the entire integrated circuit.

Description

Integrated circuit packaging structure

Technical Field

The present invention relates to an integrated circuit package structure, and more particularly, to a package structure for miniaturization and high power density of an integrated circuit.

Background

Integrated circuits are made smaller and smaller on the basis of satisfying moore's law. The smaller the size, the more difficult the technological advancement. The degree of intellectualization, miniaturization and power density of the equipment is higher and higher, and in order to solve the problems of miniaturization, intellectualization and ultrahigh power density of the equipment, the functions and efficiency of the tube cores with various functions are required to be improved, and the area and the volume of the tube cores are reduced; the technical requirements of miniaturization, integration, high power density and the like are also required to be completed on the aspect of packaging technology, and the problems of heat dissipation of the integrated circuit, complex production process, long production period, high production cost and the like are solved.

Many existing integrated circuit package structures continue to use conventional package methods, mount various dies by using frames, electrically connect by using wire bonding, and often use thicker bonding wires and more bonding wires when the power is higher. Such packaging methods include DIP packaging of IPM module, TO220 packaging of single MOSFET, etc., and these packaging methods are usually large in volume and are not suitable for miniaturization application. Because a plurality of bonding wires are needed, the bonding process period is long, the cost is high, and the cost performance of the whole bonding machine is low. In order to solve the problem of high power density, the QFN packaging method is often widely applied to some products requiring high power density due to the large heat sink; in the QFN package, a bonding wire is formed by a gold wire and a copper wire, and the aluminum wire turns to an aluminum sheet and a copper sheet with large current capacity, so that the contact resistance is reduced, and the parasitic parameters of the package are reduced. This is a successful package structure for miniaturized and high power density products. Likewise, BGA packages have a smaller size, better thermal and electrical performance, and shorter electrical connections, and are therefore widely used in multi-pin CPU and memory chips. On the basis, the method combines the advantages of QFN and BGA packaging, meets the requirements of large-current connection, small packaging size and a connection structure of a multilayer structure, and has the advantages of simple production process, high cost performance and higher economy.

SUMMERY OF THE UTILITY MODEL

According to one aspect of the present application, the integrated circuit package structure includes an upper substrate, a lower substrate, an intermediate filling layer, and optionally other intermediate substrate layers, wherein the components are sandwiched between the upper and lower substrates, and are directly connected to the upper and lower substrates or directly connected to other intermediate substrate layers in the intermediate filling layer. The upper substrate, the lower substrate, the components and the middle substrate are electrically and physically connected through a welding method.

According to another aspect of the present invention, an integrated circuit packaged by the integrated circuit packaging method has a distinct layered structure, an upper substrate layer, a lower substrate layer, an intermediate element layer, an intermediate substrate layer, and an intermediate filling layer, wherein the element layer or the intermediate substrate layer is further wrapped by the intermediate filling layer, and the filling layer uses a filling material to reinforce the element and the fixation of the upper substrate layer and the lower substrate layer, thereby ensuring the heat dissipation of the element, the electrical insulation, and the structural stability of the whole integrated circuit.

The upper and lower substrates are layered, as are the middle substrate layers. The designed metal layer completes the interconnection of the integrated circuit through the connection Pad, meets the requirement of high-current interconnection, meets the requirement of the shortest connection line and meets the requirement of optimal heat conduction.

The upper substrate may alternatively have only one metal layer, which is bonded to the component by a bonding Pad.

The upper substrate may optionally have only one metal layer, which is directly exposed to enhance heat conduction.

The upper substrate can optionally comprise an upper metal layer and a lower metal layer, the inner metal layer is connected with the element through a connecting Pad, and the outer metal layer is directly exposed to the outside to enhance heat conduction.

The upper substrate can optionally have multiple metal layers, except that the inner metal layer of the upper and lower metal layers is connected with the element through a connecting Pad, the outer metal layer is directly exposed to the outside to strengthen heat conduction, and one or more metal layers are arranged in the upper substrate and are subjected to gold immersion through open holes to complete complex integrated circuit interconnection.

The lower substrate is optionally provided with a metal layer, and the connection Pad on the metal layer is the connection Pad of the integrated circuit and is reserved for PCB application.

The lower substrate can optionally have multiple metal layers, and besides the outer metal layer serving as a connecting Pad of the integrated circuit, the lower substrate can also have multiple metal layers and be interconnected through open-hole gold deposition to complete complex integrated circuit interconnection.

The optional intermediate substrate optionally has all the features of the upper substrate and the lower substrate, and is bonded to the element and the other substrates by the bonding Pad.

In the embodiment of the application, the internal connecting line of the integrated circuit packaging structure is short, the flow conductivity is strong, the heat conductivity is strong, the parasitic electric parameter is small, and the requirements of miniaturization and high power density of the integrated circuit on the market can be met.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 illustrates a single chip integrated circuit package structure according to an embodiment of the present application;

fig. 2 illustrates a dual chip integrated circuit package structure according to another embodiment of the present application.

Detailed description of the invention

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The technical solution of the embodiment of the present invention is described below with reference to the drawings of the embodiment of the present application.

Fig. 1 shows a single chip integrated circuit package structure 101 according to an embodiment of the present invention, which includes an upper substrate 1, a device 3, and a lower substrate 2, upper metal layers 4, lower metal layers 5, and

bonding pads

6, 7, 8 on the lower metal layers 5 on the upper substrate 1, upper metal layers 9, lower metal layers 10, and

bonding pads

11, 12 on the upper metal layers 9, and

bonding pads

13, 14, 15, 16 on the lower metal layers 10 on the lower substrate 2. The upper substrate 1 and the lower substrate 2 are connected by

gold immersion

17, 18, the lower substrate 2 is connected by the upper metal layer 9, the lower metal layer 10 through

hole gold immersion

19, 20, the middle filling layer 21, the upper substrate 1 middle layer 22, the lower substrate 2 middle layer 23.

Fig. 2 shows a dual chip integrated circuit package 201 according to an embodiment of the present application, which includes an upper substrate 1, a component 3, a component 4, and a lower substrate 2, an upper metal layer 5, a lower metal layer 6 on the upper substrate 1, and

bonding pads

7, 8, 9, 10 on the lower metal layer 6, an upper metal layer 11, a lower metal layer 12 on the lower substrate 2, and

pads

13, 14, 15, 16 on the upper metal layer 11, and bonding

pads

17, 18, 19, 20, 21, and 22 on the lower metal layer 12.

Sinkers

23, 24 for bonding the upper substrate 1 and the lower substrate 2, upper metal layer 11 and lower metal layer 12 of the lower substrate 2, via

sinkers

25, 26, 27, 28, 29 for an intermediate filling layer, an intermediate layer 30 of the upper substrate 1, and an intermediate layer 31 of the lower substrate 2.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. The integrated circuit package structure includes element, two layers of upper and lower base boards and middle stuffing layer, and the element is connected electrically to the upper and lower base boards via welding process and the element and the connecting point between the element and the base boards are all packed tightly with the middle stuffing layer.

2. The structure of claim 1, wherein the component is a single component or a plurality of components, the components being active chips and/or passive devices.

3. A structure according to claim 1, characterized in that the Pad of the component for electrical connection is concentrated on one side of the component or distributed on both the upper and lower sides of the component.

4. The structure of claim 1, wherein the substrate is a single layer or a stack of multiple layers, the material of the substrate is organic, inorganic or composite, the single layer substrate is a single layer of metal or insulating layer, the substrate has a single layer, two layers or multiple layers of metal layers, and the two layers or multiple layers of metal layers are insulated and isolated by the material of the substrate.

5. The structure of claim 1, wherein the substrate is perforated with copper to interconnect layers of the substrate, the metal layers on the upper and lower surfaces of the substrate have pads for electrical connections, and the remaining non-electrical connections are insulated and solder-resistant.

6. The structure of claim 1, wherein the bonding Pad of the component is adapted to be interconnected with the bonding Pad on the substrate, and the bonding of the Pad on the component to the Pad on the substrate is performed by soldering.

7. The structure of claim 1, wherein the filling layer is filled with a high thermal conductivity insulating material to protect the components between the upper and lower substrate layers and the bonding pads between the components and the substrate.

8. The structure of claim 1, wherein the structure comprises an upper substrate layer and a lower substrate layer, and the number of the intermediate substrate layers in the intermediate filling layer is zero or more than 2.