CN211017066U

CN211017066U - Ultra-low parasitic inductance diode packaging body

Info

Publication number: CN211017066U
Application number: CN201922251086.6U
Authority: CN
Inventors: 罗泽伟; 孙林弟; 林旭帆
Original assignee: Zhejiang Mingde Microelectronics Co ltd
Current assignee: Zhejiang Mingde Microelectronics Co ltd
Priority date: 2019-12-16
Filing date: 2019-12-16
Publication date: 2020-07-14
Anticipated expiration: 2029-12-16

Abstract

The utility model discloses an ultra-low parasitic inductance diode packaging body, including the first metal body that has outer terminal surface casing, the second metal body that has outer terminal surface casing, diode chip and plastic-sealed body, another terminal surface and the diode chip one side of first metal end body are brazed, and another terminal surface and the another side of diode chip of second metal end body are brazed, and the first metal body, second metal body and diode chip package become one through adding the injection plastic-sealed body after the completion of brazing. The utility model discloses be used for through shortening metal body terminal length, increase metal body terminal sectional area to reduce the parasitic inductance that the encapsulation produced.

Description

Ultra-low parasitic inductance diode packaging body

Technical Field

The utility model belongs to the technical field of the electronic device encapsulation, concretely relates to ultra-low parasitic inductance diode packaging body.

Background

The diode plays an important role in the aspect of rectification switch due to the unidirectional conductive characteristic; the voltage stabilizing device has a voltage stabilizing effect in a certain current range under a reverse breakdown state. When the forward direction is biased to a certain extent, the diode starts to be conducted, and the larger the current is, the larger the voltage is, and the impedance is very low; when reverse bias is applied, the diode is not conducted, has small leakage current in a certain range, and has large impedance. The unidirectional conductivity of the diode also functions as a switch, and therefore, the diode has wide application in both rectification and switching.

The diode causes parasitic inductance during packaging due to the leads during packaging. Parasitic inductance can cause waveform oscillations during diode reverse recovery, thereby increasing electromagnetic interference and turn-off losses. The calculation formula of the circular conductor inductance is as follows:

wherein l is the length of the wire/m, d is the diameter of the wire/m, L is the parasitic inductance/H,

according to the wire inductance calculation formula, the parasitic inductance can be obviously reduced by reducing the length of the wire and increasing the area of the end face of the wire.

SUMMERY OF THE UTILITY MODEL

In view of the technical problem who exists above, the utility model is used for providing an ultra-low parasitic inductance diode packaging body for through shortening metal body terminal length, increase metal body terminal sectional area, thereby reduce the parasitic inductance of encapsulation production.

In order to solve the technical problem, the utility model discloses a following technical scheme:

the diode packaging body comprises a first metal body with an outer end face shell, a second metal body with an outer end face shell, a diode chip and a plastic packaging body, wherein the other end face of the first metal body is brazed with one face of the diode chip, the other end face of the second metal body is brazed with the other face of the diode chip, and the first metal body, the second metal body and the diode chip are packaged into a whole by adding the plastic packaging body after brazing.

Preferably, the outer end surface shell is a square outer end surface shell, and the other end surface of the first metal body is formed by extending a frustum pyramid.

Preferably, the other end surface of the second metal body is formed by extending a prism.

Preferably, the inner surface area of the square outer shell of the first metal body and the second metal body is larger than the area of the frustum pyramid, so that the channel structure is formed at the contact part of the square outer shell and the frustum pyramid.

In another application embodiment, the outer end surface shell is a square outer end surface shell, and the other end surface of the first metal body is formed by extending a circular truncated cone.

Preferably, the other end surface of the second metal body is formed by extending a circular truncated cone.

Preferably, the inner surface area of the square outer end face shell of the first metal body and the square outer end face shell of the second metal body are larger than the area of the circular truncated cone, so that a channel structure is formed at the contact part of the square outer shell and the circular truncated cone.

Adopt the utility model discloses following beneficial effect has:

(1) since the length of the lead from the diode chip to the outside is shortened and the diameter of the lead is increased, parasitic inductance is reduced at the root of the diode package.

(2) The tin climbing area is increased by welding the side face of the metal terminal with the PCB, and the connection is more reliable.

Drawings

Fig. 1 is a schematic structural diagram of an ultra-low parasitic inductance diode package according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an ultra-low parasitic inductance diode package according to an embodiment of the present invention at another angle;

fig. 3 is a schematic structural diagram of the ultra-low parasitic inductance diode package after plastic package according to the embodiment of the present invention;

fig. 4 is a schematic side view perspective structure view of a metal body of an ultra-low parasitic inductance diode package according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of an ultra-low parasitic inductance diode package according to another embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1 to 4, it is shown that the ultra-low parasitic inductance diode package according to an embodiment of the present invention includes a first metal body 101 having a square outer end face housing, a second metal body 102 having a square outer end face housing, a diode chip 103 and a plastic package body, wherein another end face of the first metal body is soldered to one side of the diode chip, another end face of the second metal body is soldered to another side of the diode chip, and the first metal body, the second metal body and the diode chip are packaged into a whole by injecting the plastic package body after the soldering is completed, which is shown in fig. 3 as a rectangular column. Wherein the other end surface of the first metal body 101 is formed by extending a prism table. The other end surface of the second metal body 102 is formed by extending a prism. Through the packaging structure, the sectional area of the frustum pyramid is large, the lead between the packaging pins, namely the frustum pyramid, is as short as possible, and parasitic inductance generated by diode packaging is greatly reduced.

In a specific application example, in order to increase the contact area between the metal body and the plastic package sealant and prevent water vapor from permeating, the inner surface area of the square outer shell of the first metal body and the second metal body is larger than the area of the frustum pyramid, so that the channel structure 1021 is formed at the contact part of the square outer shell and the frustum pyramid. The channel structure makes in the plastic envelope in-process, and the combination that the plastic envelope glue can be more firm with the metal physical stamina, and can prevent that steam from deepening to the chip.

In another embodiment of the present invention, referring to fig. 5, a schematic structural diagram of an ultra-low parasitic inductance diode package includes a first metal body 101 having a square outer end face housing, a second metal body 102 having a square outer end face housing, a diode chip 103, and a plastic package body, wherein another end face of the first metal body is soldered to one side of the diode chip, another end face of the second metal body is soldered to another side of the diode chip, and the first metal body, the second metal body, and the diode chip are packaged into a whole by adding the plastic package body after the soldering is completed. The other end surface of the first metal body 101 is formed by extending a circular truncated cone. The other end surface of the second metal body 102 is formed by extending a circular truncated cone.

It will be appreciated by those skilled in the art that the outer end face housing may be of other shapes that are readily solderable to the PCB.

It is to be understood that the exemplary embodiments described herein are illustrative and not restrictive. While one or more embodiments of the present invention have been illustrated in the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. The diode packaging body is characterized by comprising a first metal body with an outer end face shell, a second metal body with an outer end face shell, a diode chip and a plastic packaging body, wherein the other end face of the first metal body is brazed with one face of the diode chip, the other end face of the second metal body is brazed with the other face of the diode chip, and the first metal body, the second metal body and the diode chip are packaged into a whole by adding the plastic packaging body after the brazing is finished.

2. The ultra-low parasitic inductance diode package of claim 1, wherein the outer end face housing is a square outer end face housing, and the other end face of the first metal body is extended by a frustum of a pyramid.

3. The ultra-low parasitic inductance diode package of claim 1 or 2, wherein the other end face of the second metal body is formed by extending through a frustum of a prism.

4. The ultra-low parasitic inductance diode package of claim 3, wherein the inner surface area of the square outer casing of the first metal body and the second metal body is larger than the bottom area of the frustum pyramid, so that the channel structure is formed between the square outer casing and the frustum pyramid contact part.

5. The ultra-low parasitic inductance diode package of claim 1, wherein the outer end face housing is a square outer end face housing, and the other end face of the first metal body is formed by extending through a circular truncated cone.

6. The ultra-low parasitic inductance diode package of claim 1 or 5, wherein the other end face of the second metal body is formed by extending through a circular truncated cone.

7. The ultra-low parasitic inductance diode package of claim 6, wherein the inner surface area of the square outer end face housing of the first metal body and the second metal body is larger than the area of the circular truncated cone, so that the contact portion of the square outer housing and the circular truncated cone forms a channel structure.