CN212782904U - Simplified patch type piezoresistor - Google Patents
Simplified patch type piezoresistor Download PDFInfo
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- CN212782904U CN212782904U CN202022130217.8U CN202022130217U CN212782904U CN 212782904 U CN212782904 U CN 212782904U CN 202022130217 U CN202022130217 U CN 202022130217U CN 212782904 U CN212782904 U CN 212782904U
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Abstract
The utility model discloses a simplified patch type piezoresistor, which comprises a piezoresistor chip and a sheet metal terminal; the piezoresistor chip comprises a first electrode surface and a second electrode surface, the first electrode surface and the second electrode surface are arranged in an up-down symmetrical structure, at least part of the first electrode surface is coated with a first insulating layer, and the part of the first electrode surface which is not coated with the first insulating layer forms a terminal connecting part; one end of the sheet metal terminal is welded on the terminal connecting part; the second electrode surface is at least partially coated with a second insulating layer, and the part of the second electrode surface, which is not coated with the second insulating layer, forms a circuit board connecting part. The utility model discloses do not need the pressure injection manufacturing process to make, simplified production technology and saved manufacturing cost. When the chip type metal terminal is used, the other end of the chip type metal terminal and the second electrode surface of the piezoresistor chip are welded on a circuit board, so that the chip type metal terminal can work, and the chip type metal terminal is convenient to use.
Description
Technical Field
The utility model relates to an electronic components field, the more specifically paster type piezoresistor of simplified type that says so.
Background
The varistor is an overvoltage protection type electronic component, which is connected in parallel with a protected device to absorb surge voltage suddenly appearing in a circuit. The piezoresistors commonly used at present are mainly of the plug-in type. There are two types of chip type piezoresistors at present: a first multilayer chip type chip varistor; the second one is a plastic package type patch varistor which is injection-molded and packaged by a plug-in varistor chip and a chip metal terminal. The first one has low working current and small through current due to size limitation, and mainly plays a role in protecting a semiconductor device for electrostatic protection and a low-voltage circuit; and the second method adopts the pressure injection process, so the manufacturing cost is higher and the market popularization difficulty is high.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome prior art's not enough, provide a paster type piezoresistor of simplified type.
In order to achieve the above purpose, the utility model adopts the following technical scheme: a simplified patch type piezoresistor comprises a piezoresistor chip and a sheet type metal terminal; the piezoresistor chip comprises a first electrode surface and a second electrode surface, wherein the first electrode surface and the second electrode surface are arranged in an up-down symmetrical structure, at least part of the first electrode surface is coated with a first insulating layer, and the part of the first electrode surface, which is not coated with the first insulating layer, forms a terminal connecting part; one end of the sheet metal terminal is welded on the terminal connecting part; and at least part of the second electrode surface is coated with a second insulating layer, and the part of the second electrode surface, which is not coated with the second insulating layer, forms a circuit board connecting part.
The further technical scheme is as follows: the piezoresistor chip has a circular cross-section.
The further technical scheme is as follows: the terminal connecting portion is located at the center of the first electrode face.
The further technical scheme is as follows: the diameter of the terminal connecting part is more than 2 mm.
The further technical scheme is as follows: the circuit board connecting part is positioned in the center of the second electrode surface.
The further technical scheme is as follows: the sheet metal terminal comprises a first welding part, a second welding part and a connecting part; the first welding part and the second welding part are connected through the connecting part, the first welding part is used for being welded with the terminal connecting part, and the second welding part is used for being welded with the circuit board.
The further technical scheme is as follows: the first welding part is arranged in parallel relative to the piezoresistor chip, the connecting part is arranged in an inclined way relative to the piezoresistor chip, and the second welding part is parallel to the first welding part.
The further technical scheme is as follows: the included angle between the first welding part and the connecting part is 115-140 degrees.
The further technical scheme is as follows: the included angle between the first welding part and the connecting part is 135 degrees.
Compared with the prior art, the utility model beneficial effect be: the utility model discloses only need weld the one end of the good piece formula metal terminal of shaping on the first electrode face of piezoresistor chip, just so constituted the paster piezoresistor of simplified type, do not need the pressure to annotate manufacturing process and make, simplified production technology and saved manufacturing cost. When the chip type metal terminal is used, the other end of the chip type metal terminal and the second electrode surface of the piezoresistor chip are welded on a circuit board, so that the chip type metal terminal can work, and the chip type metal terminal is convenient to use.
The foregoing is a summary of the present invention, and other objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments, which is provided for the purpose of illustration and understanding of the present invention.
Drawings
Fig. 1 is a cross-sectional view of a simplified embodiment of a chip varistor in accordance with the present invention;
fig. 2 is a schematic structural diagram of a simplified embodiment of a patch type varistor of the present invention.
Reference numerals
1. A varistor chip; 11. a first electrode face; 12. a second electrode face; 13. a first insulating layer; 14. a second insulating layer; 2. a sheet metal terminal; 21. a first weld; 22. a connecting portion; 23. a second weld.
Detailed Description
In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further described and illustrated with reference to the following specific embodiments, but not limited thereto.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and to simplify the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "secured" are to be construed broadly and can, for example, be connected or detachably connected or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact between the first and second features, or may comprise contact between the first and second features not directly. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," some embodiments, "" an example, "" a specific example, "" or "some examples," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above should not be understood to necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by one skilled in the art.
Referring to fig. 1 and 2, the present invention provides a simplified chip type varistor, which includes a varistor chip 1 and a chip type metal terminal 2; the piezoresistor chip 1 comprises a first electrode surface 11 and a second electrode surface 12, wherein the first electrode surface 11 and the second electrode surface 12 are arranged in a vertical symmetrical structure, at least part of the first electrode surface 11 is coated with a first insulating layer 13, and the part of the first electrode surface 11 which is not coated with the first insulating layer 13 forms a terminal connecting part 22; one end of the sheet-type metal terminal 2 is welded to the terminal connecting portion 22; the second electrode surface 12 is at least partially coated with the second insulating layer 14, and a portion of the second electrode surface 12 not coated with the second insulating layer 14 constitutes a circuit board connection portion 22. The first insulating layer 13 and the second insulating layer 14 are made of epoxy resin.
The utility model discloses only need weld the one end of the good piece formula metal terminal 2 of shaping on the first electrode face 11 of piezoresistor chip 1, just so constituted the paster piezoresistor of simplified type, do not need the pressure to annotate manufacturing process and make, simplified production technology and saved manufacturing cost. When in use, the second welding part 23 of the sheet metal terminal 2 and the second electrode surface 12 of the piezoresistor chip 1 are welded on the circuit board, so that the operation can be carried out, and the use is convenient.
In the present embodiment, the cross section of the varistor chip 1 is circular. The terminal connecting portion 22 is located at the center of the first electrode face 11; the terminal connecting portion 22 has a diameter of 2 mm. The circuit board connection part 22 is located at the center of the second electrode face 12. In other embodiments, the varistor chip 1 may have other shapes, for example, rectangular or square.
Further, the sheet metal terminal 2 includes a first welding portion 21, a second welding portion 23, and a connecting portion 22; the first solder part 21 and the second solder part 23 are connected by the connecting part 22, the first solder part 21 is used for soldering with the terminal connecting part 22, and the second solder part 23 is used for soldering with the circuit board.
In the present embodiment, the first bonding portion 21 is disposed in parallel with the varistor chip 1, the connecting portion 22 is disposed in an inclined manner with respect to the varistor chip 1, and the second bonding portion 23 is disposed in parallel with the first bonding portion 21. The angle between the first welding portion 21 and the connection portion 22 is 135 °.
The technical content of the present invention is further described by the embodiments only, so that the reader can understand it more easily, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation according to the present invention is protected by the present invention. The protection scope of the present invention is subject to the claims.
Claims (9)
1. A simplified patch type piezoresistor is characterized by comprising a piezoresistor chip and a sheet type metal terminal; the piezoresistor chip comprises a first electrode surface and a second electrode surface, wherein the first electrode surface and the second electrode surface are arranged in an up-down symmetrical structure, at least part of the first electrode surface is coated with a first insulating layer, and the part of the first electrode surface, which is not coated with the first insulating layer, forms a terminal connecting part; one end of the sheet metal terminal is welded on the terminal connecting part; and at least part of the second electrode surface is coated with a second insulating layer, and the part of the second electrode surface, which is not coated with the second insulating layer, forms a circuit board connecting part.
2. A simplified chip varistor as claimed in claim 1, wherein said varistor chip has a circular cross-section.
3. A simplified patch-type varistor according to claim 2, wherein said terminal connecting portion is located at the center of said first electrode surface.
4. A simplified patch-type varistor according to claim 2, wherein said terminal connecting portion has a diameter of 2mm or more.
5. A simplified patch-type varistor according to claim 2, wherein said circuit board connection portion is located in the center of said second electrode surface.
6. A simplified chip varistor according to claim 1, wherein said chip metal terminals comprise a first soldering portion, a second soldering portion and a connecting portion; the first welding part and the second welding part are connected through the connecting part, the first welding part is used for being welded with the terminal connecting part, and the second welding part is used for being welded with the circuit board.
7. A simplified chip varistor according to claim 6, wherein said first bonding portion is parallel to said varistor chip, said connecting portion is inclined with respect to said varistor chip, and said second bonding portion is parallel to said first bonding portion.
8. A simplified patch type varistor according to claim 7, wherein said first soldering portion and said connecting portion have an included angle of 115 ° to 140 °.
9. A simplified chip varistor according to claim 8, wherein said first bond and said connection are at an angle of 135 °.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022130217.8U CN212782904U (en) | 2020-09-24 | 2020-09-24 | Simplified patch type piezoresistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022130217.8U CN212782904U (en) | 2020-09-24 | 2020-09-24 | Simplified patch type piezoresistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212782904U true CN212782904U (en) | 2021-03-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022130217.8U Active CN212782904U (en) | 2020-09-24 | 2020-09-24 | Simplified patch type piezoresistor |
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| Country | Link |
|---|---|
| CN (1) | CN212782904U (en) |
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- 2020-09-24 CN CN202022130217.8U patent/CN212782904U/en active Active
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