CN210926014U - 一种半导体芯片的sip封装结构 - Google Patents

一种半导体芯片的sip封装结构 Download PDF

Info

Publication number
CN210926014U
CN210926014U CN201922446603.5U CN201922446603U CN210926014U CN 210926014 U CN210926014 U CN 210926014U CN 201922446603 U CN201922446603 U CN 201922446603U CN 210926014 U CN210926014 U CN 210926014U
Authority
CN
China
Prior art keywords
semiconductor chip
copper
copper foil
package structure
sip package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201922446603.5U
Other languages
English (en)
Inventor
邓明
潘丽
王玲
陈智彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AKM Electronics Industrial (PanYu) Ltd
Original Assignee
AKM Electronics Industrial (PanYu) Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AKM Electronics Industrial (PanYu) Ltd filed Critical AKM Electronics Industrial (PanYu) Ltd
Priority to CN201922446603.5U priority Critical patent/CN210926014U/zh
Application granted granted Critical
Publication of CN210926014U publication Critical patent/CN210926014U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本实用新型公开了一种半导体芯片的sip封装结构，包括：第一铜箔；半导体芯片，通过导电胶贴装在第一铜箔上；介质层以及设置在介质层上的第二铜箔，层压在半导体芯片上以形成双面覆铜线路板；第一铜箔和第二铜箔上均设置有图形线路；设置在双面覆铜线路板上的镀铜孔，半导体芯片的电极通过镀铜孔电连接至图形线路；控制芯片，贴装在第二铜箔远离半导体芯片的一侧，控制芯片以金属键合的方式连接至第二铜箔上的图形线路；塑封层，设置在控制芯片上。本实用新型通过改变半导体芯片的封装方式为埋入式封装，从而将金属键合的导电方式变更成铜柱接触的导电方式，可以有效降低封装的内阻，并通过层压制作成SIP模组，从而实现阻值和空间的同时减小。

Description

一种半导体芯片的sip封装结构
技术领域
本实用新型涉及SIP封装领域，尤其涉及一种半导体芯片的sip封装结构。
背景技术
SIP封装将多个具有不同功能的有源电子元件与可选无源器件，以及诸如MEMS或者光学器件等其他器件优先组装到一起，实现一定功能的单个标准封装件，从而形成一个系统或者子系统。随着手机快充技术的发展，电子产品对功率器件模组的内阻值的要求越来越高，功率芯片的内阻已经可以降低到1-3mΩ,降低封装的内阻已经迫在眉睫。
但目前常规的半导体功率器件芯片的封装一般采用金属键合的方式，这种方式封装而成封装结构内阻较大，且体积较大，难以适应现在的技术潮流。
发明内容
本实用新型的目的在于，针对上述问题，提供一种半导体芯片的sip封装结构，将金属键合的导电方式变更成铜柱接触的导电方式，可以有效降低封装的内阻，并通过层压制作成SIP模组，从而实现阻值和空间的同时减小。
为解决上述技术问题，本实用新型基于以下技术方案进行实施：
一种半导体芯片的sip封装结构，包括：第一铜箔；半导体芯片，通过导电胶贴装在所述第一铜箔上；介质层以及设置在所述介质层上的第二铜箔，层压在所述半导体芯片上以形成双面覆铜线路板；所述第一铜箔和第二铜箔上均设置有图形线路；设置在所述双面覆铜线路板上的镀铜孔，所述半导体芯片的电极通过所述镀铜孔电连接至所述图形线路；控制芯片，贴装在所述第二铜箔远离所述半导体芯片的一侧，所述控制芯片以金属键合的方式连接至所述第二铜箔上的图形线路；塑封层，设置在所述控制芯片上。
进一步的，所述控制芯片的电极通过金属引线键合至所述第二铜箔上的图形线路。
进一步的，所述双面覆铜线路板的板厚和所述镀铜孔的孔径的比值小于或等于1。
进一步的，所述第二铜箔上还设置有阻焊层。
进一步的，所述介质层为半固化片。
进一步的，所述导电胶为塞孔树脂、导电银胶或焊锡膏。
进一步的，所述阻焊层为阻焊油墨。
进一步的，所述镀铜孔的打孔方式为机械钻孔或激光钻孔。
进一步的，所述镀铜孔的镀铜方式为化学镀铜或电镀铜。
进一步的，所述第二铜箔上设置有加厚电镀层。
与现有技术相比，本实用新型的有益效果是：
本实用新型公开了一种半导体芯片的sip封装结构，通过改变半导体芯片的封装方式为埋入式封装，从而将金属键合的导电方式变更成铜柱接触的导电方式，可以有效降低封装的内阻，并通过层压制作成SIP模组，从而实现阻值和空间的同时减小。
附图说明
图1是本实用新型实施例中所述的一种半导体芯片的sip封装结构的剖面结构示意图。
图中：
101-控制芯片；1011-金属引线；102-第二铜箔；103-半导体芯片；104-导电胶；105-塑封层；106-介质层；107-镀铜孔；108，109-图形线路；110-阻焊油墨；111-第一铜箔。
具体实施方式
在下面的描述中阐述了很多具体细节以便于充分理解本实用新型。但是本实用新型能够以很多不同于此描述的其他方式来实施，本领域技术人员可以在不违背本实用新型内涵的情况下做类似推广，因此本实用新型不受下面公开的具体实施例的限制。
下面结合具体实施例和附图对本实用新型的技术方案进行清楚、完整的描述。
如图1所示，本实施例公开了一种半导体芯片的sip封装结构，包括第一铜箔111、半导体芯片103、导电胶104、介质层106、第二铜箔102、控制芯片101和塑封层105。
具体的，半导体芯片103，通过导电胶104贴装在第一铜箔111上。具体的，导电胶104为塞孔树脂、导电银胶或焊锡膏。
具体的，介质层106以及设置在介质层106上的第二铜箔102层压在半导体芯片103上以形成双面覆铜线路板。具体的，第一铜箔111上设置有图形线路109，第二铜箔102上设置有图形线路108.
具体的，镀铜孔107设置在双面覆铜线路板，具体的，镀铜孔107设置在所述半导体芯片103与第一铜箔111和第二铜箔哦102之间，半导体芯片103的三极通过镀铜孔107电连接至图形线路108或图形线路109。具体的，介质层106为半固化片。
具体的，镀铜孔107的打孔方式为机械钻孔或激光钻孔。具体的，镀铜孔107的镀铜方式为化学镀铜或电镀铜。具体的，第二铜箔102上通过对镀铜孔107进行加厚电镀以形成加厚电镀层，从而可以满足大电流的通过要求。具体的，第二铜箔102上还设置有阻焊油墨110。
具体的，双面覆铜线路板的板厚和镀铜孔107的孔径的比值小于或等于1。通过这样设置，镀铜孔电镀时的电势分布比较均匀，孔中离子扩散度比较好，电镀液的深镀能力比较高。
具体的，控制芯片101贴装在第二铜箔102远离半导体芯片103的一侧，控制芯片101以金属键合的方式连接至第二铜箔102上的图形线路108，具体的，塑封层105设置在控制芯片101上并加热完成封装。具体的，控制芯片101的电极通过金属引线1011键合至第二铜箔102上的图形线路108。
本实施例公开的半导体芯片的sip封装结构，通过改变半导体芯片的封装方式为埋入式封装，从而将金属键合的导电方式变更成铜柱接触的导电方式，可以有效降低封装的内阻，并通过层压制作成SIP模组，从而实现阻值和空间的同时减小。
以上，仅是本实用新型的较佳实施例而已，并非对本实用新型做任何形式上的限制，故凡未脱离本实用新型技术方案的内容，依据本实用新型的技术实质对以上实施例所做的任何简单修改、等同变化与修饰，均仍属于本实用新型技术方案的范围内。

Claims (10)

1.一种半导体芯片的sip封装结构，其特征在于，包括：
第一铜箔；
半导体芯片，通过导电胶贴装在所述第一铜箔上；
介质层以及设置在所述介质层上的第二铜箔，层压在所述半导体芯片上以形成双面覆铜线路板；所述第一铜箔和第二铜箔上均设置有图形线路；
设置在所述双面覆铜线路板上的镀铜孔，所述半导体芯片的电极通过所述镀铜孔电连接至所述图形线路；
控制芯片，贴装在所述第二铜箔远离所述半导体芯片的一侧，所述控制芯片以金属键合的方式连接至所述第二铜箔上的图形线路；
塑封层，设置在所述控制芯片上。
2.根据权利要求1所述的半导体芯片的sip封装结构，其特征在于，所述控制芯片的电极通过金属引线键合至所述第二铜箔上的图形线路。
3.根据权利要求1所述的半导体芯片的sip封装结构，其特征在于，所述双面覆铜线路板的板厚和所述镀铜孔的孔径的比值小于或等于1。
4.根据权利要求1所述的半导体芯片的sip封装结构，其特征在于，所述第二铜箔上还设置有阻焊层。
5.根据权利要求1所述的半导体芯片的sip封装结构，其特征在于，所述介质层为半固化片。
6.根据权利要求1所述的半导体芯片的sip封装结构，其特征在于，所述导电胶为塞孔树脂、导电银胶或焊锡膏。
7.根据权利要求4所述的半导体芯片的sip封装结构，其特征在于，所述阻焊层为阻焊油墨。
8.根据权利要求1所述的半导体芯片的sip封装结构，其特征在于，所述镀铜孔的打孔方式为机械钻孔或激光钻孔。
9.根据权利要求1所述的半导体芯片的sip封装结构，其特征在于，所述镀铜孔的镀铜方式为化学镀铜或电镀铜。
10.根据权利要求1所述的半导体芯片的sip封装结构，其特征在于，所述第二铜箔上设置有加厚电镀层。
CN201922446603.5U 2019-12-27 2019-12-27 一种半导体芯片的sip封装结构 Active CN210926014U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201922446603.5U CN210926014U (zh) 2019-12-27 2019-12-27 一种半导体芯片的sip封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201922446603.5U CN210926014U (zh) 2019-12-27 2019-12-27 一种半导体芯片的sip封装结构

Publications (1)

Publication Number Publication Date
CN210926014U true CN210926014U (zh) 2020-07-03

Family

ID=71369017

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201922446603.5U Active CN210926014U (zh) 2019-12-27 2019-12-27 一种半导体芯片的sip封装结构

Country Status (1)

Country Link
CN (1) CN210926014U (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112967932A (zh) * 2021-02-03 2021-06-15 复旦大学 一种板级GaN半桥功率器件及其制备方法
CN113140538A (zh) * 2021-04-21 2021-07-20 上海闻泰信息技术有限公司 转接板、封装结构及转接板的制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112967932A (zh) * 2021-02-03 2021-06-15 复旦大学 一种板级GaN半桥功率器件及其制备方法
CN113140538A (zh) * 2021-04-21 2021-07-20 上海闻泰信息技术有限公司 转接板、封装结构及转接板的制作方法

Similar Documents

Publication Publication Date Title
TW200704307A (en) Circuit board with a through hole wire, and forming method thereof
CN210926014U (zh) 一种半导体芯片的sip封装结构
CN103594386A (zh) 层叠封装结构及其制作方法
CN103871996A (zh) 封装结构及其制作方法
US20010040239A1 (en) Chip-type semiconductor light-emitting device
CN109587928A (zh) 印刷电路板
CN105210462A (zh) 元器件内置基板的制造方法及元器件内置基板
CN108601203B (zh) 一种pcb及pcba
WO2019227956A1 (zh) 一种无线传输模组及制造方法
KR20190115911A (ko) 인쇄회로기판 및 인쇄회로기판 스트립
CN103929895A (zh) 具有内埋元件的电路板、其制作方法及封装结构
KR20230066541A (ko) 회로기판
US20120032301A1 (en) Semiconductor device
KR101124784B1 (ko) 배선 기판 및 그 제조 방법
CN103681359A (zh) 层叠封装结构及其制作方法
KR101034089B1 (ko) 배선 기판 및 그 제조 방법
JP4814129B2 (ja) 部品内蔵配線基板、配線基板内蔵用部品
CN214477428U (zh) 一种无引线框架的嵌入式ipm封装结构
JP4985136B2 (ja) 固体電解コンデンサ、固体電解コンデンサ内蔵基板およびそれらの製造方法
CN214068695U (zh) 一种2.5d封装结构及电子设备
CN106408070B (zh) 接触式智能卡及制造方法
CN216217701U (zh) 一种高硬度防断裂的大功率电路板
CN114496808B (zh) 倒装式塑封的装配方法、屏蔽系统、散热系统及应用
JP2011176067A (ja) 固体電解コンデンサ
CN220692001U (zh) 混合式内埋半导体封装结构

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant