CN209374443U - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

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CN209374443U
CN209374443U CN201822239380.0U CN201822239380U CN209374443U CN 209374443 U CN209374443 U CN 209374443U CN 201822239380 U CN201822239380 U CN 201822239380U CN 209374443 U CN209374443 U CN 209374443U
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chip
layer
encapsulated layer
face
conductive column
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孙鹏
任玉龙
刘军
吕书臣
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National Center for Advanced Packaging Co Ltd
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Abstract

本实用新型公开了一种芯片封装结构和封装方法，包括：底面相对贴合的第一芯片和第二芯片；多个导电柱，分布在第一芯片周围；引线，连接在第二芯片正面和金属端子的第一面之间；封装层，包封第一芯片、第二芯片、引线、导电柱，具有第一表面及与第一表面相对立的第二表面，第一表面暴露第一芯片的正面和导电柱的第二面，第二表面暴露第二芯片正面的预设区域；引出层，设置在封装层的第一表面上，分别与导电柱的第一面和/或第一芯片的正面电连接。堆叠的芯片之间连接，无需设置基板进行转接，其中上层芯片通过引线与导电柱将焊盘引出，可以满足堆叠芯片引脚的扇出，在封装层上形成暴露第二芯片正面的预设区域，较好的满足特定芯片的应用。

Description

芯片封装结构
技术领域
本实用新型涉及半导体封装技术领域，具体涉及一种芯片封装结构。
背景技术
随着半导体工业的发展，出于对更低成本、更高性能、更大集成电路密度的持续需求，叠层封装(Package on Package，POP)技术已经越来越普及；尤其随着移动通讯设备的兴起，片上系统(SoC)技术与存储器技术的集成更几乎成为高端产品的标配。
目前，POP通常采用上下两层封装叠加而成，封装内芯片通过金线键合底层封装体到基板上，同样的，上层封装中的芯片通过金线再将两个封装层之间的基板键合,然后整个封装成一个整体的封装体。然而在封装过程中，上下堆叠的封装体都需要使用基板，堆叠封装的整体高度偏高，难以满足电子产品小型化的需求。
实用新型内容
因此，本实用新型提供一种芯片封装结构，降低封装体的翘曲变形。
本实用新型实施例提供了一种芯片封装结构，至少包括：底面相对贴合的第一芯片和第二芯片；多个金属端子，分布在所述第一芯片周围，所述金属端子的一面与所述第一芯片的正面在同一平面；引线，连接在所述第二芯片正面和金属端子的另一面之间；封装层，包封所述第一芯片、第二芯片、引线以及金属端子，具有第一表面及与所述第一表面相对立的第二表面，所述第一表面与所述金属端子的一面与所述第一芯片的正面在同一平面；引出层，设置在所述封装层的第一表面上，分别与所述金属端子的一面第一芯片的正面电连接。
可选地，所述引出层包括：第一重布线层，所述布线层形成在所述封装层的第一表面，与所述第一芯片正面和部分金属端子的一面电连接。过孔。
可选地，所述引出层还包括：介质层，设置在所述布线层的表面，具有多个过孔；第二重布线层，设置在所述介质层表面，通过所述过孔分别与所述第一重布线层、所述金属端子的一面以及所述第一芯片的正面中的至少之一电连接。
可选地，引出层还包括：引脚，分布在所述第二重布线层上。
可选地，所述封装层的第一表面暴露所述金属端子的一面和第一芯片的正面。
可选地，所述封装层包括塑封层。
可选地，所述第一芯片和所述第二芯片之间包括焊接层、烧结层或粘接层中的任意一种。
本实用新型技术方案，具有如下优点：
相比于现有技术中的芯片封装结构，堆叠的芯片之间连接，无需设置基板进行转接，其中上层芯片通过引线与导电柱将焊盘引出，可以满足堆叠芯片引脚的扇出，另外，在封装层上形成暴露第二芯片正面的预设区域，可以较好的满足特定芯片的应用。
附图说明
为了更清楚地说明本实用新型具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本实用新型的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本实用新型实施例提供的芯片装结构截面示例的结构图；
图2～图13为本实用新型实施例提供的芯片封装结构的封装方法具体示流程图。
具体实施方式
下面将结合附图对本实用新型的技术方案进行清楚、完整地描述，显然，所描述的实施例是本实用新型一部分实施例，而不是全部的实施例。基于本实用新型中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本实用新型保护的范围。
此外，下面所描述的本实用新型不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
本实用新型实施例提供一种芯片封装结构，如图1所示，该结构包括：底面相对贴合的第一芯片10和第二芯片20；多个导电柱30，分布在所述第一芯片10周围，所述导电柱30的第一面与所述第一芯片10的正面在同一平面；引线40，连接在所述第二芯片20正面和导电柱30的另一面之间；第一封装层51，包封所述第一芯片10和导电柱30，第二封装层52，包封第二芯片20、引线40，第一封装层51和第二封装层52组成封装层50，封装层50具有第一表面及与所述第一表面相对立的第二表面，所述第一表面暴露所述第一芯片10的正面和导电柱30的第二面，所述第二表面暴露所述第二芯片20正面的预设区域，引出层60，设置在所述封装层50的第一表面上，分别与所述导电柱30的第一面第一芯片10的正面电连接。在本实施例中，所称第二芯片10可以为探测芯片，例如，可以为温度探测芯片，光电探测芯片等探测芯片，所称预设区域为探测区域。在本实施例中，封装层暴露探测层，需将第二芯片的正面背向第一芯片进行封装。
相比于现有技术中的芯片封装结构，堆叠的芯片之间连接，无需设置基板进行转接，其中上层芯片通过引线与导电柱将焊盘引出，可以满足堆叠芯片引脚的扇出，另外，在封装层上形成暴露第二芯片正面的预设区域，可以较好的满足特定芯片的应用。
作为可选的实施例，所述封装层50包括第一封装层51，包封所述第一芯片10，并暴露所述第一芯片10的背面。第二封装层52，设置在所述第一封装层51上，包封所述第二芯片20，并暴露所述第二芯片20正面的预设区域。在本实施例中将封装层50分为层，分别包封第一芯片10和第二芯片20，可以较为方便的制作导电柱30。
所述导电柱30贯穿所述第一封装层51，所述导电柱30的第一面在所述第一封装层面向所述第一芯片背面的一面的表面具有延伸部。所述延伸部的表面具有与所述引线适配的镀层32。在本实施例中，所称导电柱10可以通过金属填充盲孔31得到，也可以将预成型的导电柱安装，再进行封装。所称延伸部的表面的镀层可以为Ni/Pd/Au镀层。可以在引线键合时不仅提高引线的键合力，还可以提高引线与导电柱的导电性能。
在本实施例中，第一芯片10和第二芯片20可以以底面相对贴合的方式堆叠，此外，作为可选的实施例，还可以包括多个芯片，第一芯片10和第二芯片20之间设置层芯片，具体的，各个芯片之间可以设置过渡层，该过渡层不覆盖相邻芯片正面焊盘，第一芯片10上面的堆叠的芯片的正面焊盘均通过引线40连接至导电柱30。在本实施例中，第一芯片10与第二芯片20的连接方式可以为导电胶粘接，焊料焊接，也可以采用烧结的形式贴合在一起。
作为可选的实施例，引出层60包括：第一介质层61，设置在所述封装层60的第一面上，具有与所述导电柱30第二面、第一芯片10的焊盘相对的第一通孔62；重布线层63，所述布线层形成在所述第一介质层背离所述封装层50的一面，通过所述第一通孔62与所述导电柱30的第二面和第一芯片10的焊盘电连接；第二介质层64，设置在所述重布线层63背离所述第一介质层61的一面，具有第二通孔65；引脚66，分布第二通孔65内。在本实施例中，所称第一介质层61和第二介质层63可以为聚对苯撑苯并二噁唑纤维(Poly-p-phenylenebenzobisoxazole，PBO)、聚酰亚胺材料等有机介质材料，所称引脚66可以为球形引脚，也可以为柱形引脚。
本实施例提供了一种芯片封装方法，结合图2-图10，将详细的介绍该封装结构的制作过程，该封装结构的制作方法可以包括如下步骤：
步骤S1：提供一载片100，该载片100具有第一表面及与第一表面相对立的第二表面，第一表面上叠倒装第一芯片10。
在本实施例中，载片100可以为硅基板或者玻璃基板，在本实施例中，第一芯片10可以通过贴装的形式倒装在载片100的第一表面。通过执行步骤S1形成图2所示的结构。
S2.制作第一封装层51，包封第一芯片10，对第一封装层51减薄至第一芯片10背面。所述第一封装层51背离所述载片100的一面暴露所述第一芯片10的背面。通过执行步骤S2形成图3所示的结构。
S3.在所述第一封装层51上形成贯穿所述第一封装层的盲孔31。在本实施例中，可以通过光刻或者激光制作该盲孔，通过执行步骤S3形成图4所示的结构。
S4.金属填充盲孔31，并在所述第一封装层51的背离所述载片的一面的表面形成延伸部。在本实施例中，可以对盲孔31电镀，电镀金属冒镀至第一封装层的上表面。通过执行步骤S4形成图5所示的结构。
S5.在所述延伸部表面金属化镀与所述引线适配的镀层32。在本实施例中，可以对对冒镀出第一封装层上表面的金属化镀Ni/Pd/Au层。通过执行步骤S5形成图6所示的结构。
S6.在所述第一芯片10的背面正装所述第二芯片20。在本实施例中，第二芯片20可以通过焊接或粘接贴附在第一芯片10背面。通过执行步骤S6形成图7所示的结构。
S7.在所述第二芯片20的正面焊盘和与所述焊盘对应的所述导电柱30之间连接引线40。在本实施例中，可以通过键合的方式连接引线，该引线可以为金线或铝线。通过执行步骤S7形成图8所示的结构。
S8.在所述第一封装层51上制作第二封装层52，在所述第二封装52层背离所述第一封装层51的一面正对所述第二芯片20的预设区域开设凹槽53，暴露所述预设区域。通过执行步骤S8形成图9所示的结构。
S9.拆除所述载片100并在所述封装层50拆除所述载片的一面形成引出层60。通过执行步骤S9形成图10所示的结构。具体的步骤S9可以包括如下步骤：
S91.在所述封装层50拆除所述载片的一面形成第一介质层61，并在第一介质层61上形成与所述导电柱30第二面、第一芯片10的焊盘相对的第一通孔62。通过执行步骤S91形成图11所示的结构。
S92.在所述第一介质层61背离所述封装层的一面形成重布线层63，通过所述第一通孔62与所述导电柱30的第二面和第一芯片10的焊盘电连接。通过执行步骤S92形成图12所示的结构。
S93.在所述重布线层63背离所述第一介质层61的一面形成第二介质层64，并在第二介质层64上形成第二通孔65，该通孔连接至重布线层63。第一介质层61和第二介质层63可以通过旋涂PI/PBO类有机介质材料方式制得，第一通孔62和第二通孔64可以通过光刻或激光打孔的方式实现。通过执行步骤S92形成图13所示的结构。
S94.在第二通孔内形多个引脚66。通过执行步骤S94形成图10所示的结构。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本实用新型创造的保护范围之中。

Claims (6)

1.一种芯片封装结构，其特征在于，至少包括：
底面相对贴合的第一芯片和第二芯片；
多个导电柱，分布在所述第一芯片周围；
引线，连接在所述第二芯片正面和金属端子的第一面之间；
封装层，包封所述第一芯片、第二芯片、引线、导电柱，具有第一表面及与所述第一表面相对立的第二表面，所述第一表面暴露所述第一芯片的正面和所述导电柱的第二面，所述第二表面暴露所述第二芯片正面的预设区域；
引出层，设置在所述封装层的第一表面上，分别与所述导电柱的第一面和/或第一芯片的正面电连接。
2.如权利要求1所述的芯片封装结构，其特征在于，所述封装层包括第一封装层，包封所述第一芯片，并暴露所述第一芯片的背面；
第二封装层，设置在所述第一封装层上，包封所述第二芯片，并暴露所述第二芯片正面的预设区域。
3.如权利要求2所述的芯片封装结构，其特征在于，
所述导电柱贯穿所述第一封装层，所述导电柱的第一面在所述第一封装层面向所述第一芯片背面的一面的表面具有延伸部。
4.如权利要求3所述的芯片封装结构，其特征在于，
所述延伸部的表面具有与所述引线适配的镀层。
5.如权利要求1所述的芯片封装结构，其特征在于，
所述第二芯片为探测芯片，所述预设区域为探测区域。
6.根据权利要求1所述的芯片封装结构，其特征在于，所述引出层包括：第一介质层，设置在所述封装层的第一面上，具有与所述导电柱第二面、第一芯片的焊盘相对的第一通孔；
重布线层，所述重布线层形成在所述第一介质层背离所述封装层的一面，通过所述通孔与所述导电柱的第二面和第一芯片的焊盘电连接；
第二介质层，设置在所述重布线层背离所述第一介质层的一面，具有第二通孔；
引脚，分布第二通孔内。
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Publication number Priority date Publication date Assignee Title
CN109801894A (zh) * 2018-12-28 2019-05-24 华进半导体封装先导技术研发中心有限公司 芯片封装结构和封装方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109801894A (zh) * 2018-12-28 2019-05-24 华进半导体封装先导技术研发中心有限公司 芯片封装结构和封装方法

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