CN206148437U

CN206148437U - Mesa diode

Info

Publication number: CN206148437U
Application number: CN201621185134.6U
Authority: CN
Inventors: 冯春阳; 李学良; 马晓洁; 戴建定; 唐毅
Original assignee: SICHUAN HONGXINWEI TECHNOLOGY Co Ltd
Current assignee: SICHUAN HONGXINWEI TECHNOLOGY Co Ltd
Priority date: 2016-11-04
Filing date: 2016-11-04
Publication date: 2017-05-03
Anticipated expiration: 2026-11-04

Abstract

The utility model discloses the semiconductor technology field especially relates to a mesa diode, mesa structure, cover including having the tap drain groove are in the passivation layer on the surface in tap drain groove, mesa structure's PN junction at least the part expose in the surface in tap drain groove, its characterized in that: mesa structure still includes the counter drain groove, the counter drain groove is located the tap drain groove with between the electrode, the passivation layer by the surface in tap drain groove extends to the surface in counter drain groove is and cover the surface in counter drain groove. Through adopting two groove structures and the portion's of blocking design, mesa diode's characteristic and reliability have been improved, especially under high -pressure application scenario. Owing to adopted two groove structures, can further broaden extensive manufacturing of being convenient for to the technical requirement of the appearance of slot.

Description

A kind of mesa diode

Technical field

The utility model technical field of semiconductors, more particularly to a kind of mesa diode of high pressure resistant application.

Background technology

Power semiconductor and large scale integrated circuit are semiconductor chip mutually irreplaceable two important branch. Generally power semiconductor is divided into device for power switching（Such as MOSFET/BJT/IGBT）And power rectifier device（Such as Schottky/FRD）Deng they are the basic components of power-supply management system.And all of electronic information, can't do without electricity Management system.In high voltage rectifier application, the PN junction diode of mesa structure is still widely used.By chemical attack Mode corrode and trench mesas, special passivation glass medium is then filled on table top, to being exposed on trench mesas PN junction is protected.However, for the trench mesas obtained in chemical attack mode, the table top oblique angle of PN junction is controlled well Comparison of coherence Deng groove pattern is difficult, and electric-field intensity compares concentration at the surface that trench mesas have a common boundary with PN junction, and this will When can affect the breakdown voltage, particularly high-voltage applications of PN junction, affect more aobvious serious.

To reduce the table top PN junction surface field concentration effect to obtain high performance breakdown voltage characteristics, can take and subtract The doping content of the little semi-conducting material for forming PN junction.Can thing followed seondary effect be：The doping of semiconductor is lower, is partly leading Body is located at the probability increasing that trench mesas near surface forms the contrary inversion layer of conduction type, i.e.,：Easily form " transoid conduction Raceway groove ", will cause PN junction leakage current to dramatically increase, and at high temperature, the reliability of PN junction device is by serious degradation.Glassivation material Interface charge between material and semiconductor at surface induces the formation of the raceway groove.If interface charge is negative, it would be possible to P-type raceway groove is formed in the N-type semiconductor side for forming PN junction；If interface charge is for just, it would be possible in the p-type for forming PN junction Semiconductor side forms n-type channel.The polarity of interface charge, depends on characteristic and the manufacture of the glass medium filled in groove Process conditions.For application of the breakdown reverse voltage more than 1000V, the N-type semiconductor of PN junction and the doping of P-type semiconductor are formed Concentration is relatively low, and the probability that the raceway groove is formed is bigger.

Industrial quarters make groove when, generally using HNO₃The method of-HF-HAC systems chemical attack carries out trench etching, should Method is easy, processes batch greatly, low cost.But in actual technical process, position shown in label A in FIG（That is groove The position having a common boundary with upper surface）Shape matching is sharp, under glass melting state, is deteriorated in the adhesiveness of the sharp parts, causes Glass herein is than relatively thin, or even groove can not be completely covered, and PN junction is exposed outside.During subsequent technique, such as chemical plating In Ni, and encapsulation process, H2O vapour, metal ion contamination etc. introduce alkali metal such as Na+ and stain from this position, into passivation glass Between glass medium and trench mesas interface, and then deteriorate the characteristic of diode.Particularly high-voltage applications when, affect it is more serious.

Utility model content

In order to solve the above problems, double groove structures and transoid ditch that the utility model passes through a kind of mesa diode of proposition Road blocking unit designs to improve the characteristic and reliability of semiconductor PN mesa diode, particularly in high voltage applications occasion.

A kind of mesa diode, including the mesa structure with main line, the passivation on the surface for being covered in the main line Layer, the PN junction of the mesa structure is at least partly exposed to the surface of the main line；It is characterized in that：The mesa structure is also Including counter drain groove, the counter drain groove is located between the main line and the electrode, the passivation layer by the main line table Face extends to the surface of the counter drain groove and covers the surface of the counter drain groove.

Preferably, depth of the depth of the counter drain groove less than the main line.

Preferably, being provided with inversion channel blocking unit between the counter drain groove and the main line.

Preferably, the mesa structure includes the N areas and P areas for forming the PN junction, the electrode is included by institute The anode for stating the extraction of P areas and the negative electrode drawn by the N areas；The main line and the counter drain groove are formed at the P areas, described Isolation part is provided between counter drain groove and the PN junction.

Preferably, the P areas include the P- areas contacted with N areas and the P+ areas at the top of the P- areas；The tap drain P+ areas between groove and the counter drain groove form the inversion channel blocking unit.

Preferably, thickness of the depth of the counter drain groove less than P+ areas.

Preferably, the N areas include the N- areas contacted with the P areas, the bottom in the N- areas is provided with N+ areas, described the moon Drawn by the N+ areas pole.

Preferably, the passivation layer is glass passivation layer.

The utility model is by using double groove structures and the design of inversion channel blocking unit, improve the spy of mesa diode Property and reliability, particularly under high pressure applications.As a result of double groove structures, the technical requirements to the pattern of groove Can further relax, be easy to extensive manufacture.

Description of the drawings

Fig. 1 prior art single-groove groove mesa diode section of structures.

Fig. 2 mesa diode section of structures of the present utility model.

Fig. 3 mesa diode operation principle schematic diagrams of the present utility model.

Specific embodiment

Embodiment of the present utility model is described in detail below in conjunction with accompanying drawing.

Mesa diode structure of the present utility model, including the mesa structure with main line 8, its cross-section structure such as Fig. 2 It is shown.

N-type substrate silicon chip, its resistance substrate rate is in 30-40 Ω cm scopes, about 280 μm of thickness.At high temperature, N-type substrate By aluminium and boron impurity, while High temperature diffusion forms P+ areas, (surface concentration of boron is about 10 for the upper surface of silicon chip²⁰Atom/cm³Quantity Level) and P- areas, the thickness sum in P+ and P- areas is about 95 μm.The lower surface of N-type substrate silicon chip carries out N-type impurity phosphorus diffusion Form the thickness about 55-60 μm N+ areas (surface concentration 10 of phosphorus²⁰Atom/cm³The order of magnitude), about 110 μm middle of N- areas thickness.

By technologies such as well-known photoetching, chemical attacks, main line 8 is etched.PN junction is on the surface of main line 8 To be exposed on outer.In order to protect PN junction, industrial quarters to adopt many methods, such as knife scraping method, electrophoresis, photoresistance glass method skill Art, coats protective glass as passivation layer 1 on the surface of main line 8, and PN junction and the external world are carried out into insulation blocking.Then generally lead to The method for crossing chemical plating, plates W metal, Au etc., forms the anode 2 and negative electrode 3 of diode.After chip is made, then through envelope Dress forms finished product diode rectifier.

The utility model introduces a counter drain groove 4 as supplement 8 in addition to being passivated the main line of the covering protection of layer 1. Passivation layer 1 is extended to the surface of counter drain groove 4 by the surface of main line 8, and the surface of counter drain groove 4 is covered.Cover the He of counter drain groove 4 The passivation layer 1 of main line 8 links together.The depth of counter drain groove 4 is less than the depth of main line 8, and counter drain groove 4 and main line There is certain interval so that there is the region of a P+ type between main line 8 and counter drain groove 4, the region defines between 8 Inversion channel blocking unit 5, maintains a certain distance with PN junction.

If the doping content of semiconductor is 10¹⁸,10¹⁷,10¹⁶Atom/cm³Magnitude, if surface charge distribution is 10¹², 10¹¹,10¹⁰Electric charge/cm²Magnitude, that is, be possible to produce inversion channel.If surface charge is positive charge (as Na+ stains), P type island region domain produces inversion channel.If surface charge is negative electrical charge, in N-type region domain inversion channel is produced.Although good in theory Good technology controlling and process can be with the density of control surface electric charge, but surface charge density is highly prone to various contaminations in production process Impact.

Such as Fig. 3, in main line 8, there is positive charge 7 in semiconductor, with the interface of passivation glass when the density of positive charge 7 reaches To after certain value, n-type channel will be produced in the near interface of P- areas and passivation layer 1.When PN junction reverse bias, n-type channel from PN junction space barrier region 6 is extended to positioned at the surface of main line 8 in P- areas.And the doping content in P+ areas is high, even if glass is blunt Changing in layer has positive charge, also not easily leads to P+ areas and forms n-type inversion channels.Counter drain groove 4 by n-type channel and electrode 2 every Leave so that n-type channel terminates at inversion channel blocking unit 5.Reverse leakage current will reduce, and hot properties will be enhanced.

In addition, because the pattern of inversion channel blocking unit 5 is than shallower, the glass and half of passivation layer 1 can be improved The adhesion of conductor silicon face, to the surface of main line 8 (PN junction interface) finer and close protection is carried out.In actual process, label in Fig. 1 Region shown in A, the adhesion of glass passivation layer easily goes wrong.And in the double groove structures shown in Fig. 2, the glass of passivation layer 1 The PN junction of main line is entered back into by the transition of counter drain groove 4, it is easy to form fine and close glass passivation layer.And now in counter drain groove 4, Pattern near the boundary position of electrode 2 becomes less important.In this sense by of the present utility model pair of groove knot Structure, relaxes the requirement to groove pattern, is more beneficial for manufacturing.

Claims

1. a kind of mesa diode, including the mesa structure with main line, the passivation layer on the surface for being covered in the main line, The PN junction of the mesa structure is at least partly exposed to the surface of the main line；It is characterized in that：The mesa structure is also wrapped Include counter drain groove, the counter drain groove is located between the main line and the electrode, the passivation layer by the main line surface The surface for extending to the counter drain groove and the surface for covering the counter drain groove.

2. a kind of mesa diode according to claim 1, it is characterised in that：The depth of the counter drain groove is less than the master The depth of groove.

3. a kind of mesa diode according to claim 1, it is characterised in that：Between the counter drain groove and the main line It is provided with inversion channel blocking unit.

4. a kind of mesa diode according to claim 3, it is characterised in that：The mesa structure is included for being formed State the N areas and P areas of PN junction, the negative electrode that the electrode includes the anode drawn by the P areas and drawn by the N areas；The master Groove and the counter drain groove are formed at the P areas.

5. a kind of mesa diode according to claim 4, it is characterised in that：The P areas include the P- areas contacted with N areas With the P+ areas at the top of the P- areas；P+ areas between the main line and the counter drain groove form the inversion channel blocking Portion, between the counter drain groove and the PN junction isolation part is provided with.

6. a kind of mesa diode according to claim 4, it is characterised in that：The depth of the counter drain groove is less than P+ areas Thickness.

7. a kind of mesa diode according to claim 5, it is characterised in that：The N areas include what is contacted with the P areas N- areas, the bottom in the N- areas is provided with N+ areas, and the negative electrode is drawn by the N+ areas.

8. a kind of mesa diode according to claim 1, it is characterised in that：The passivation layer is glass passivation layer.