CN213366606U

CN213366606U - MOS controlled rectifier covered with passivation layer

Info

Publication number: CN213366606U
Application number: CN202120803056.6U
Authority: CN
Inventors: 周泽民; 顾航; 高巍; 戴茂州
Original assignee: Chengdu Rongsi Semiconductor Co ltd
Current assignee: Chengdu Rongsi Semiconductor Co ltd
Priority date: 2021-04-20
Filing date: 2021-04-20
Publication date: 2021-06-04
Anticipated expiration: 2031-04-20

Abstract

The utility model provides a cover MOS control rectifier of passivation layer, including negative pole metal, heavy doping N type semiconductor substrate, N type semiconductor drift region, P type semiconductor body region, heavy doping P type semiconductor contact region, heavy doping N type semiconductor contact region, SiO₂Layer, polycrystalline silicon layer, passivation layer, hole, positive pole metal, the utility model discloses abundant protection grid polycrystalline silicon not receive the influence of stress when the routing, polycrystalline silicon can not cracked to the reliability of device has been improved. Because the reliability of the grid polysilicon is improved, the method further improves the reliability of the grid polysiliconMore advanced device wire bonding methods are allowed to be applied to the structure of the present invention.

Description

MOS controlled rectifier covered with passivation layer

Technical Field

The utility model relates to a power semiconductor device technique, concretely relates to MOS control Rectifier (MOS Controlled Rectifier) that covers the passivation layer, MCR for short.

Background

A MOS Controlled Rectifier (MCR) is a power diode device with excellent performance. MCR is based on power VDMOS, and N is the same as N⁺The source region is directly connected with the N-type epitaxial layer, and the grid electrode and the source electrode are short-circuited to form the two-terminal device. Like the commercially available jbs (junction Barrier Controlled Schottky Rectifier) and MPS (targeted PiN/Schottky Rectifier), MCR combines the advantages of low reverse recovery time of unipolar devices and high withstand voltage and low leakage of PiN diodes. The grid electrode and the source electrode of the original MOSFET are in short circuit to form the anode of the MCR, and the drain electrode of the original MOSFET forms the cathode of the MCR. When the device is forward biased, the parasitic JFET structure depletion region in the original MOSFET structure becomes narrow, and a secondary N is formed⁺And the contact region passes through the JFET region and the N-type drift region to reach the conductive path of the substrate. And due to the existence of the MOS structure, an accumulation layer of electrons is formed below the grid when the device is conducted, so that the forward conduction voltage drop of the device is reduced. When the device is reversely biased, the depletion layer of the JFET area can be widened to pinch off a conducting path only by a small voltage, and the depletion layer is formed below the grid due to the existence of the MOS structure, so that the device has low reverse leakage current. In addition, since the current components when the device is turned on include MOS current and PN junction current, the reverse recovery time of the MCR can be shorter than that of the PiN diode.

The gate poly of an MCR device needs to be connected to an external circuit or lead frame, a process known as wire bonding. In the wire bonding process, heat and stress are often applied to the surface of the metal, so that the inside of the metal is deformed, and further, polysilicon below the metal is damaged. Polysilicon is easily broken when strained, and polysilicon is critical to turn on and off devices in gated devices, so it is very important to protect polysilicon from stress.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned drawbacks of the prior art, the present invention is directed to a new structure of MCR covering passivation layer, which is shown in fig. 1. A passivation layer is added between the grid polycrystalline material and the metal electrode, and the passivation layer can relieve stress in a routing process so that the polycrystalline material is prevented from being damaged by the stress.

In order to realize the purpose of the utility model, the utility model discloses technical scheme as follows:

a MOS control rectifier covering a passivation layer comprises a cathode metal, a heavily doped N-type semiconductor substrate above the cathode metal, and an N-type semiconductor drift region above the heavily doped N-type semiconductor substrate, wherein a P-type semiconductor body region, a heavily doped P-type semiconductor contact region and a heavily doped N-type semiconductor contact region are arranged in the N-type semiconductor drift region, the heavily doped N-type semiconductor contact region is arranged above the P-type semiconductor body region, the heavily doped P-type semiconductor contact region is arranged at one side of the heavily doped N-type semiconductor contact region and one side of the P-type semiconductor body region, and SiO is covered above the middle of the N-type drift region₂Layer of SiO₂A polycrystalline silicon layer covers the layer, and a passivation layer covers the polycrystalline silicon layer; and a hole is formed in the middle of the passivation layer, anode metal covers the passivation layer, the hole is filled with metal, and the contact between the anode metal and the polycrystalline silicon layer is realized through the metal in the hole.

Preferably, the passivation layer is selected from SiO₂One of a passivation layer, a SiNx passivation layer, a phosphorosilicate glass passivation layer and a polyimide passivation layer.

Preferably, the anode metal is metallic aluminum.

Preferably, the heavy doping is of an impurity concentration order greater than 1e18cm^-3Doping of (3).

The utility model discloses the theory of operation does: when applying positive bias voltage to the MCR structure of the present invention, the depletion layer of the JFET region in the original MOSFET structure becomes narrow, forming a channel N⁺And the contact region passes through the JFET region and the N-type drift region to reach the conductive path of the substrate. Meanwhile, a PN junction formed by the P-type body region and the N drift region is conducted, so that the current when the device is conducted comprises two components of PN junction current and MOS current. The MOS structure enables an accumulation layer of electrons to be formed below the grid electrode during forward bias, and forward conduction voltage drop of the device is reduced. When giving the utility modelWhen the MCR structure in the MOSFET structure applies reverse bias voltage, a depletion layer of a JFET (junction field effect transistor) region in the original MOSFET structure is widened to the JFET region to be pinched off, the device is in a cut-off state at the moment, and reverse bias voltage is borne by a PN junction formed by a P-type body region and an N drift region. And a depletion layer is formed below the grid electrode of the MOS structure in reverse bias, so that the device has lower off-state leakage current. During reverse recovery, the reverse recovery time is shorter than that of a conventional PiN diode because only a part of the conduction current of the device is bipolar current. Meanwhile, when the device is subjected to reverse voltage withstanding, the PN junction formed by the P-type body region and the N drift region bears voltage, so that the structure is higher in voltage withstanding and smaller in electric leakage compared with a conventional Schottky diode. Therefore, the structure in the utility model has the advantages of bipolar diode and unipolar diode concurrently. In order to reduce the damage to the grid polysilicon in the wire bonding process, a passivation layer is deposited above the polysilicon, so that the stress generated in the wire bonding process can be relieved, and the polysilicon layer is protected from cracking. And then punching the passivation layer to realize the interconnection of the polysilicon gate and the device anode.

The utility model has the advantages that: 1. the utility model discloses abundant protection grid polycrystalline silicon not receive the influence of stress when the routing, polycrystalline silicon can not cracked to the reliability of device has been improved. 2. The utility model discloses because the reliability of grid polycrystalline silicon has been improved, so make more advanced device routing methods be allowed to use in the structure of the utility model.

Drawings

Fig. 1 is a cross-sectional view of a MOS controlled rectifier covered with a passivation layer according to the present invention.

Fig. 2 is a circuit topology diagram of a MOS controlled rectifier covered with a passivation layer according to the present invention.

1 is heavily doped N-type semiconductor substrate, 2 is N-type semiconductor drift region, 3 is P-type semiconductor body region, 4 is heavily doped P-type semiconductor contact region, 5 is heavily doped N-type semiconductor contact region, 6 is SiO₂Layer, 7 is a polysilicon layer, 8 is a passivation layer, 9 is an anode metal, 10 is a cathode metal, and 11 is a hole.

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

As shown in fig. 1, the present embodiment provides a MOS Controlled Rectifier (MOS Controlled Rectifier), abbreviated as MCR, covering a passivation layer, including a cathode metal, a heavily doped N-type semiconductor substrate above the cathode metal, and an N-type semiconductor drift region above the heavily doped N-type semiconductor substrate, wherein a P-type semiconductor body region, a heavily doped P-type semiconductor contact region, and a heavily doped N-type semiconductor contact region 5 are disposed in the N-type semiconductor drift region, the heavily doped N-type semiconductor contact region is disposed above the P-type semiconductor body region, the heavily doped P-type semiconductor contact region is disposed at one side of the heavily doped N-type semiconductor contact region and the P-type semiconductor body region, and a SiO is covered above the middle of the N-type drift region₂Layer of SiO₂A polycrystalline silicon layer covers the layer, and a passivation layer covers the polycrystalline silicon layer; and a hole is formed in the middle of the passivation layer, anode metal covers the passivation layer, the hole is filled with metal, and the contact between the anode metal and the polycrystalline silicon layer is realized through the metal in the hole.

The passivation layer is selected from SiO₂One of a passivation layer, a SiNx passivation layer, a phosphorosilicate glass passivation layer and a polyimide passivation layer.

The anode metal is metallic aluminum.

Heavily doped to an impurity concentration level greater than 1e18cm^-3Doping of (3).

Fig. 2 is a circuit topology diagram of the structure. The graphic representation of a MOS Controlled Rectifier (MCR) overlying the passivation layer may be formed by a combination of a JFET and a diode, wherein the JFET gate and drain are shorted to form the anode of the MCR; the anode of the diode is connected with the source electrode of the JFET to form the cathode of the MCR. The device is turned on when a forward bias is applied and turned off when a reverse bias is applied.

The working principle of the structure in this embodiment is as follows: when giving the present utilityWhen the novel MCR structure applies positive bias voltage, the depletion layer of the JFET area in the original MOSFET structure is narrowed to form a structure from N⁺And the contact region passes through the JFET region and the N-type drift region to reach the conductive path of the substrate. Meanwhile, a PN junction formed by the P-type body region and the N drift region is conducted, so that the current when the device is conducted comprises two components of PN junction current and MOS current. The MOS structure enables an accumulation layer of electrons to be formed below the grid electrode during forward bias, and forward conduction voltage drop of the device is reduced. When giving the utility model provides a MCR structure when applying reverse bias voltage, JFET district depletion layer in the former MOSFET structure widens to JFET district pinch-off, and the device is in the off-state this moment, and reverse bias voltage is undertaken by the PN junction that P type somatic region and N drift region formed. And a depletion layer is formed below the grid electrode of the MOS structure in reverse bias, so that the device has lower off-state leakage current. During reverse recovery, the reverse recovery time is shorter than that of a conventional PiN diode because only a part of the conduction current of the device is bipolar current. Meanwhile, when the device is subjected to reverse voltage withstanding, the PN junction formed by the P-type body region and the N drift region bears voltage, so that the structure is higher in voltage withstanding and smaller in electric leakage compared with a conventional Schottky diode. Therefore, the structure in the utility model has the advantages of bipolar diode and unipolar diode concurrently. In order to reduce the damage to the grid polysilicon in the wire bonding process, a passivation layer is deposited above the polysilicon, so that the stress generated in the wire bonding process can be relieved, and the polysilicon layer is protected from cracking. And then punching the passivation layer to realize the interconnection of the polysilicon gate and the device anode.

The utility model relates to a key technology: the process of covering the passivation layer 8 on the polysilicon layer 7 adopts CVD chemical vapor deposition, mechanical punching is carried out on the passivation layer 8, then metal aluminum is deposited on the passivation layer 8, and the grid electrode and the source electrode of the original MOSFET structure are connected through a small hole in the middle of the passivation layer 8.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A MOS controlled rectifier overlying a passivation layer, comprising: the silicon-based SOI device comprises a cathode metal (10), a heavily doped N-type semiconductor substrate (1) above the cathode metal (10), and an N-type semiconductor drift region (2) above the heavily doped N-type semiconductor substrate (1), wherein a P-type semiconductor body region (3), a heavily doped P-type semiconductor contact region (4) and a heavily doped N-type semiconductor contact region (5) are arranged inside the N-type semiconductor drift region (2), the heavily doped N-type semiconductor contact region (5) is arranged above the P-type semiconductor body region (3), the heavily doped P-type semiconductor contact region (4) is arranged on one side of the heavily doped N-type semiconductor contact region (5) and one side of the P-type semiconductor body region (3), and SiO is covered above the middle of the N-₂Layer (6), SiO₂A polysilicon layer (7) covers the layer (6), and a passivation layer (8) covers the polysilicon layer (7); a hole (11) is formed in the middle of the passivation layer (8), anode metal (9) covers the passivation layer (8), metal is filled in the hole (11), and the anode metal (9) is in contact with the polycrystalline silicon layer (7) through the metal in the hole (11).

2. A MOS controlled rectifier of claim 1, wherein: the passivation layer (8) is selected from SiO₂One of a passivation layer, a SiNx passivation layer, a phosphorosilicate glass passivation layer and a polyimide passivation layer.

3. A MOS controlled rectifier of claim 1, wherein: the anode metal (9) is metallic aluminum.