CN205723627U - 一种led焊线打线 - Google Patents

一种led焊线打线 Download PDF

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Publication number
CN205723627U
CN205723627U CN201620378420.8U CN201620378420U CN205723627U CN 205723627 U CN205723627 U CN 205723627U CN 201620378420 U CN201620378420 U CN 201620378420U CN 205723627 U CN205723627 U CN 205723627U
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Prior art keywords
routing
bank
bonding wire
little bank
little
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CN201620378420.8U
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Inventor
王宇鹏
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Changzhi Hongyuan Photoelectric Technology Co Ltd
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Changzhi Hongyuan Photoelectric Technology Co Ltd
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Priority to CN201620378420.8U priority Critical patent/CN205723627U/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

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  • Led Device Packages (AREA)

Abstract

一种LED焊线打线，属于LED封装领域中的焊线工序技术领域，它包括打线和小线弧，其特征是：打线为一字形，打线两端分别设置有小线弧，所述打线两端小线弧相互平行，所述小线弧通过打线形成90°内错角。所述打线与小线弧的材质均为金及不可避免的杂质，其中打线与小线弧中金的纯度为99.97%。与现有技术相比，同样支架情况下，鱼尾加小线弧会有效增加焊线拉力；材料封胶后，胶体会对金线进行拉扯，极端环境下热胀冷缩剧烈，将鱼尾拉起，导致死灯，加小线弧会使鱼尾变牢固，不容易被拉起，从而提高焊线品质，降低死灯率。

Description

一种LED焊线打线
技术领域
本实用新型属于LED封装领域中的焊线工序技术领域，特别涉及一种LED焊线打线。
背景技术
打线也叫Wire Bonding，即压焊，也称为绑定，键合，丝焊，是指使用金属丝（金线、铝线等），利用热压或超声能源，完成微电子器件中固态电路内部互连接线的连接，即芯片与电路或引线框架之间的连接。常见于表面封装工艺，如COB工艺。
LED封装技术中焊线打线由于参数设置不当，打线极易出现鱼尾现象，影响焊线品质。
实用新型内容
本实用新型的目的是减少打线出现鱼尾的现象，保证焊线品质，本实用新型特别提供一种LED焊线打线。
为解决上述技术问题，本实用新型采用的技术方案为：
一种LED焊线打线，它包括打线和小线弧，其特征是：打线为一字形，打线两端分别设置有小线弧，所述打线两端小线弧相互平行，所述小线弧通过打线形成90°内错角。
所述打线与小线弧的材质均为金及不可避免的杂质，其中打线与小线弧中金的纯度为99.97%。
由于本实用新型采用了上述技术方案，与现有技术相比，同样支架情况下，鱼尾加小线弧会有效增加焊线拉力；材料封胶后，胶体会对金线进行拉扯，极端环境下热胀冷缩剧烈，将鱼尾拉起，导致死灯，加小线弧会使鱼尾变牢固，不容易被拉起，从而提高焊线品质，降低死灯率。
附图说明
图1为现有技术中打线结构示意图。
图2为本实用新型中打线结构示意图。
图中，1为打线，2为小线弧。
具体实施方式
如图1、2所示，一种LED焊线打线，它包括打线1和小线弧2，其特征是：打线1为一字形，打线1两端分别设置有小线弧2，所述打线1两端小线弧2相互平行，所述小线弧2通过打线1形成90°内错角。
所述打线1与小线弧2的材质均为金及不可避免的杂质，其中打线1与小线弧2中金的纯度为99.97%。
以上所述，仅为本实用新型的具体实施方式，但本实用新型的保护范围并不局限于此，任何熟悉技术领域的技术人员在本实用新型揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本实用新型的保护范围之内。因此，本实用新型的保护范围应以所述权利要求的保护范围为准。

Claims (2)

1.一种LED焊线打线，它包括打线（1）和小线弧（2），其特征是：打线（1）为一字形，打线（1）两端分别设置有小线弧（2），所述打线（1）两端小线弧（2）相互平行，所述小线弧（2）通过打线（1）形成90°内错角。
2.根据权利要求1所述的一种LED焊线打线，其特征是：所述打线（1）与小线弧（2）的材质均为金及不可避免的杂质，其中打线（1）与小线弧（2）中金的纯度为99.97%。
CN201620378420.8U 2016-04-29 2016-04-29 一种led焊线打线 Active CN205723627U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201620378420.8U CN205723627U (zh) 2016-04-29 2016-04-29 一种led焊线打线

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201620378420.8U CN205723627U (zh) 2016-04-29 2016-04-29 一种led焊线打线

Publications (1)

Publication Number Publication Date
CN205723627U true CN205723627U (zh) 2016-11-23

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Country Status (1)

Country Link
CN (1) CN205723627U (zh)

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