CN202796916U - 一种塑封的非绝缘功率半导体模块 - Google Patents
一种塑封的非绝缘功率半导体模块 Download PDFInfo
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- CN202796916U CN202796916U CN2012204138661U CN201220413866U CN202796916U CN 202796916 U CN202796916 U CN 202796916U CN 2012204138661 U CN2012204138661 U CN 2012204138661U CN 201220413866 U CN201220413866 U CN 201220413866U CN 202796916 U CN202796916 U CN 202796916U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
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Abstract
本实用新型涉及一种塑封的非绝缘功率半导体模块,包括芯片、铜基板、电极引脚、塑封管壳、绝缘衬垫,芯片焊接在铜基板上,芯片和芯片、芯片和电极引脚、铜基板和电极引脚、铜基板和铜基板之间通过铝丝键合连接,本模块采用芯片直接焊接在铜基板上,省却了陶瓷层,减小了热阻,提高了塑封模块的功率密度,实现了体积的小型化,而且加工过程简单,与现有塑封工艺兼容,成本相较灌封的大功率模块大大降低,而且进一步减小了模块的内部互联电感。
Description
技术领域
本实用新型涉及一种塑封的非绝缘功率半导体模块。
背景技术
现有功率半导体模块,有两种封装形式,一种是灌封形式的封装,可以实现大功率的集成,散热和应力比较优异;另一种是塑封形式的封装,加工简单,成本很低,非常便于自动化生产。塑封功率半导体模块一般指采用塑封结构实现两个以上的芯片互联,形成某种拓扑实现一定的功能的模块。灌封工艺加工模块可以实现大功率封装,但是加工步骤复杂,成本很高,塑封工艺加工模块由于散热以及应力的限制,只能实现小功率的模块,或者大功率的单管封装。
实用新型内容
本实用新型所要解决的技术问题是提供一种塑封的非绝缘功率半导体模块,采用塑封结构并配合绝缘衬垫实现大功率模块的集成封装,体积轻便,内部互联电感相较灌封工艺加工的模块大大减小,加工步骤与现有塑封工艺完全兼容,成本低廉。
本实用新型解决上述技术问题的技术方案如下:一种塑封的非绝缘功率半导体模块,包括芯片、铜基板、电极引脚、塑封管壳、绝缘衬垫,芯片焊接在铜基板上,芯片和电极引脚之间通过铝丝键合连接、铜基板和电极引脚之间通过铝丝键合连接,起到一个互联的作用以实现不同的电路连接结构;电极引脚和铜基板固定密封在塑封管壳中,形成一个坚实的整体,绝缘衬垫粘合在铜基板下方起到一个绝缘的作用。所述的键合连接为材料经表面清洗和活化处理,在一定条件下直接结合,通过范德华力、分子力甚至原子力使晶片键合成为一体。
进一步,芯片和铜基板可为多个,多个芯片之间通过铝丝键合连接,多个铜基板之间通过铝丝键合连接。
本实用新型的有益效果是:模块采用芯片直接焊接在铜底板上,省却了陶瓷层,减小了热阻,提高了塑封模块的功率密度,实现了体积的小型化,且加工过程简单,与现有塑封工艺兼容,成本相较灌封的大功率模块大大降低,而且进一步减小了模块的内部互联电感。
附图说明
图1为本实用新型半桥塑封模块结构图;
图2为本实用新型半桥塑封模块沿图1中虚线剖面结构图;
图3为本实用新型斩波塑封模块结构图;
图4为本实用新型斩波塑封模块沿图3中虚线剖面结构图。
附图中,各标号所代表的部件列表如下:
1、芯片,2、电极引脚,3、铜基板,4、塑封管壳,5、铝丝,6、绝缘衬垫。
具体实施方式
以下结合附图对本实用新型的原理和特征进行描述,所举实例只用于解释本实用新型,并非用于限定本实用新型的范围。
如图1所示,为一个半桥模块的主视图,该半桥模块有7个电极引脚,两块铜基板3,两块绝缘衬垫6,4颗芯片,1个塑封管壳,芯片1焊接在铜基板3上,芯片和芯片、芯片和电极引脚、铜基板和电极引脚、铜基板和铜基板之间通过铝丝5键合连接,电极引脚2和铜基板3通过塑封管壳4来定位和密封形成一个坚实的整体,绝缘衬垫6粘合在铜基板3下方。
图2为沿图一虚线处得横切剖面图。
如图3所示为采用两块铜基板3,两块绝缘衬垫6,2颗芯片,一个塑封管壳4,4个电极引脚来实现一个斩波电路结构。
以上所述仅为本实用新型的较佳实施例,并不用以限制本实用新型,凡在本实用新型的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本实用新型的保护范围之内。
Claims (2)
1.一种塑封的非绝缘功率半导体模块,其特征在于包括芯片、铜基板、电极引脚、塑封管壳、绝缘衬垫,所述芯片焊接在铜基板上,所述芯片和所述电极引脚通过铝丝键合连接,所述铜基板和所述电极引脚之间通过铝丝键合连接,所述电极引脚和铜基板固定密封于塑封管壳中,所述绝缘衬垫粘合在铜基板下方。
2.如权利要求1所述的塑封的非绝缘功率半导体模块,其特征在于,所述芯片和铜基板为多个,所述多个芯片之间通过铝丝键合连接,所述多个铜基板之间通过铝丝键合连接。
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CN105895588A (zh) * | 2014-12-30 | 2016-08-24 | 华天科技(西安)有限公司 | 一种多元件、铜框架和基板混装的封装结构及其制备方法 |
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CN105895588A (zh) * | 2014-12-30 | 2016-08-24 | 华天科技(西安)有限公司 | 一种多元件、铜框架和基板混装的封装结构及其制备方法 |
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