CN205582966U

CN205582966U - Chip package base plate

Info

Publication number: CN205582966U
Application number: CN201620182921.9U
Authority: CN
Inventors: 黄晓东; 陈锡园
Original assignee: Huading Science And Technology Group Co Ltd; Shanghai Ten Thousand Safety And Environmental Protection In Third Of Twelve Earthly Branches Science And Technology Ltd
Current assignee: Shanghai Huayan safety and Environmental Protection Technology Co.,Ltd.
Priority date: 2016-03-10
Filing date: 2016-03-10
Publication date: 2016-09-14
Anticipated expiration: 2026-03-10

Abstract

The utility model discloses a chip package base plate, including base plate layer, sputter layer and protective layer, sputter layer deposit is on the base plate layer, and the protective layer covers on the sputter layer, the material on base plate layer is glass or polymer, the material on sputter layer is the copper alloy, the material of protective layer is metal or metal oxide. Above -mentioned chip package base plate has used the conducting material copper more low -priced relatively than ITO transparency carrier to have the circuit diagram of specific design, have high impact resistance nature and low overall resistance's performance, can practice thrift manufacturing cost by a wide margin, improve production efficiency, help improving the packaging efficiency of follow -up chip, and then make the subsequent product more stable, therefore have high visibility and cost competitiveness.

Description

A kind of chip package base plate

Technical field

This utility model belongs to semiconductor device processing technology field, is specifically related to a kind of chip package base plate.

Background technology

Base plate for packaging can be chip provide electrically connect, protect, support, dispel the heat, the effect such as assembling, to realize many pinizations, reduce encapsulating products volume, improve electrical property and the purpose of thermal diffusivity, VHD or multi-chip module. LED (light emitting diode) encapsulation refers to the encapsulation of luminescence chip, LED Encapsulation technology mostly develops in Discrete device packaging technical foundation and develops, but has the biggest particularity.Generally, the tube core of discrete device is sealed in packaging body, and the effect of encapsulation is mainly protected tube core and completes electric interconnection.And LED Encapsulation has been then the output signal of telecommunication, and protection tube core normally works, the function of output visible ray, and existing electrical quantity has again design and the technology requirement of optical parameter, so there is special requirement to encapsulating material, it is impossible to being packaged for discrete device simply LED .In the ordinary course of things, LED Emission wavelength vary with temperature into 0 . 2-0 . 3nm/ DEG C, spectral width increases therewith, affects bright-colored degree.When forward current flows through pn Knot, heat generation loss makes interface produce temperature rise, and near room temperature, temperature often raises 1 DEG C, LED Luminous intensity can correspondingly reduce 1% Left and right, so package cooling is to holding LED Excitation is extremely important with luminous intensity, and use reduces its way driving electric current more, reduces junction temperature, most LED Driving electric current be limited in 20mA Left and right.But, LED Light output can increase with the increase of electric current, a lot of power-types LED Driving electric current can reach 70mA 、 100mA Even 1A Level, improves encapsulating structure, introduces brand-new LED Encapsulation design concept and low thermal resistance encapsulating structure and technology are improved LED Original restriction performance, in this context COB Encapsulation technology is applied to more and more widely LED Encapsulation, COB Encapsulation will be directly encapsulated into metal base printed circuit board by multiple chips MCPCB , use multiple chips can not only improve brightness, additionally aid realization LED The reasonable disposition of chip, reduces single LED The input current amount of chip is to guarantee high efficiency.On the other hand pass through COB Package application in LED Light fixture, not only with saving of work and time, and can save the cost of device encapsulation, totally can reduce 30% Left and right cost, this for LED The application of illumination has the most great meaning.But due to current COB Base plate for packaging all selects metal basal board, and it is only capable of presenting dome-geometry light source to greatest extent, for making LED The luminescence of energy greater angle, a lot of enterprises all have trial to be packaged on the transparent substrate LED , transparency carrier mainly have glass, PC Deng, but due to their heat conduction and heat radiation poor effect and be difficult to make electrode, printed circuit etc. above and be abandoned and be applied to LED Chip COB Encapsulation field.Transparency carrier is used, by sputter on transparency carrier through improving some enterprise ITO Electrically conducting between circuit realiration chip and chip, transparent characteristic will not stop simultaneously LED Chip go out light.Owing to technical process relating to dry etching equipment, therefore complex technical process, relatively costly.

Summary of the invention

For technical problem present in prior art, the purpose of this utility model is the product in order to simplify prior art, replaces with copper ITO , by direct for copper sputter on the transparent substrate, make a kind of chip package base plate.

In order to realize object above, this utility model is achieved through the following technical solutions:

A kind of chip package base plate, including substrate layer, sputtered layer and protective layer；Described sputtered layer deposits on the substrate layer, and protective layer overlays in sputtered layer；The material of described substrate layer is glass or polymer, and the material of described sputtered layer is copper alloy, and the material of described protective layer is metal or metal-oxide, described sputter use the pulse power carry out, operation voltage between 400 Volt is extremely 700 Between Fu Te.

Further, the material of described substrate layer is PET (polyethylene terephthalate), PI (polyimides), PC (Merlon), PMMA (polymethyl methacrylate), COC (cyclic olefine copolymer), TCA (Triafol T) or sapphire.

Further, described sputtered layer distribution copper conductor circuit, the width of described copper conductor is less than 4 Micron, each copper conductor is spaced 50-100 Micron.

Further, the thickness of described substrate layer is 15-250 Micron, preferably 25-75 Micron.

Further, the thickness of described sputtered layer is 0.03-1.5 Micron, preferably 0.05-0.5 Micron.

Further, described protective layer thickness is described sputtered layer thickness 30-40% 。

Chip package base plate of the present utility model employs ratio ITO The conductive material copper that transparency carrier is relatively inexpensive, and there is the circuit diagram of particular design, there is high impact properties and the performance of low all-in resistance, can significantly save production cost, improve production efficiency, it is favorably improved the packaging efficiency of follow-up chip, and then makes subsequent product more stable, thus there is high visibility and cost competitiveness.

Accompanying drawing explanation

Figure 1 Structural representation for this utility model chip package base plate.

Wherein, 1. Substrate layer, 2. Sputtered layer, 3. Protective layer.

Detailed description of the invention

In order to make those skilled in the art be more fully understood that the technical solution of the utility model, with detailed description of the invention, this utility model is described in further detail below in conjunction with the accompanying drawings.

See figure 1 , chip package base plate of the present utility model, including substrate layer, sputtered layer and protective layer；Described sputtered layer deposits on the substrate layer, and protective layer overlays in sputtered layer；The material of described substrate layer is glass or polymer, and the material of described sputtered layer is copper alloy, and the material of described protective layer is metal or metal-oxide.

Chip package base plate preparation technology of the present utility model mainly comprises the steps:

1 , select substrate: glass, PET (polyethylene terephthalate), PI (polyimides), PC (Merlon), PMMA (polymethyl methacrylate), COC (cyclic olefine copolymer), TCA (Triafol T) or sapphire.

Select target: copper alloy, purity is good, and quality is even, bubble-free, and surfacing is bright and clean.

, sputter: sputter substrate, this technological requirement vacuum exists 1 × 10-3Torr Left and right, i.e. 1.3 × 10-3Pa Vacuum state under be filled with noble gas argon (Ar) , and at plastic substrate or glass ( Anode ) And metal targets ( Negative electrode ) Between apply high voltage direct current, due to glow discharge (glow discharge) Produce charged particle bombardment target material surface so that it is sputtering entrance gas phase (i.e. target enters gas phase, bombards), produce plasma, the atom of metal targets is driven out of, is deposited on plastic substrate by plasma.In the application, being that metal material of copper is attached to by the way of sputter substrate surface, the thickness of sputtered layer is about 0.03~1.5 μ m , sputter can use the sputtering process of routine.The purpose using sputter has following 3 Point:

( 1 If) directly use plated film technique copper wire to be electroplated onto on substrate, copper material adhesive force is inadequate, it is impossible to pass through thermal shock test, the problem that there is reliability, and using the reliability of sputtering way higher, after test proves by sputter, electroplating line can pass through thermal shock test.

( 2 ) metal of sputter can play electric action in electroplating process；The circuit board of this mode, without additional designs electroplate lead wire, contributes to reducing cabling area, it is achieved the miniaturization of product.

( 3 ) sputtered metal layer of substrate surface can play buffering when by thermal shock and be acted on.

In sputtered layer Protective layer is covered on surface.

Embodiment 1

Above-mentioned chip package base plate, wherein said substrate layer is PET , thickness is 20 Micron, described sputtered layer thickness is 0.05 Micron, described protective layer is copper, and thickness is 0.02 Micron；Described sputtered layer distribution copper conductor circuit, the width of described copper conductor is less than 4 Micron, each copper conductor is spaced 50 Micron.

Embodiment 2

Above-mentioned chip package base plate, wherein said substrate layer is PET , thickness is 200 Micron, described sputtered layer thickness is 1.5 Micron, described protective layer is rustless steel, and thickness is 0.5 Micron, described sputtered layer distribution copper conductor circuit, the width of described copper conductor is less than 4 Micron, each copper conductor is spaced 100 Micron.

Embodiment 3

Above-mentioned chip package base plate, wherein said substrate layer is PI , thickness is 50 Micron, described sputtered layer thickness is 0.5 Micron, described protective layer thickness is 0.15 Micron, described sputtered layer distribution copper conductor circuit, the width of described copper conductor is less than 4 Micron, each copper conductor is spaced 75 Micron.

Embodiment 4

The above embodiments 1 Chip package base plate, difference is that described substrate layer is PC , thickness is 50 Micron, described sputtered layer thickness is 0.5 Micron, described protective layer thickness is 0.15 Micron.

Embodiment 5

The above embodiments 2 Chip package base plate, difference is that described substrate layer is PMMA , thickness is 50 Micron, described sputtered layer thickness is 0.5 Micron, described protective layer thickness is 0.15 Micron.

Embodiment 6

The above embodiments 2 Chip package base plate, difference is that described substrate layer is TCA , thickness is 50 Micron, described sputtered layer thickness is 0.5 Micron, described protective layer thickness is 0.15 Micron.

Embodiment 7

The above embodiments 3 Chip package base plate, difference is that described substrate layer is sapphire, and thickness is 20 Micron, described sputtered layer thickness is 0.05 Micron, described protective layer thickness is 0.02 Micron.

Embodiment 8

The above embodiments 3 Chip package base plate, difference is that described substrate layer is glass, and thickness is 20 Micron, described sputtered layer thickness is 0.05 Micron, described protective layer thickness is 0.02 Micron.

It is last it should be noted that, embodiment of above is only in order to illustrate that the technical solution of the utility model is not intended to limit.It should be understood by a person of ordinary skill in the art that detailed description of the invention of the present utility model can be modified or portion of techniques feature is carried out equivalent；Without deviating from the spirit of technical solutions of the utility model, it all should be contained in the middle of the technical scheme scope that this utility model is claimed.

Claims

1. a chip package base plate, it is characterised in that include substrate layer, sputtered layer and protective layer；Described sputtered layer deposits on the substrate layer, and protective layer overlays in sputtered layer；The material of described substrate layer is glass or polymer, and the material of described sputtered layer is copper alloy, and the material of described protective layer is metal or metal-oxide.

Chip package base plate the most according to claim 1, it is characterized in that, the material of described substrate layer is PET(polyethylene terephthalate), PI(polyimides), PC(Merlon), PMMA(polymethyl methacrylate), COC(cyclic olefine copolymer), TCA(Triafol T) or sapphire.

Chip package base plate the most according to claim 1, it is characterised in that described sputtered layer distribution copper conductor circuit, the width of described copper conductor is less than 4 microns, each copper conductor spaced 50-100 micron.

Chip package base plate the most according to claim 1, it is characterised in that the thickness of described substrate layer is 15-250 micron.

5. according to chip package base plate described in claim 1 or 4, it is characterised in that the thickness of described substrate layer is 25-75 micron.

Chip package base plate the most according to claim 1, it is characterised in that the thickness of described sputtered layer is 0.03-1.5 micron.

7. according to chip package base plate described in claim 1 or 6, it is characterised in that the thickness of described sputtered layer is 0.05-0.5 micron.

Chip package base plate the most according to claim 1, it is characterised in that described protective layer thickness is the 30-40% of described sputtered layer thickness.