CN105702813A - Chip package substrate - Google Patents
Chip package substrate Download PDFInfo
- Publication number
- CN105702813A CN105702813A CN201610135396.XA CN201610135396A CN105702813A CN 105702813 A CN105702813 A CN 105702813A CN 201610135396 A CN201610135396 A CN 201610135396A CN 105702813 A CN105702813 A CN 105702813A
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- CN
- China
- Prior art keywords
- layer
- chip package
- base plate
- substrate
- thickness
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Abstract
The present invention discloses a chip package substrate, which comprises a substrate layer, a sputtering layer and a protective layer. The sputtering layer is deposited on the substrate layer. The protective layer is coated on the sputtering layer. The substrate layer is made of glass or polymer. The sputtering layer is made of copper alloy. The protective layer is made of metal or metal oxide. The sputtering operation is conducted by using a pulsed power supply, and the operating voltage is between 400 volts to 700 volts. The above chip package substrate is prepared by adopting the conductive material copper, wherein the conductive material copper is relatively inexpensive compared with an ITO transparent substrate. Meanwhile, the circuit diagram of the chip package substrate is specifically designed, so that the chip package substrate is high in impact resistance and low in total resistance. The production cost is greatly saved and the production efficiency is improved. The subsequent packaging efficiency of a chip is improved. Therefore, the subsequent product is more stable. As a result, the chip package substrate is high in visibility and cost competitiveness.
Description
Technical field
The invention belongs to semiconductor device processing technology field, be specifically related to a kind of chip package base plate。
Background technology
Base plate for packaging can provide the effects such as electrical connection, protection, support, heat radiation, assembling for chip, to realize many pinizations, reduces encapsulating products volume, improves electrical property and the purpose of thermal diffusivity, VHD or multi-chip module。LED(light emitting diode) encapsulate the encapsulation referring to luminescence chip, mostly development and the differentiation in Discrete device packaging technical foundation of LED encapsulation technology, but have very big particularity。Generally, the tube core of discrete device is sealed in packaging body, and the effect of encapsulation is mainly protected tube core and completes electric interconnection。LED encapsulation has been then the output signal of telecommunication, protects tube core normal operation, the function of output visible ray; existing electrical quantity; there are again design and the technology requirement of optical parameter, so encapsulating material there being special requirement, it is impossible to simply the encapsulation of discrete device is used for LED。In the ordinary course of things, the emission wavelength of LED varies with temperature as 0.2-0.3nm/ DEG C, and spectral width increases therewith, affects bright-colored degree。When forward current flows through pn-junction, heat generation loss makes interface produce temperature rise, at near room temperature, temperature often raises 1 DEG C, the luminous intensity of LED can correspondingly reduce about 1%, so package cooling is extremely important to keeping LED excitation and luminous intensity, adopt reduced its way driving electric current more in the past, reducing junction temperature, the driving electric current of most LED is limited in about 20mA。But, the light output of LED can increase with the increase of electric current, the driving electric current of a lot of power-type LEDs can reach 70mA, 100mA is 1A level even, improve encapsulating structure, introduce brand-new LED encapsulation design concept and low thermal resistance encapsulating structure and technology improves the original restriction performance of LED, COB encapsulation technology is applied to LED encapsulation more and more widely in this context, COB encapsulation is directly encapsulated into metal base printed circuit board MCPCB by multiple chips, use multiple chips can not only improve brightness, additionally aid the reasonable disposition realizing LED chip, reduce the input current amount of single led chip to guarantee high efficiency。On the other hand by COB package application in LED lamp, not only can saving of work and time, and the cost of device encapsulation can be saved, totally can reduce the cost of about 30%, this has very great meaning for the application of LED illumination。But owing to current COB base plate for packaging all selects metal basal board, it is only capable of presenting dome-geometry light source to greatest extent, for making the luminescence of LED energy greater angle, a lot of enterprises all have trial to be packaged LED on the transparent substrate, transparency carrier mainly has glass, a PC etc., but due to their heat conduction and heat radiation poor effect and be difficult to make electrode, printed circuit etc. herein above and be abandoned and be applied to LED chip COB encapsulation field。Adopting transparency carrier through improving some enterprise, by electrically conducting between sputter ITO circuit realiration chip and chip on transparency carrier, what transparent characteristic will not stop LED chip simultaneously goes out light。Owing to technical process relating to dry etching equipment, therefore complex technical process, relatively costly。
Summary of the invention
For the technical problem existed in prior art, the invention aims to simplify the product of prior art, replace ITO with copper, by direct for copper sputter on the transparent substrate, make a kind of chip package base plate。
In order to realize object above, the present invention is achieved through the following technical solutions:
A kind of chip package base plate, including substrate layer, sputtered layer and protective layer；Described sputtered layer deposits on the substrate layer, and protective layer overlays in sputtered layer；The material of described substrate layer is glass or polymer, and the material of described sputtered layer is copper alloy, and the material of described protective layer is metal or metal-oxide。
Further, the material of described substrate layer is PET(polyethylene terephthalate), PI(polyimides), PC(Merlon), PMMA(polymethyl methacrylate), COC(cyclic olefine copolymer), TCA(Triafol T) or sapphire。
Further, described sputtered layer distribution copper conductor circuit, the width of described copper conductor less than 4 microns, the spaced 50-100 micron of each copper conductor。
Further, the thickness of described substrate layer is 15-250 micron, it is preferable that 25-75 micron。
Further, the thickness of described sputtered layer is 0.03-1.5 micron, it is preferable that 0.05-0.5 micron。
Further, described protective layer thickness is the 30-40% of described sputtered layer thickness。
The chip package base plate of the present invention employs the conductive material copper more relatively inexpensive than transparent substrate, and there is the circuit diagram of particular design, there is high impact properties and the performance of low all-in resistance, can significantly save production cost, improve production efficiency, it is favorably improved the packaging efficiency of follow-up chip, and then makes subsequent product more stable, thus there is high visibility and cost competitiveness。
Accompanying drawing explanation
Fig. 1 is the structural representation of chip package base plate of the present invention。
Wherein, 1. substrate layer, 2. sputtered layer, 3. protective layer。
Detailed description of the invention
In order to make those skilled in the art be more fully understood that technical scheme, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail。
Referring to Fig. 1, the chip package base plate of the present invention, including substrate layer, sputtered layer and protective layer；Described sputtered layer deposits on the substrate layer, and protective layer overlays in sputtered layer；The material of described substrate layer is glass or polymer, and the material of described sputtered layer is copper alloy, and the material of described protective layer is metal or metal-oxide, and described sputter adopts the pulse power to carry out, and operation voltage is between 400 volts to 700 volts。
The chip package base plate preparation technology of the present invention mainly comprises the steps:
1, select substrate: glass, PET(polyethylene terephthalate), PI(polyimides), PC(Merlon), PMMA(polymethyl methacrylate), COC(cyclic olefine copolymer), TCA(Triafol T) or sapphire。
Select target: copper alloy, purity is good, and quality is even, bubble-free, and surfacing is bright and clean。
2, sputter: sputter substrate, this technological requirement vacuum is at about 1 × 10-3Torr, namely noble gas argon (Ar) it is filled with under the vacuum state of 1.3 × 10-3Pa, and between plastic substrate or glass (anode) and metal targets (negative electrode), apply high voltage direct current, owing to glow discharge (glowdischarge) produces charged particle bombardment target material surface, (namely target enters gas phase to make it sputter entrance gas phase, bombard), produce plasma, the atom of metal targets is driven out of by plasma, is deposited on plastic substrate。In the application, being that by the mode of sputter, metal material of copper is attached to board substrate plate surface, the thickness of sputtered layer is about 0.03 ~ 1.5 μm, and sputter can adopt the sputtering process of routine。The purpose adopting sputter has following 3 points:
(1) if directly adopting plated film technique to be electroplated onto on substrate by copper wire, copper material adhesive force is inadequate, it is impossible to pass through thermal shock test, the problem that there is reliability, and adopt the reliability of sputtering way higher, it have been experienced that by after sputter, electroplating line can pass through thermal shock test。
(2) metal of sputter can play electric action in electroplating process；The circuit board of this mode, without additional designs electroplate lead wire, contributes to reducing cabling area, it is achieved the miniaturization of product。
(3) sputtered metal layer of substrate surface can play the effect of buffering when being subject to thermal shock。
3. cover protective layer on sputtered layer surface。
Embodiment 1
Above-mentioned chip package base plate, wherein said substrate layer is PET, and thickness is 20 microns, and described sputtered layer thickness is 0.05 micron, and described protective layer is copper, and thickness is 0.02 micron；Described sputtered layer distribution copper conductor circuit, the width of described copper conductor is less than 4 microns, and spaced 50 microns of each copper conductor, described sputter adopts the pulse power to carry out, and operates voltage 400 volts。
Embodiment 2
Above-mentioned chip package base plate; wherein said substrate layer is PET; thickness is 200 microns, and described sputtered layer thickness is 1.5 microns, and described protective layer is rustless steel; thickness is 0.5 micron; described sputtered layer distribution copper conductor circuit, the width of described copper conductor less than 4 microns, spaced 100 microns of each copper conductor; described sputter adopts the pulse power to carry out, and operates voltage 700 volts。
Embodiment 3
Above-mentioned chip package base plate; wherein said substrate layer is PI; thickness is 50 microns; described sputtered layer thickness is 0.5 micron, and described protective layer thickness is 0.15 micron, described sputtered layer distribution copper conductor circuit; the width of described copper conductor is less than 4 microns; spaced 75 microns of each copper conductor, described sputter adopts the pulse power to carry out, and operates voltage 550 volts。
Embodiment 4
The chip package base plate of the above embodiments 1, is different in that described substrate layer is PC, and thickness is 50 microns, and described sputtered layer thickness is 0.5 micron, and described protective layer thickness is 0.15 micron, and described sputter adopts the pulse power to carry out, and operates voltage 600 volts。
Embodiment 5
The chip package base plate of the above embodiments 2, is different in that described substrate layer is PMMA, and thickness is 50 microns, and described sputtered layer thickness is 0.5 micron, and described protective layer thickness is 0.15 micron, described sputtering operation voltage 500 volts。
Embodiment 6
The chip package base plate of the above embodiments 2, is different in that described substrate layer is TCA, and thickness is 50 microns, and described sputtered layer thickness is 0.5 micron, and described protective layer thickness is 0.15 micron。
Embodiment 7
The chip package base plate of the above embodiments 3, is different in that described substrate layer is sapphire, and thickness is 20 microns, and described sputtered layer thickness is 0.05 micron, and described protective layer thickness is 0.02 micron。
Embodiment 8
The chip package base plate of the above embodiments 3, is different in that described substrate layer is glass, and thickness is 20 microns, and described sputtered layer thickness is 0.05 micron, and described protective layer thickness is 0.02 micron。
It is last it should be noted that, embodiment of above is only in order to illustrate that technical scheme is not intended to limit。Equivalent replacement is carried out it should be understood by a person of ordinary skill in the art that the specific embodiment of the present invention can be modified or to portion of techniques feature；Without deviating from the spirit of technical solution of the present invention, it all should be encompassed in the middle of the technical scheme scope that the present invention is claimed。
Claims (8)
1. a chip package base plate, it is characterised in that include substrate layer, sputtered layer and protective layer；Described sputtered layer deposits on the substrate layer, and protective layer overlays in sputtered layer；The material of described substrate layer is glass or polymer, and the material of described sputtered layer is copper alloy, and the material of described protective layer is metal or metal-oxide。
2. chip package base plate according to claim 1, it is characterized in that, the material of described substrate layer is PET(polyethylene terephthalate), PI(polyimides), PC(Merlon), PMMA(polymethyl methacrylate), COC(cyclic olefine copolymer), TCA(Triafol T) or sapphire。
3. chip package base plate according to claim 1, it is characterised in that described sputtered layer distribution copper conductor circuit, the width of described copper conductor less than 4 microns, the spaced 50-100 micron of each copper conductor。
4. chip package base plate according to claim 1, it is characterised in that the thickness of described substrate layer is 15-250 micron。
5. chip package base plate according to claim 1 or 4, it is characterised in that the thickness of described substrate layer is 25-75 micron。
6. chip package base plate according to claim 1, it is characterised in that the thickness of described sputtered layer is 0.03-1.5 micron。
7. chip package base plate according to claim 1 or 6, it is characterised in that the thickness of described sputtered layer is 0.05-0.5 micron。
8. chip package base plate according to claim 1, it is characterised in that described protective layer thickness is the 30-40% of described sputtered layer thickness。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610135396.XA CN105702813A (en) | 2016-03-10 | 2016-03-10 | Chip package substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610135396.XA CN105702813A (en) | 2016-03-10 | 2016-03-10 | Chip package substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105702813A true CN105702813A (en) | 2016-06-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610135396.XA Pending CN105702813A (en) | 2016-03-10 | 2016-03-10 | Chip package substrate |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017925A (en) * | 2006-02-09 | 2007-08-15 | 晟辉科技股份有限公司 | The making method of the thin film antenna |
| CN101572997A (en) * | 2008-04-29 | 2009-11-04 | 汉达精密电子(昆山)有限公司 | Method for forming conducting wire on insulated heat-conducting metal substrate in a vacuum sputtering way |
| CN101993032A (en) * | 2009-08-14 | 2011-03-30 | 京东方科技集团股份有限公司 | Method for manufacturing microstructural film pattern and TFT-LCD array substrate |
| CN105039910A (en) * | 2015-08-14 | 2015-11-11 | 陕西煤业化工技术研究院有限责任公司 | Flexible transparent conducting thin film |
| CN205582966U (en) * | 2016-03-10 | 2016-09-14 | 上海万寅安全环保科技有限公司 | Chip package base plate |
-
2016
- 2016-03-10 CN CN201610135396.XA patent/CN105702813A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017925A (en) * | 2006-02-09 | 2007-08-15 | 晟辉科技股份有限公司 | The making method of the thin film antenna |
| CN101572997A (en) * | 2008-04-29 | 2009-11-04 | 汉达精密电子(昆山)有限公司 | Method for forming conducting wire on insulated heat-conducting metal substrate in a vacuum sputtering way |
| CN101993032A (en) * | 2009-08-14 | 2011-03-30 | 京东方科技集团股份有限公司 | Method for manufacturing microstructural film pattern and TFT-LCD array substrate |
| CN105039910A (en) * | 2015-08-14 | 2015-11-11 | 陕西煤业化工技术研究院有限责任公司 | Flexible transparent conducting thin film |
| CN205582966U (en) * | 2016-03-10 | 2016-09-14 | 上海万寅安全环保科技有限公司 | Chip package base plate |
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Application publication date: 20160622 |