CN104979441A - LED chip, manufacturing method thereof, and LED display device with same - Google Patents
LED chip, manufacturing method thereof, and LED display device with same Download PDFInfo
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- CN104979441A CN104979441A CN201410131570.4A CN201410131570A CN104979441A CN 104979441 A CN104979441 A CN 104979441A CN 201410131570 A CN201410131570 A CN 201410131570A CN 104979441 A CN104979441 A CN 104979441A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 89
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 238000000034 method Methods 0.000 claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000010030 laminating Methods 0.000 claims description 5
- 229910052594 sapphire Inorganic materials 0.000 claims description 5
- 239000010980 sapphire Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000004408 titanium dioxide Substances 0.000 claims description 4
- 229910001020 Au alloy Inorganic materials 0.000 claims description 3
- 241000218202 Coptis Species 0.000 claims description 3
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000003353 gold alloy Substances 0.000 claims description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000000605 extraction Methods 0.000 description 7
- 238000003466 welding Methods 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Abstract
The invention discloses an LED chip, a manufacturing method thereof and an LED display device with same. The LED chip comprises the components of a transparent substrate; an N-type semiconductor layer which is arranged on one surface of the substrate, wherein the surface, which opposes the transparent substrate, of the N-type semiconductor layer comprises a first area and a second area; a cathode which is arranged at the first area, wherein a first reflecting layer is arranged between the cathode and the first area; a multi-quantum well active layer and a P-type semiconductor layer which are arranged in the second area, wherein the multi-quantum well active layer is arranged between the N-type semiconductor layer and the P-type semiconductor layer; and an anode which is arranged on the surface of the P-type semiconductor layer, wherein the surface of the P-type semiconductor layer opposes the multi-quantum well active layer. A second reflecting layer is arranged between the anode and the P-type semiconductor layer. The second reflecting layer is insulated from the first reflecting layer. The LED chip, the manufacturing method thereof and the LED display device provided by the technical solution have improved light emitting efficiency of the LED chip.
Description
Technical field
The present invention relates to semiconductor device fabrication process technical field, more particularly, relate to a kind of LED chip and method for packing thereof and LED display.
Background technology
Light-emitting diode (Light Emitting Diode, being called for short LED) device is a kind of energy conversion device converting electrical energy into luminous energy, has the advantages such as operating voltage is low, power consumption is few, stable performance, life-span length, shock resistance, vibration resistance is strong, lightweight, volume is little, cost is low, luminescence response is fast.Along with the day by day maturation of technology, LED is widely used in the numerous areas such as illumination, display backlight module and signal lamp.
Light extraction efficiency is the important parameter weighing LED chip, conventional LED chip is generally packed LED chip, the P electrode of its LED component and N electrode and luminous zone are arranged on the same side, the light part of luminous zone injection is absorbed by the bonding wire of electrode and electrode or blocks, thus reduces the light outgoing efficiency of LED chip.The light extraction efficiency how improving LED chip is that LED chip prepares industry problem demanding prompt solution.
Summary of the invention
For solving the problems of the technologies described above, the invention provides a kind of LED chip and preparation method thereof and LED display, to improve the light extraction efficiency of LED chip.
For achieving the above object, the invention provides following technical scheme:
A kind of LED chip, this LED chip comprises:
Transparent substrates;
Be arranged on the n type semiconductor layer on described substrate one surface, the surface that described n type semiconductor layer deviates from described transparent substrates comprises: first area and second area;
Be arranged on the negative pole of described first area, between described negative pole and described first area, be provided with the first reflector;
Be arranged on multiple quantum well active layer and the p type semiconductor layer of described second area, described multiple quantum well active layer is between described n type semiconductor layer and described p type semiconductor layer;
Being arranged on the positive pole that described p type semiconductor layer deviates from the surface of described multiple quantum well active layer, being provided with the second reflector between described positive pole and described p type semiconductor layer, insulate in described second reflector and described first reflector.
Preferably, in above-mentioned LED chip, described negative pole deviates from the surface that the surface of described transparent substrates and described positive pole deviate from described transparent substrates and is in same plane.
Preferably, in above-mentioned LED chip, also comprise:
Cover described positive pole and deviate from the insulating barrier that the surface of described transparent substrates and described negative pole deviate from the surface of described transparent substrates.
Preferably, in above-mentioned LED chip, described substrate is Sapphire Substrate.
Preferably, in above-mentioned LED chip, described negative pole and described just very silver electrode or nickel gold alloy electrodes.
Preferably, in above-mentioned LED chip, the surface that described negative pole is relative with described first reflector is greater than the surface relative with described negative pole, described first reflector, and the surface that described positive pole is relative with described second reflector is greater than the surface relative with described positive pole, described second reflector.
Preferably, in above-mentioned LED chip, described first reflector and described second reflector are silicon dioxide layer or titanium dioxide layer.
Present invention also offers a kind of LED display, this LED display comprises:
Substrate;
Fixing multiple interconnected LED chip on the substrate;
Wherein, described LED chip is the LED chip described in any one execution mode above-mentioned; The substrate of described LED chip deviates from described substrate and arranges.
Preferably, in above-mentioned LED display, described LED chip is connected or parallel with one another mutually.
Preferably, in above-mentioned LED display, interconnected by bonding wire between described LED chip.
Preferably, in above-mentioned LED display, described bonding wire is gold thread.
Present invention also offers a kind of manufacture method of LED chip, this manufacture method comprises:
One transparent substrates is provided;
Form n type semiconductor layer on described transparent substrates one surface, the surface that described n type semiconductor layer deviates from described transparent substrates comprises: first area and second area;
Form multiple quantum well active layer and p type semiconductor layer at described second area, described multiple quantum well active layer is between described second area and described p type semiconductor layer;
Forming the first reflector of being positioned at described first area and be positioned at the second reflector that described p type semiconductor layer deviates from the surface of described multiple quantum well active layer, insulate in described first reflector and described second reflector;
Form negative pole and positive pole, wherein, described negative pole is positioned at the surface that described first reflector deviates from described n type semiconductor layer, and described positive pole is positioned at the surface that described second reflector deviates from described p type semiconductor layer.
Preferably, in above-mentioned manufacture method, the forming process of described multiple quantum well active layer and p type semiconductor layer comprises:
Form the Multiple-quantum active layer covering described n type semiconductor layer and deviate from the surface of described transparent substrates;
Form the p type semiconductor layer covering described Multiple-quantum active layer and deviate from the surface of described n type semiconductor layer;
Etching removes the Multiple-quantum active layer relative with described first area and p type semiconductor layer.
Preferably, in above-mentioned manufacture method, the forming process in described first reflector and the second reflector comprises:
Form a reflecting medium layer, described dielectric layer covers described p type semiconductor layer and deviates from the surface of described multiple quantum well active layer and described first area;
Described dielectric layer is etched, the dielectric layer relative with described first area and the dielectric layer relative with described second area is insulated, and then forms described first reflector and described second reflector.
Preferably, in above-mentioned manufacture method, the forming process of described positive pole and described negative pole comprises:
The negative metal layer deviating from the surface laminating setting thickness of described n type semiconductor layer in described first reflector, as described negative pole, deviates from the cathode metal layer of the surface laminating setting thickness of described p type semiconductor layer as described positive pole in described second reflector;
Wherein, described negative pole deviates from the surface that the surface of described transparent substrates and described positive pole deviate from described transparent substrates and is in same plane; Described positive pole and described negative insulation.
Preferably, in above-mentioned manufacture method, the forming process of described positive pole and described negative pole comprises:
Form metal level, described metal level covers described first reflector and deviates from the surface that the surface of described n type semiconductor layer and described second reflector deviate from described p type semiconductor layer;
Described metal level is etched, forms the negative pole relative with described first reflector and the positive pole relative with described second reflector;
Wherein, described negative pole deviates from the described transparent surface that sinks to the bottom and described positive pole and deviates from the described transparent surface sunk to the bottom and be in same plane; Described positive pole and described negative insulation.
Preferably, in above-mentioned manufacture method, also comprise:
Formed and cover described positive pole and deviate from the insulating barrier that the surface of described transparent substrates and described negative pole deviate from the surface of described transparent substrates.
As can be seen from technique scheme, LED chip provided by the invention provided by the present invention adopts the LED structure of upside-down mounting, n type semiconductor layer is set between transparent substrates and p type semiconductor layer, emergent light points to n type semiconductor layer by p type semiconductor layer, via described transparent substrates outgoing, negative pole and positive pole are arranged on shady face, avoid bonding wire the blocking and absorbing light of positive pole, negative pole and both positive and negative polarity, thus improve light extraction efficiency.Meanwhile, by arranging described first reflector and the second reflector, further increase by the outgoing efficiency of described transparent substrates emergent light.LED display provided by the invention comprises above-mentioned LED chip, therefore has higher light outgoing efficiency.The manufacture method of LED chip provided by the invention may be used for making the above-mentioned LED chip with high light outgoing efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 provides a kind of structural representation of LED chip for the embodiment of the present invention;
Fig. 2 provides a kind of structural representation of LED display for the embodiment of the present invention;
The schematic flow sheet of a kind of LED chip manufacture method that Fig. 3-Fig. 8 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment one
Present embodiments provide a kind of LED chip, with reference to figure 1, described LED chip comprises:
Transparent substrates 1;
Be arranged on the n type semiconductor layer 2 on described substrate 1 one surface, the surface that described n type semiconductor layer 2 deviates from described transparent substrates 1 comprises: first area and second area;
Be arranged on the negative pole 3 of described first area, between described negative pole 3 and described first area, be provided with the first reflector 4;
Be arranged on multiple quantum well active layer 5 and the p type semiconductor layer 6 of described second area, described multiple quantum well active layer 5 is between described n type semiconductor layer 2 and described p type semiconductor layer 6;
Be arranged on the positive pole 7 that described p type semiconductor layer 6 deviates from the surface of described multiple quantum well active layer 5, be provided with the second reflector 8 between described positive pole 7 and described p type semiconductor layer 6, described second reflector 8 insulate 4 with described first reflector.
In order to reduce LED chip be encapsulated as LED display time, the contact stress between LED chip and substrate, arranges negative pole 3 and deviates from the surface that the surface of described transparent substrates 1 and described positive pole 7 deviate from described transparent substrates 1 and be in same plane.
Described LED chip is also provided with insulating barrier 9, and described insulating barrier 9 covers described positive pole 7 and deviates from the surface that the surface of described transparent substrates 1 and described negative pole 3 deviate from described transparent substrates 1.Described insulating barrier 9 is set, when carrying out encapsulation to described LED chip and forming LED display, described LED chip directly can be fixed on metallic substrates, on the one hand, to increase heat radiation, on the other hand, can be interconnected by bonding wire between LED chip, what existing die bond bonding equipment can be used to carry out between LED chip is interconnected, does not change packaging technology.And die bond bonding equipment technical maturity, can ensure that the yield that LED chip encapsulates is higher.
In LED chip described in the present embodiment, adopt Sapphire Substrate, sapphire material has higher light transmission and conductive coefficient, can ensure that LED component has higher light extraction efficiency and good radiating efficiency; The good silver electrode of electric conductivity or nickel gold alloy electrodes is adopted to prepare described positive pole and negative pole, to improve light extraction efficiency.
In order to welding kesistance when reducing bonding wire welding is to improve the generation rate of light, arrange described negative pole 3 surface relative with described first reflector 4 and be greater than the surface relative with described negative pole 3, described first reflector 4, the surface that described positive pole 7 is relative with described second reflector 8 is greater than the surface relative with described positive pole 7, described second reflector 8.Wherein, described first reflector 4 and the second reflector 8 can be silicon dioxide layer or titanium dioxide layer.
LED chip described in the present embodiment adopts the LED structure of upside-down mounting, n type semiconductor layer is set between transparent substrates and p type semiconductor layer, emergent light points to n type semiconductor layer by p type semiconductor layer, via described transparent substrates outgoing, negative pole and positive pole are arranged on shady face, avoid bonding wire the blocking and absorbing light of positive pole, negative pole and both positive and negative polarity, thus improve light extraction efficiency.
Simultaneously, by arranging described first reflector and the second reflector, the reflection of the light of downward outgoing through described first reflector and described second reflector through the upwards outgoing of described transparent substrates, can be further increased by the outgoing efficiency of described transparent substrates emergent light.
Embodiment two
Based on above-described embodiment, present embodiments provide a kind of LED display, the multiple interconnected LED chip that described LED display comprises substrate and arranges on the substrate, the substrate of described LED chip deviates from described substrate and arranges.Described LED chip can for the LED chip in embodiment one described in any one execution mode.
Described LED chip can be connected or parallel with one another mutually.Can, by the mode of welding, bonding wire be adopted to realize series connection between LED chip or parallel connection.
Comprise with reference to LED display shown in figure 2, Fig. 2: substrate B and the multiple A of LED chip be as shown in fig. 1 fixed on described substrate B.
The surface that described LED chip A is relative with described substrate B is provided with insulating barrier, therefore, metal substrate can be adopted as described substrate B; And can be connected by bonding wire C between LED chip A, gold thread that resistance is less can be adopted as described bonding wire, to reduce welding kesistance.At described substrate B surface-coated packaging plastic after welding completes, packaging protection can be carried out to described LED chip A.
LED display described in the present embodiment adopts the LED chip described in embodiment one, and therefore, described LED display has higher light outgoing efficiency.
Embodiment three
The present embodiment provides a kind of manufacture method of LED chip, and this manufacture method comprises:
Step S11: with reference to figure 3, provides a transparent substrates 1.
Described substrate 1 can for having the Sapphire Substrate of high transmission rate and conductive coefficient.
Step S12: with reference to figure 4, form n type semiconductor layer 2 on a surface of described transparent substrates 1, the surface that described n type semiconductor layer 2 deviates from described transparent substrates comprises: first area and second area.
Described n type semiconductor layer can be formed by depositing operation.
Step S13: with reference to figure 5, form multiple quantum well active layer and p type semiconductor layer at described second area, described multiple quantum well active layer is between described second area and described p type semiconductor layer.
The forming process of described multiple quantum well active layer and p type semiconductor layer comprises: first, as shown in Figure 6, forms the Multiple-quantum active layer covering described n type semiconductor layer and deviate from the surface of described transparent substrates; Then, the p type semiconductor layer covering described Multiple-quantum active layer and deviate from the surface of described n type semiconductor layer is formed; Finally, etching removes the Multiple-quantum active layer relative with described first area and p type semiconductor layer, forms structure as shown in Figure 5.
Step S14: with reference to figure 7, forming the first reflector 4 of being positioned at described first area and be positioned at the second reflector 8 that described p type semiconductor layer 6 deviates from the surface of described multiple quantum well active layer 5, insulate with described second reflector 8 in described first reflector 4.
The forming process in described first reflector 4 and the second reflector 8 comprises: first, form a reflecting medium layer, described dielectric layer covers described p type semiconductor layer and deviates from the surface of described multiple quantum well active layer and described first area; Described dielectric layer is etched, the dielectric layer relative with described first area and the dielectric layer relative with described second area are insulated, and then form described first reflector 4 and described second reflector 8.Described reflecting medium layer can be silicon dioxide layer or titanium dioxide layer.
Step S15: with reference to figure 8, form negative 3 and positive pole 7, wherein, described negative pole 3 is positioned at the surface that described first reflector 4 deviates from described n type semiconductor layer 2, and described positive pole 7 is positioned at the surface that described second reflector 8 deviates from described p type semiconductor layer 6.
Described negative pole 3 insulate with described positive pole 7.Contact stress during in order to reduce and balance LED chip encapsulation, described negative pole 3 deviates from the surface that the surface of described transparent substrates 1 and positive pole 7 deviate from described transparent substrates 1 and is in same plane.
In order to reduce the welding kesistance between electrode, arrange described negative pole 3 surface relative with described first reflector 4 and be greater than the surface relative with described negative pole 3, described first reflector 4, the surface that described positive pole 7 is relative with described second reflector 8 is greater than the surface relative with described positive pole 7, described second reflector 8.
The forming process of described positive pole and described negative pole can be: the surface deviating from described n type semiconductor layer in described first reflector fit set thickness negative metal layer as described negative pole, deviate from the cathode metal layer of the surface laminating setting thickness of described p type semiconductor layer in described second reflector as described positive pole.
The surface that thickness by controlling described cathode metal layer and described cathode metal layer makes the two deviate from described transparent substrates is in same plane.
The forming process of described positive pole and described negative pole can also be: form metal level, and described metal level covers described first reflector and deviates from the surface that the surface of described n type semiconductor layer and described second reflector deviate from described p type semiconductor layer; Described metal level is etched, forms the negative pole relative with described first reflector and the positive pole relative with described second reflector.
Can form described metal level by depositing operation, and the surface that both described positive pole and negative pole can be made to deviate from described transparent substrates by the deposit thickness controlling first area and second area metal level is in same plane.The mould of setting can be adopted to be greater than to prepare area the positive pole that the negative pole in the first reflector and area be greater than the second reflector.
Metal substrate encapsulation can be applicable to make described LED chip, and adopt welding manner to realize between LED chip interconnected, described manufacture method also comprises: formed and cover described positive pole and deviate from the insulating barrier that the surface of described transparent substrates and described negative pole deviate from the surface of described transparent substrates.The LED chip of final formation as shown in Figure 1.
Manufacture method described in the present embodiment can prepare the LED chip with high light outgoing efficiency.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (17)
1. a LED chip, is characterized in that, comprising:
Transparent substrates;
Be arranged on the n type semiconductor layer on described substrate one surface, the surface that described n type semiconductor layer deviates from described transparent substrates comprises: first area and second area;
Be arranged on the negative pole of described first area, between described negative pole and described first area, be provided with the first reflector;
Be arranged on multiple quantum well active layer and the p type semiconductor layer of described second area, described multiple quantum well active layer is between described n type semiconductor layer and described p type semiconductor layer;
Being arranged on the positive pole that described p type semiconductor layer deviates from the surface of described multiple quantum well active layer, being provided with the second reflector between described positive pole and described p type semiconductor layer, insulate in described second reflector and described first reflector.
2. LED chip according to claim 1, is characterized in that, described negative pole deviates from the surface that the surface of described transparent substrates and described positive pole deviate from described transparent substrates and is in same plane.
3. LED chip according to claim 1, is characterized in that, also comprises:
Cover described positive pole and deviate from the insulating barrier that the surface of described transparent substrates and described negative pole deviate from the surface of described transparent substrates.
4. LED chip according to claim 1, is characterized in that, described substrate is Sapphire Substrate.
5. LED chip according to claim 1, is characterized in that, described negative pole and described just very silver electrode or nickel gold alloy electrodes.
6. LED chip according to claim 1, it is characterized in that, the surface that described negative pole is relative with described first reflector is greater than the surface relative with described negative pole, described first reflector, and the surface that described positive pole is relative with described second reflector is greater than the surface relative with described positive pole, described second reflector.
7. LED chip according to claim 1, is characterized in that, described first reflector and described second reflector are silicon dioxide layer or titanium dioxide layer.
8. a LED display, is characterized in that, comprising:
Substrate;
Fixing multiple interconnected LED chip on the substrate;
Wherein, described LED chip is the LED chip described in any one of claim 1-7; The substrate of described LED chip deviates from described substrate and arranges.
9. LED display according to claim 8, is characterized in that, described LED chip is connected or parallel with one another mutually.
10. LED display according to claim 8, is characterized in that, interconnected by bonding wire between described LED chip.
11. LED display according to claim 8, is characterized in that, described bonding wire is gold thread.
The manufacture method of 12. 1 kinds of LED chips, is characterized in that, comprising:
One transparent substrates is provided;
Form n type semiconductor layer on described transparent substrates one surface, the surface that described n type semiconductor layer deviates from described transparent substrates comprises: first area and second area;
Form multiple quantum well active layer and p type semiconductor layer at described second area, described multiple quantum well active layer is between described second area and described p type semiconductor layer;
Forming the first reflector of being positioned at described first area and be positioned at the second reflector that described p type semiconductor layer deviates from the surface of described multiple quantum well active layer, insulate in described first reflector and described second reflector;
Form negative pole and positive pole, wherein, described negative pole is positioned at the surface that described first reflector deviates from described n type semiconductor layer, and described positive pole is positioned at the surface that described second reflector deviates from described p type semiconductor layer.
13. manufacture methods according to claim 12, is characterized in that, the forming process of described multiple quantum well active layer and p type semiconductor layer comprises:
Form the Multiple-quantum active layer covering described n type semiconductor layer and deviate from the surface of described transparent substrates;
Form the p type semiconductor layer covering described Multiple-quantum active layer and deviate from the surface of described n type semiconductor layer;
Etching removes the Multiple-quantum active layer relative with described first area and p type semiconductor layer.
14. manufacture methods according to claim 12, is characterized in that, the forming process in described first reflector and the second reflector comprises:
Form a reflecting medium layer, described dielectric layer covers described p type semiconductor layer and deviates from the surface of described multiple quantum well active layer and described first area;
Described dielectric layer is etched, the dielectric layer relative with described first area and the dielectric layer relative with described second area is insulated, and then forms described first reflector and described second reflector.
15. manufacture methods according to claim 12, is characterized in that, the forming process of described positive pole and described negative pole comprises:
The negative metal layer deviating from the surface laminating setting thickness of described n type semiconductor layer in described first reflector, as described negative pole, deviates from the cathode metal layer of the surface laminating setting thickness of described p type semiconductor layer as described positive pole in described second reflector;
Wherein, described negative pole deviates from the surface that the surface of described transparent substrates and described positive pole deviate from described transparent substrates and is in same plane; Described positive pole and described negative insulation.
16. manufacture methods according to claim 12, is characterized in that, the forming process of described positive pole and described negative pole comprises:
Form metal level, described metal level covers described first reflector and deviates from the surface that the surface of described n type semiconductor layer and described second reflector deviate from described p type semiconductor layer;
Described metal level is etched, forms the negative pole relative with described first reflector and the positive pole relative with described second reflector;
Wherein, described negative pole deviates from the described transparent surface that sinks to the bottom and described positive pole and deviates from the described transparent surface sunk to the bottom and be in same plane; Described positive pole and described negative insulation.
17. manufacture methods according to claim 12, is characterized in that, also comprise:
Formed and cover described positive pole and deviate from the insulating barrier that the surface of described transparent substrates and described negative pole deviate from the surface of described transparent substrates.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105425469A (en) * | 2016-01-04 | 2016-03-23 | 京东方科技集团股份有限公司 | Backlight module and manufacturing method and display device thereof |
| CN110178230A (en) * | 2019-02-03 | 2019-08-27 | 泉州三安半导体科技有限公司 | Light emitting device |
| TWI784361B (en) * | 2019-12-02 | 2022-11-21 | 億光電子工業股份有限公司 | LED light emitting device and manufacturing method thereof |
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| CN103390711A (en) * | 2013-07-18 | 2013-11-13 | 江苏中谷光电股份有限公司 | LED chip with electrode reflective layers and manufacture method thereof |
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| WO2017117933A1 (en) * | 2016-01-04 | 2017-07-13 | Boe Technology Group Co., Ltd. | Backlight module, fabrication method, and display apparatus |
| CN105425469B (en) * | 2016-01-04 | 2018-09-11 | 京东方科技集团股份有限公司 | A kind of backlight module and preparation method thereof, display device |
| CN110178230A (en) * | 2019-02-03 | 2019-08-27 | 泉州三安半导体科技有限公司 | Light emitting device |
| TWI784361B (en) * | 2019-12-02 | 2022-11-21 | 億光電子工業股份有限公司 | LED light emitting device and manufacturing method thereof |
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