CN205016507U - 电子器件 - Google Patents

电子器件 Download PDF

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CN205016507U
CN205016507U CN201520727622.4U CN201520727622U CN205016507U CN 205016507 U CN205016507 U CN 205016507U CN 201520727622 U CN201520727622 U CN 201520727622U CN 205016507 U CN205016507 U CN 205016507U
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wafer
chip
front surface
electronic device
protection wafer
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M·索里厄尔
K·萨克斯奥德
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STMicroelectronics Grenoble 2 SAS
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Abstract

本申请涉及电子器件。其中在基体晶片(2)的顶部上安装集成电路芯片(3)，并且在所述芯片的顶部上安装保护晶片(12)，围绕所述芯片和保护晶片并且在基体晶片的前表面的外围部分上形成密封块(18)。所述密封块包括：第一密封环(19)，其围绕芯片和保护晶片而布置，具有相对于保护晶片的前表面而突出的环形镶边(20)，并且形成相对于所述突出的环形镶边而凹陷的外围沟槽(24)；以及第二密封环(25)，其填充所述第一密封环的外围沟槽(24)。根据本实用新型的方案，能够提供一种改进的集体制造而产生的电子器件，使得密封块的前表面基本上行进在保护晶片的前表面的平面中。

Description

电子器件
技术领域
本实用新型涉及包括集成电路芯片的电子器件的领域。
背景技术
根据已知的构造，电子器件包括堆叠的构件，该构件包括基体晶片、安装在该基体晶片的前表面上并且包括在其前表面内的传感器的集成电路芯片、以及安装在该前表面的顶部上的保护晶片。通常，该堆叠的构件由密封块所围绕。
通常由集体制造而产生的这种电子器件特别地展现了在使得密封块的前表面基本上行进在保护晶片的前表面的平面中的制造中的困难。
实用新型内容
本实用新型特别地致力于解决这些困难。
根据一个实施例，提供一种电子器件，包括：基体晶片，具有前表面；集成电路芯片，其背表面被固定到所述基体晶片的前表面上；保护晶片，位于所述芯片的顶部上；以及密封块，围绕所述芯片和所述保护晶片并且在所述基体晶片的前表面的外围部分上布置，所述密封块包括：第一密封环，围绕所述芯片和所述保护晶片而布置，具有相对于所述保护晶片的前表面而朝前突出并且位于包括所述保护晶片的外围边沿的环形区域内的环形镶边，并且形成相对于所述突出的环形镶边而凹陷的外围沟槽；以及第二密封环，填充所述第一密封环的外围沟槽。
所述突出的环形镶边可以延伸在所述保护晶片的前表面的外围区域上方。
所述第二密封环可以具有基本上位于所述突出的环形镶边的尖峰的平面中的前表面。
电子器件可以包括用于在所述芯片上方一定距离处安装所述保护晶片并且用于填充在所述保护晶片和所述芯片之间创建的自由空间的机构。
所述芯片可以包括传感器，所述传感器与未被所述突出的环形镶边覆盖的所述保护晶片的中心区域相对地延伸。
所述传感器可以为光学传感器并且所述保护晶片可以为透明的。
根据本实用新型的方案，能够提供一种改进的集体制造而产生的电子器件，使得密封块的前表面基本上行进在保护晶片的前表面的平面中。
附图说明
现在将通过在附图中图示的非限制性的例子对电子器件和制造该电子器件的方式进行描述，其中：
图1示出了包括芯片和保护晶片的电子器件的横截面；以及
图2到图6示出了与针对图1中的电子器件的制造步骤对应的构件的横截面。
具体实施方式
如图1中所图示的，电子器件1包括在堆叠中的形成基体和用于电气连接的晶片2以及其背表面4通过粘合剂薄层安装在基体晶片2的前表面5上的集成电路芯片3。例如为正方形的背表面4的表面面积小于例如为正方形的前表面5的表面面积。芯片3安装在基体晶片2的中间，其外围边沿分别为平行的。
芯片3在其前表面6的中心区域中包括例如为光学传感器的传感器7。
形成基体的晶片2具有电气连接网络8。芯片3通过多个电气连接接线9连接到这个电气连接网络8，所述电气连接接线9在芯片3的外围边沿和基体晶片2的外围边沿之间连接布置在芯片3的前表面6的外围区域上的前凸缘10和布置在基体晶片2的前表面5的外围区域上的电气连接网络8的前凸缘11。
电子器件1进一步包括大体上为透明的保护晶片12，该保护晶片12堆叠在芯片3上并且经由附接和填充机构13被固定在离芯片3的前表面6一定距离处。保护晶片12的外围边沿在芯片3的包括电气连接凸缘10的外围区域的内部、平行于芯片3的外围边沿而行进。
所述附接和填充机构13在传感器7和芯片3的前表面6的前凸缘10之间、并且在离所述传感器7和芯片3的前表面6的前凸缘10一定距离处且在保护晶片12的背表面14的外围区域上方行进，从而芯片3的前表面6具有包括传感器7的中心区域15，该中心区域15面朝保护晶片12的背表面14的中心区域16并且位于距离该中心区域16一定距离处，同时允许外围界定的自由空间17存在于这些区域15和16之间。
根据一个示例性实施例，所述附接和填充机构13可以包括粘合剂的环形带18，该环形带的形式为围绕着芯片3的前表面的中心区域15的开放环，其中该粘合剂可以包括固体间隔元素从而确保自由空间17的最小厚度以及保护晶片相对于芯片3的定位。
电子器件1进一步包括环形密封块18，该环形密封块围绕着芯片3和保护晶片12而布置，并且在基体晶片2的前表面5的外围部分上方且电气连接接线9掩埋在其中。该密封块18还围绕附接和填充机构13，因此在芯片3和保护晶片12之间的自由空间17得以保留。
密封块18的外围侧18a以及基体晶片2的相对应的外围侧2a分别在垂直于前述的基体晶片2的表面的平面中行进，因此电子器件1具有基本上为平行四边形平行六面体的形状。
密封块18包括围绕芯片3和保护晶片12以及也围绕附接和填充机构13并且在前述的基体晶片2的前表面5的外围部分上形成的第一密封环19，并且电气连接接线9掩埋在该第一密封环19中。
第一密封环19具有在保护晶片12的外围边沿的区域之内的环形镶边20，其相对于保护晶片12的前表面22向前方突出。根据所示出的例子，该突出的环形镶边20在保护晶片12的前表面22的狭窄外围区域21上方延伸。
第一密封环19形成了相对于突出的环形镶边20凹陷并且朝向外部以及朝向前方而外围地定向的外围沟槽24。由此，第一密封环19的外围侧19a形成了密封块18的外围侧18a的后部部分。
密封块18还包括第二密封环25，该第二密封环25填充了第一密封环19的外围沟槽24。
第二密封环25具有外围侧25a，该外围侧25a形成了密封块18的外围侧18a的前方部分并且具有基本上平行于基体晶片2的平坦前表面26，该前表面26基本上在与突出的环形镶边20的前尖峰27相同的平面中延伸并且其程度如该前尖峰27一般，以这样的方式使得第二密封环25构造了电子器件1的前角落。
根据所示出的例子，所述突出的环形镶边20留下了其位置与传感器7相对并且其表面面积大于该传感器7的表面面积的自由中心区域28。
根据一个变形的实施例，所述突出的环形镶边20可以形成在外侧并且其方式为相邻于保护晶片12的外围边沿。在这种情况下，保护晶片12的整个前表面22将保留为未被覆盖。
现在将参照图2到图6来描述一种制造电子器件1的方式。
如在图2中所描述的，着眼于集体制造，晶片2A被设置有多个相邻的位置E，其形式为正方形矩阵，在其中的每一个位置中都具有电气连接网络8。
集成电路芯片3被传送并且通过粘合剂薄层固定到晶片2A的位置E中的每一个位置的前表面上。
接着，如之前所描述地安装连接接线9。
接下来，如之前所描述的，通过传送并且固定在芯片3的顶部上并借助于附接和填充机构13进行安装，从而对保护晶片12进行安装。
由此，在位置E，分别包括芯片3以及保护晶片12的堆叠的构件29形成在基体晶片2A的部分的顶部上，这些部分在稍后的阶段对应于支撑的基体晶片2。
由此，存在行进在堆叠的构件29之间的通道30，在基体晶片2A的前表面32上的相对应的区域31前方，并且存在围绕着所有堆叠的构件29的该前表面31的外围区域33。
接下来，如图3所描述的，在基体晶片2A的所述表面32的外围区域33上形成外部外围阻挡物34，围绕着所述多个堆叠的构件29并且离该多个堆叠的构件29有一定距离。
为此目的，沉积诸如适合的粘合剂之类的材料的带，并且该材料例如在炉中被硬化。由此在位于外围的堆叠的构件29和外部外围阻挡物34之间创建了外围通道35。
接着，例如通过滴涂注射，将第一涂层材料19A沉积在通道30中并且在外围通道35中。
第一涂层材料19A以如下这样的方式进行沉积，即突出的环形镶边20A围绕着与将要形成的环形镶边20对应的保护晶片12而形成，并且在通道30以及外围通道35中且沿着外围通道35，基本上与将要形成的沟槽24的一半对应地形成凹陷的沟槽24A。
接着，执行该第一涂层材料19A的硬化。由此，在每一个位置E中形成第一密封环19。
所述硬化的第一涂层材料19A具有可形变的特别的属性。例如，所述第一涂层材料19A可以由在炉中被硬化的适合的粘合剂树脂制成。
接着，如图5所描述的，如上述所获得的构件放置在模具的两个板36和37之间，所述模具板36抵靠着基体晶片2A的背表面按压并且模具板37位于第一涂层材料19A的突出的镶边20A的尖峰27A的顶部上，从而创建了沿着这些尖峰27A的封闭区域。
在突出的镶边20A的侧上，所述模具板37包括压缩性材料的膜38。在模制位置中，第一涂层材料19A的突出的镶边20A具有穿透的趋势并且穿透进入可形变的膜38，由此创建了沿着突出的镶边20A的尖峰27A而建立的环形封闭区域。此外，所述可形变的膜38依靠在保护晶片12的前表面22上，由此还创建了局部封闭面。
由此，在沟槽24A和模具板37之间存在间隙40。
归功于所述第一涂层材料19A和膜38的可形变的属性，由模具板37施加在突出的镶边20A以及保护晶片12上从而获得保护晶片12相对于间隙40的隔离的压力在堆叠的构件29，尤其是在芯片3中，不会诱发应力或者诱发极小的应力。
外部外围阻挡物34具有高度从而使得其至少在其外围的部分上不会到达模具板37，其方式为存在至少一个外围通路39。
接着，通过经由模具外围上的至少一个地方进行注入，将第二涂层材料25A注入到模具中，从而填充空间35和40，该材料能够经由压力和毛细作用发生迁移。例如，第二涂层材料25A可以为能够在炉中被硬化的适合的粘合剂树脂。当然，外部外围阻挡物34以及模具的外围被设计为允许空气的注入和排出。
接着，执行第二涂层材料25A的硬化。由此，在每个位置E中形成第二密封环25。
接着，如图6所描述的，在脱模之后，后部电气连接镶边被安装42在电气连接网络8的后部凸缘上。
最后，将在每个位置E中获得的电子器件1进行划片，例如通过沿着位置E的矩阵的线42贯穿晶片2A以及涂层材料19A和25A进行锯切。
根据一个变形的实施例，基体晶片2可以由包括用于处理来自芯片3的信号的电子电路的芯片所取代。
本实用新型不限于上面所描述的例子。可以有各种实施例而不会偏离本实用新型的范围。

Claims (6)

1.一种电子器件，其特征在于，包括：
基体晶片，具有前表面，
集成电路芯片，其背表面被固定到所述基体晶片的前表面上，
保护晶片，位于所述芯片的顶部上，以及
密封块，围绕所述芯片和所述保护晶片并且在所述基体晶片的前表面的外围部分上布置，
所述密封块包括：
第一密封环，围绕所述芯片和所述保护晶片而布置，具有相对于所述保护晶片的前表面而朝前突出并且位于包括所述保护晶片的外围边沿的环形区域内的环形镶边，并且形成相对于所述突出的环形镶边而凹陷的外围沟槽，以及
第二密封环，填充所述第一密封环的外围沟槽。
2.根据权利要求1所述的电子器件，其特征在于，所述突出的环形镶边延伸在所述保护晶片的前表面的外围区域上方。
3.根据权利要求1所述的电子器件，其特征在于，所述第二密封环具有基本上位于所述突出的环形镶边的尖峰的平面中的前表面。
4.根据权利要求1所述的电子器件，其特征在于，包括用于在所述芯片上方一定距离处安装所述保护晶片并且用于填充在所述保护晶片和所述芯片之间创建的自由空间的机构。
5.根据权利要求1到4中任一项所述的电子器件，其特征在于，所述芯片包括传感器，所述传感器与未被所述突出的环形镶边覆盖的所述保护晶片的中心区域相对地延伸。
6.根据权利要求5所述的电子器件，其特征在于，所述传感器为光学传感器并且所述保护晶片为透明的。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105679717A (zh) * 2014-12-09 2016-06-15 意法半导体(格勒诺布尔2)公司 制造电子器件的方法以及具有双密封环的电子器件
CN107403862A (zh) * 2016-05-20 2017-11-28 厦门市三安光电科技有限公司 发光二极管封装结构的制作方法
EP4231653A3 (en) * 2016-03-28 2024-03-06 Ningbo Sunny Opotech Co., Ltd. Camera module and molded photosensitive assembly and manufacturing method therefor, and electronic device

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10763286B2 (en) * 2015-07-23 2020-09-01 Sony Corporation Semiconductor device, manufacturing method thereof, and electronic apparatus
FR3061629A1 (fr) * 2017-01-03 2018-07-06 Stmicroelectronics (Grenoble 2) Sas Procede de fabrication d'un capot pour boitier electronique et boitier electronique comprenant un capot
FR3061630B1 (fr) 2017-01-03 2021-07-09 St Microelectronics Grenoble 2 Procede de fabrication d'un capot pour boitier electronique et boitier electronique comprenant un capot
FR3061628A1 (fr) 2017-01-03 2018-07-06 Stmicroelectronics (Grenoble 2) Sas Procede de fabrication d'un capot d'encapsulation pour boitier electronique et boitier electronique comprenant un capot
JP2018144325A (ja) * 2017-03-03 2018-09-20 キヤノン株式会社 樹脂層表面の押圧方法
CN108695165A (zh) * 2017-04-07 2018-10-23 宁波舜宇光电信息有限公司 基于模制工艺的半导体封装方法和半导体装置
WO2018184572A1 (zh) 2017-04-07 2018-10-11 宁波舜宇光电信息有限公司 基于模制工艺的半导体封装方法和半导体装置
WO2019022664A1 (en) * 2017-07-25 2019-01-31 Ams Sensors Singapore Pte. Ltd. WAFER-LEVEL PROCESSES FOR THE MANUFACTURE OF UNIFORM MATERIAL LAYERS ON OPTOELECTRONIC MODULES
FR3075466B1 (fr) * 2017-12-15 2020-05-29 Stmicroelectronics (Grenoble 2) Sas Couvercle de boitier de circuit electronique

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61222384A (ja) * 1985-03-27 1986-10-02 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6483030B1 (en) * 1999-12-08 2002-11-19 Amkor Technology, Inc. Snap lid image sensor package
TWI398949B (zh) * 2009-07-29 2013-06-11 Kingpak Tech Inc 模造成型之影像感測器封裝結構製造方法及封裝結構
TWI437700B (zh) * 2010-05-31 2014-05-11 Kingpak Tech Inc 晶圓級影像感測器構裝結構之製造方法
FR2977076A1 (fr) * 2011-06-21 2012-12-28 St Microelectronics Grenoble 2 Dispositif semi-conducteur a elements de connexion electrique encapsules et son procede de fabrication
TW201503334A (zh) * 2013-07-08 2015-01-16 Kingpaktechnology Inc 影像感測器二階段封裝方法
FR3029687A1 (fr) * 2014-12-09 2016-06-10 Stmicroelectronics (Grenoble 2) Sas Procede de fabrication de dispositifs electroniques et dispositif electronique a double anneau d'encapsulation

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105679717A (zh) * 2014-12-09 2016-06-15 意法半导体(格勒诺布尔2)公司 制造电子器件的方法以及具有双密封环的电子器件
CN105679717B (zh) * 2014-12-09 2019-05-07 意法半导体(格勒诺布尔2)公司 制造电子器件的方法以及具有双密封环的电子器件
EP4231653A3 (en) * 2016-03-28 2024-03-06 Ningbo Sunny Opotech Co., Ltd. Camera module and molded photosensitive assembly and manufacturing method therefor, and electronic device
CN107403862A (zh) * 2016-05-20 2017-11-28 厦门市三安光电科技有限公司 发光二极管封装结构的制作方法
CN107403862B (zh) * 2016-05-20 2020-02-11 厦门市三安光电科技有限公司 发光二极管封装结构的制作方法

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