CN204857714U - 一种新型引线框架 - Google Patents

一种新型引线框架 Download PDF

Info

Publication number
CN204857714U
CN204857714U CN201520639691.XU CN201520639691U CN204857714U CN 204857714 U CN204857714 U CN 204857714U CN 201520639691 U CN201520639691 U CN 201520639691U CN 204857714 U CN204857714 U CN 204857714U
Authority
CN
China
Prior art keywords
slide glass
lead frame
fin
hole
leg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201520639691.XU
Other languages
English (en)
Inventor
黄斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SICHUAN JINWAN ELECTRONIC CO Ltd
Original Assignee
SICHUAN JINWAN ELECTRONIC CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SICHUAN JINWAN ELECTRONIC CO Ltd filed Critical SICHUAN JINWAN ELECTRONIC CO Ltd
Priority to CN201520639691.XU priority Critical patent/CN204857714U/zh
Application granted granted Critical
Publication of CN204857714U publication Critical patent/CN204857714U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本实用新型公开了一种新型引线框架，包括铜基单元，所述铜基单元包括依次连接成一体的散热片、载片、内引线和外引线，所述散热片上设有定位孔，所述内引线上设有焊脚，所述散热片和载片连接处设有注塑孔，所述注塑孔的内壁沿圆周方向设有环状凸肋，其提供了可靠性更高的注塑引线框架，防止塑封体件与引线框架脱落，提高电子元器件的使用寿命。

Description

一种新型引线框架
技术领域
本实用新型涉及半导体电子元器件制造技术领域，尤其涉及一种新型引线框架。
背景技术
引线框架作为集成电路的芯片载体，是一种借助于键合材料（金丝、铝丝、铜丝）实现芯片内部电路引出端与外引线的电气连接，形成电气回路的关键结构件，它起到了和外部导线连接的桥梁作用，绝大部分的半导体集成块中都需要使用引线框架，是电子信息产业中重要的基础材料。目前，半导体电子元器件通常由芯片、塑封体件、金丝或者铝丝、引线框架组装而成，为了提高自动化生产效率，引线框架一般由多个相同的铜基单元排列而成，而每个铜基单元包括依次连接成一体的散热片、载片、内引线和外引线，载片用于承载电子元器件的芯片，芯片通过塑封体包封后封装在载片上。这类产品封装后塑封体与载片间结构不牢固，易于分离或脱落，尤其是发生振动或使用时间较长时，塑封体与载片更易发生脱落，降低了电子元器件的使用寿命。
另有中国专利号为201310435822.8，公布日为2013.12.25公开了公开了一种封装引线框架，由若干个铜基单元连续排列而成，每个铜基单元包括依次连接成一体的散热片、载片、内引线和外引线；其特征在于：散热片和载片连接处设置有一燕尾槽，燕尾槽设置在铜基单元的正面上；载片正面上设置有U形槽；内引线上设置有V型槽，V型槽设置在内引线的正面上；载片底面的四周边缘处设置有固胶凹槽。上述专利封装引线框架通过在散热片与载片间的燕尾槽和载片底面四周凹槽进行固胶，在一定程度上提高了电子元器件产品的塑封体与载片的结合强度，但产品的抗震性并不强，塑封体并不能与引线框架形成紧固连接。
实用新型内容
为了克服上述现有技术的缺陷，本实用新型提供了一种新型引线框架，其目的是进一步提供可靠性更高的注塑引线框架，防止塑封体件与引线框架脱落，提高电子元器件的使用寿命。
为了解决上述技术问题，本实用新型采用的技术方案是：
一种新型引线框架，包括铜基单元，所述铜基单元包括依次连接成一体的散热片、载片、内引线和外引线，所述散热片上设有定位孔，所述内引线上设有焊脚，其特征在于：所述散热片和载片连接处设有注塑孔，所述注塑孔的内壁沿圆周方向上设有环状凸肋。
所述散热片和载片连接处设有燕尾槽，所述注塑孔设置在燕尾槽上。
所述的注塑孔为长圆孔。
所述的焊脚上设有锁胶孔。
所述的焊脚为两个，其中一个焊脚的宽度大于另一个焊脚的宽度。
所述载片上设置有呈“田”字形的V型凹槽。
本实用新型具有以下优点：
1、本实用新型在散热片和载片连接处设有注塑孔，所述注塑孔的内壁沿圆周方向设有环状凸肋，结合正面设置的台阶结构，塑料注入注塑孔后，环状凸肋在塑封体件内形成倒钩，即设有环状凸肋的注塑孔为环倒钩的孔，塑封体件与引线框架结合牢固，即使电子元器件发生震动，塑封体件与引线框架也不会发生分离或脱落，提高了电子元器件可靠性和延长了使用寿命。
2、本实用新型的散热片和载片连接处设有燕尾槽，在燕尾槽上设置注塑孔，使塑封体与载片结合更稳定、牢固，从而进一步提高了电子元器件可靠性和延长了使用寿命。
3、本实用新型的焊脚上设有锁胶孔，载片设置有呈“田”字形的V型凹槽，锁胶孔内注入塑胶，焊脚被塑胶牢牢的拉住，防止焊脚受向外的力时，焊脚被拉出塑胶体或焊脚产生松动。
4、本实用新型的载片上设置有呈“田”字形的V型凹槽，加强焊料与框架的结合力，防止产品使用时间长后焊料与框架分离，导致芯片无法散热，提高产品可靠性与寿命。
附图说明
图1为本实用新型的结构示意图；
图2为图1的A-A向视图；
图3为本实用新型的实施例2的结构示意图；
图4为图3的B-B向视图。
图中标记：1、散热片，2、载片，3、定位孔，4、内引线，5、外引线，6、焊脚，7、注塑孔，8、锁胶孔，9、燕尾槽，10、“田”字形的V型凹槽，11、环状凸肋，12、塑封体，13、芯片。
具体实施方式
下面结合附图对本实用新型做进一步的说明：
实施例1
如图1、图2所示，一种新型引线框架，包括铜基单元，所述铜基单元包括依次连接成一体的散热片1、载片2、内引线4和外引线5，所述散热片1上设有定位孔3，所述载片2用于安装芯片13，所述内引线4上设有焊脚6，焊脚6通过焊线与芯片13连接，所述散热片1和载片2连接处设有注塑孔7，注塑孔7为一贯穿散热片1和载片2连接处的通孔，向注塑孔7内注入塑胶，将安装好的芯片13与载片2进行塑胶封住，为了防止注塑后的塑封体12脱落，所述注塑孔7的内壁沿圆周方向上设有环状凸肋11，环状凸肋11在注塑孔7对塑封体12起着倒钩的作用，防止震动时塑封体12分离或脱落，注塑孔7为长圆孔（其形状如图1所示），提高了电子元器件可靠性和延长了使用寿命。
进一步的，所述散热片1和载片2连接处设有燕尾槽9，所述注塑孔7设置在燕尾槽9上，就是先在散热片1和载片2连接处设置燕尾槽9，然后在燕尾槽9上设置注塑孔7，使塑封体件与载片结合更稳定、牢固。
实施例2
如图3、图所示，一种新型引线框架，包括铜基单元，所述铜基单元包括依次连接成一体的散热片1、载片2、内引线4和外引线5，所述散热片1上设有定位孔3，所述载片2用于承载电子元器件的芯片13，所述内引线4上设有焊脚6，焊脚6通过焊线与芯片13连接，所述散热片1和载片2连接处设有注塑孔7，注塑孔7为一贯穿散热片1和载片2连接处的通孔，向注塑孔7内注入塑胶，将安装好的芯片13与载片2进行塑胶封住，为了防止注塑后的塑封体12脱落，所述注塑孔7的内壁沿圆周方向设有环状凸肋11，环状凸肋11在注塑孔7对塑封体12起着倒钩的作用，防止震动时塑封体12分离或脱落。所述散热片1和载片2连接处设有燕尾槽9，所述注塑孔7设置在燕尾槽9上，就是先在散热片1和载片2连接处设置燕尾槽9，然后在燕尾槽9上设置注塑孔7。
进一步的，在所述的焊脚6上设有锁胶孔8，锁胶孔8为贯穿焊脚6的通孔，塑胶注入锁胶孔8内，焊脚被塑胶牢牢的拉住，防止焊脚受向外的力时，管焊脚被拉出塑胶体。
进一步的，所述载片2上设置有呈“田”字形的V型凹槽10，所述“田”字形的V型凹槽10是指该凹槽的形状为“田”字形，其笔画设置在载片2上为V型，加强焊料与框架的结合力，防止产品使用时间长后焊料与框架分离，导致芯片无法散热，提高产品可靠性与寿命。
更进一步的，所述的焊脚6为两个，其中一个焊脚的宽度大于另一个焊脚的宽度，如图3所示，右边的焊脚宽度大于左边的焊脚宽度，以满足越来越多的焊线要求，更适用不同的焊接方式及多种类型的芯片，适用于不同功率大小的电子元件，满足不同的功能需求。

Claims (6)

1.一种新型引线框架，包括铜基单元，所述铜基单元包括依次连接成一体的散热片(1)、载片(2)、内引线(4)和外引线(5)，所述散热片(1)上设有定位孔(3)，所述内引线(4)上设有焊脚(6)，其特征在于：所述散热片(1)和载片(2)连接处设有注塑孔(7)，所述注塑孔(7)的内壁沿圆周方向设有环状凸肋(11)。
2.根据权利要求1所述的一种新型引线框架，其特征在于：所述散热片(1)和载片(2)的连接处设有燕尾槽(9)，所述注塑孔(7)设置在燕尾槽(9)上。
3.根据权利要求1所述的一种新型引线框架，其特征在于：所述的注塑孔(7)为长圆孔。
4.根据权利要求1所述的一种新型引线框架，其特征在于：所述的焊脚(6)上设有锁胶孔。
5.根据权利要求1所述的一种新型引线框架，其特征在于：所述的焊脚(6)为两个，其中一个焊脚的宽度大于另一个焊脚的宽度。
6.根据权利要求1所述的一种新型引线框架，其特征在于：所述载片(2)上设置有呈“田”字形的V型凹槽(10)。
CN201520639691.XU 2015-08-24 2015-08-24 一种新型引线框架 Active CN204857714U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201520639691.XU CN204857714U (zh) 2015-08-24 2015-08-24 一种新型引线框架

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201520639691.XU CN204857714U (zh) 2015-08-24 2015-08-24 一种新型引线框架

Publications (1)

Publication Number Publication Date
CN204857714U true CN204857714U (zh) 2015-12-09

Family

ID=54748240

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201520639691.XU Active CN204857714U (zh) 2015-08-24 2015-08-24 一种新型引线框架

Country Status (1)

Country Link
CN (1) CN204857714U (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105895592A (zh) * 2016-06-24 2016-08-24 扬州扬杰电子科技股份有限公司 一种框架、包含该框架的二极管及二极管的加工工艺
CN105931972A (zh) * 2016-06-17 2016-09-07 泰兴市永志电子器件有限公司 半导体框架的内引线分层制作方法
CN107994003A (zh) * 2017-12-01 2018-05-04 泰州友润电子科技股份有限公司 一种改进的to-220ew引线框架
CN108807328A (zh) * 2018-05-02 2018-11-13 泰州友润电子科技股份有限公司 一种便于塑封脱模的多载型220d8引线框架
CN108807329A (zh) * 2018-05-02 2018-11-13 泰州友润电子科技股份有限公司 一种便于封装加工的多载型引线框架
CN110676236A (zh) * 2019-08-27 2020-01-10 华东光电集成器件研究所 一种厚膜功率混合集成电路
CN113394188A (zh) * 2021-05-14 2021-09-14 南通华达微电子集团股份有限公司 具有异形锁孔的引线框架

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105931972A (zh) * 2016-06-17 2016-09-07 泰兴市永志电子器件有限公司 半导体框架的内引线分层制作方法
CN105895592A (zh) * 2016-06-24 2016-08-24 扬州扬杰电子科技股份有限公司 一种框架、包含该框架的二极管及二极管的加工工艺
CN107994003A (zh) * 2017-12-01 2018-05-04 泰州友润电子科技股份有限公司 一种改进的to-220ew引线框架
CN108807328A (zh) * 2018-05-02 2018-11-13 泰州友润电子科技股份有限公司 一种便于塑封脱模的多载型220d8引线框架
CN108807329A (zh) * 2018-05-02 2018-11-13 泰州友润电子科技股份有限公司 一种便于封装加工的多载型引线框架
CN110676236A (zh) * 2019-08-27 2020-01-10 华东光电集成器件研究所 一种厚膜功率混合集成电路
CN113394188A (zh) * 2021-05-14 2021-09-14 南通华达微电子集团股份有限公司 具有异形锁孔的引线框架
CN113394188B (zh) * 2021-05-14 2022-04-22 南通华达微电子集团股份有限公司 具有异形锁孔的引线框架

Similar Documents

Publication Publication Date Title
CN204857714U (zh) 一种新型引线框架
CN106847800A (zh) Qfn表面贴装式rgb‑led封装模组及其制造方法
CN202308051U (zh) Led封装支架及led器件
CN103985692A (zh) Ac-dc电源电路的封装结构及其封装方法
CN104425426A (zh) 压力传感器装置及装配方法
US9817079B2 (en) Molded sensor package with an integrated magnet and method of manufacturing molded sensor packages with an integrated magnet
US20110199749A1 (en) Led lead frame structure
CN206340542U (zh) 一种qfn表面贴装式rgb‑led封装模组
CN103474411A (zh) 一种封装引线框架
US8334175B1 (en) Manufacturing method of LED package structure
CN201417768Y (zh) 一种半导体集成电路引线框架
CN201663159U (zh) 一种强力固胶型塑料封装引线框架
CN203910845U (zh) 一种朗伯型led大功率封装结构
CN203774298U (zh) 一种带电极压力装置的功率半导体模块
CN103985693A (zh) 无刷直流电机集成驱动电路的封装结构及其封装方法
CN203871321U (zh) 无刷直流电机集成驱动电路的封装结构
CN209515637U (zh) 一种功率模块结构
CN207651475U (zh) 一种芯片封装组件
CN103094450A (zh) Led封装支架、led器件及led器件的制造方法
CN203553212U (zh) 一种可组合的晶片直接封装cob支架
CN206849834U (zh) 一种抗冲击用的引线框架
CN103130173B (zh) 用于mems芯片封装的无小岛引线框、引线框阵列及封装结构
CN104465955A (zh) 一种led灯带及其制作方法
CN205319144U (zh) 一种封装芯片的结构
CN205081116U (zh) 一种新型半导体引线框架

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant