CN204204843U - 晶片封装结构 - Google Patents
晶片封装结构 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8434—Bonding interfaces of the connector
- H01L2224/84345—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
本实用新型提供一种晶片封装结构。所述晶片封装结构包括晶片座、设于所述晶片座的晶片、跳线和引脚,所述跳线一端抵接所述晶片,另一端与所述引脚相接,所述跳线包括跳线本体和多个跳线卡块,多个所述跳线卡块设于所述跳线本体并与所述引脚相接。本实用新型提供的晶片封装结构具有稳固性高及电流导通量大的优点。
Description
技术领域
本实用新型涉及电子封装工业领域,尤其涉及一种晶片封装结构。
背景技术
随着电子封装工业在我国的迅速发展,尤其是晶片封装的小型化和组装的高密度化,对晶片封装的质量要求也越来越高。晶片封装技术的发展对于晶片来说是必须的,也是至关重要的。
晶片封装是指安装半导体集成电路晶片用的外壳,它不仅起着保护晶片和增强导热性能的作用,而且还是沟通晶片内部世界与外部电路的桥梁。跳线是晶片封装结构的主要元件之一,其作用是连接引脚与晶片,进行同等电势电压传输,同时,也有利于保护电路的参考电压,此外,对于有精密电压要求的,金属跳线的些许变化所产生的压降也会对产品性能产生很大影响。
现有技术的晶片封装结构主要存在以下问题:
一、稳固性低:跳线与引脚仅仅存在搭接关系,二者容易晃动,会影响焊接效果,而影响晶片封装结构的信号传输质量;
二、电流导通量小:跳线与引脚的焊接桥面积小,导致电流导通量小。
实用新型内容
为了解决上述晶片封装结构稳固性低和电流导通量小的技术问题,本实用新型提供一种稳固性高和电流导通量大的晶片封装结构。
本实用新型提供的晶片封装结构,包括晶片座、设于所述晶片座的晶片、跳线和引脚,所述跳线一端抵接所述晶片,另一端与所述引脚相接,所述跳线包括跳线本体和多个跳线卡块,多个所述跳线卡块设于所述跳线本体并与所述引脚相接。
在本实用新型提供的晶片封装结构的一种较佳实施例中,多个所述跳线卡块与所述跳线本体为一体化连接。
在本实用新型提供的晶片封装结构的一种较佳实施例中,多个所述跳线卡块为楔形块或方形块。
在本实用新型提供的晶片封装结构的一种较佳实施例中,多个所述跳线卡块分别与所述跳线本体形成的夹角为钝角。
在本实用新型提供的晶片封装结构的一种较佳实施例中,多个所述跳线卡块间隔设置,并围成一个卡位区。
在本实用新型提供的晶片封装结构的一种较佳实施例中,所述引脚包括引脚本体和设于所述引脚本体一端的引块,所述引块与所述跳线相接。
相较于现有技术,本实用新型提供的晶片封装结构具有以下有益效果:
一、通过在跳线上增设多个跳线卡块,对跳线在与引脚连接时起到限位作用,增强跳线与引脚连接时的稳固性,利于晶片封装结构的信号传输质量提升;
二、通过采用多个跳线卡块与所述引脚相接的设计,增加跳线与引脚的接触面积,扩大了跳线和引脚的焊接桥面积,增大了跳线与引脚间的电流导通量;
三、通过将多个跳线卡块分别与跳线形成的夹角设计为钝角,便于引块嵌入多个跳线卡块围成的卡位区,利用多个跳线卡块固定引块,实现跳线与引脚的稳固相接,利于对二者进行焊接。
附图说明
为了更清楚地说明本实用新型实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本实用新型的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的附图,其中:
图1是本实用新型提供的晶片封装结构的一种实施例的结构示意图;
图2是图1所示的晶片封装结构的俯视图;
图3是图1所示的晶片封装结构的跳线的局部结构示意图;
图4是图1所示的晶片封装结构的引脚的结构示意图。
具体实施方式
下面将结合本实用新型实施例中的附图,对本实用新型实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本实用新型的一部分实施例,而不是全部的实施例。基于本实用新型中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本实用新型保护的范围。
请同时参阅图1和图2,其中,图1是本实用新型提供的晶片封装结构的一种实施例的结构示意图,图2是图1所示的晶片封装结构的俯视图。所述晶片封装结构1包括晶片座11、设于所述晶片座11的晶片13、跳线15和引脚17。所述跳线15一端抵接所述晶片13设置,另一端与所述引脚17相接。
所述晶片座11包括承载面,所述承载面用于支撑所述晶片13,所述晶片座11同时具有散热功能。
所述晶片13包括第一表面131和具感应区且与所述第一表面131相对设置的第二表面133。所述承载面与所述第一表面131相接设置,所述第二表面133与所述跳线15抵接。所述晶片13储存的信息和功能通过所述第二表面133实现传递和体现。
请结合参阅图3,图3是图1所示的晶片封装结构的跳线的局部结构示意图。所述跳线15包括跳线本体151和设于所述跳线本体151的三跳线卡块153、155、157,三所述跳线卡块153、155、157分别为跳线卡块一153、跳线卡块二155和跳线卡块三157,三所述跳线卡块153、155、157间隔设置,三者围成一卡位区,所述跳线卡块一153和所述跳线卡块二155分别设于所述跳线本体151一端的两个边角,所述跳线卡块157设于所述跳线本体151中部。在本实施例中,所述跳线卡块一153、所述跳线卡块二155和所述跳线卡块三157都为楔形块,所述跳线卡块一153、所述跳线卡块二155及所述跳线卡块三157分别与所述跳线15形成一定的夹角,且夹角为钝角。在其他情况下,所述跳线卡块一153、所述跳线卡块二155和所述跳线卡块三157还可以为方形块。所述跳线卡块一153、跳线卡块二155和跳线卡块三157与所述跳线本体151为一体化连接形成所述跳线15。
请再结合参阅图4,图4是图1所示的晶片封装结构的引脚的结构示意图。所述引脚17包括引脚本体171和设于所述引脚本体171一端的引块173。所述引块173与所述跳线15的三所述跳线卡块153、155、157相接,所述引块173嵌入三所述跳线卡块153、155、157围成的卡位区,利用三所述跳线卡块153、155、157对其固定,实现所述跳线15与所述引脚17的稳固相接,利于对二者进行焊接。
本实用新型具有以下有益效果:
一、通过采用三所述跳线卡块153、155、157的结合设计,对所述跳线15在与所述引脚17连接时起到限位作用,增强所述跳线15与所述引脚17连接时的稳固性,利于所述晶片封装结构1的信号传输质量提升;
二、通过采用三所述跳线卡块153、155、157与所述引脚17相接的设计,增加所述跳线15与所述引脚17的接触面积,扩大了所述跳线15和所述引脚17的焊接桥面积,增大了所述跳线15与所述引脚17间的电流导通量;
三、通过将三所述跳线卡块153、155、157分别与所述跳线本体151形成的夹角设计为钝角,便于所述引块173嵌入三所述跳线卡块153、155、157围成的卡位区,利用三所述跳线卡块153、155、157固定所述引块173,实现所述跳线15与所述引脚17的稳固相接,利于对二者进行焊接。
以上所述仅为本实用新型的实施例,并非因此限制本实用新型的专利范围,凡是利用本实用新型说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其它相关的技术领域,均同理包括在本实用新型的专利保护范围内。
Claims (6)
1.一种晶片封装结构,其特征在于:包括晶片座、设于所述晶片座的晶片、跳线和引脚,所述跳线一端抵接所述晶片,另一端与所述引脚相接,所述跳线包括跳线本体和多个跳线卡块,多个所述跳线卡块设于所述跳线本体并与所述引脚相接。
2.根据权利要求1所述的晶片封装结构,其特征在于:多个所述跳线卡块与所述跳线本体为一体化连接。
3.根据权利要求1所述的晶片封装结构,其特征在于:多个所述跳线卡块为楔形块或方形块。
4.根据权利要求1所述的晶片封装结构,其特征在于:多个所述跳线卡块分别与所述跳线本体形成的夹角为钝角。
5.根据权利要求1所述的晶片封装结构,其特征在于:多个所述跳线卡块间隔设置,并围成一个卡位区。
6.根据权利要求1所述的晶片封装结构,其特征在于:所述引脚包括引脚本体和设于所述引脚本体一端的引块,所述引块与所述跳线相接。
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CN109887896A (zh) * | 2019-03-12 | 2019-06-14 | 如皋市大昌电子有限公司 | 一种超薄型贴片式桥堆整流装置 |
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CN109887896A (zh) * | 2019-03-12 | 2019-06-14 | 如皋市大昌电子有限公司 | 一种超薄型贴片式桥堆整流装置 |
CN109887896B (zh) * | 2019-03-12 | 2021-08-24 | 如皋市大昌电子有限公司 | 一种超薄型贴片式桥堆整流装置 |
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