CN203733790U - Internal decoupling integrated circuit packaging - Google Patents

Internal decoupling integrated circuit packaging Download PDF

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Publication number
CN203733790U
CN203733790U CN201420050566.0U CN201420050566U CN203733790U CN 203733790 U CN203733790 U CN 203733790U CN 201420050566 U CN201420050566 U CN 201420050566U CN 203733790 U CN203733790 U CN 203733790U
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CN
China
Prior art keywords
chip
decoupling
decoupling capacitor
substrate
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN201420050566.0U
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Chinese (zh)
Inventor
潘计划
袁正红
毛忠宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Fastprint Circuit Tech Co Ltd
Yixing Silicon Valley Electronic Technology Co Ltd
Original Assignee
Shenzhen Fastprint Circuit Tech Co Ltd
Yixing Silicon Valley Electronic Technology Co Ltd
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Filing date
Publication date
Application filed by Shenzhen Fastprint Circuit Tech Co Ltd, Yixing Silicon Valley Electronic Technology Co Ltd filed Critical Shenzhen Fastprint Circuit Tech Co Ltd
Priority to CN201420050566.0U priority Critical patent/CN203733790U/en
Application granted granted Critical
Publication of CN203733790U publication Critical patent/CN203733790U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

The utility model discloses internal decoupling integrated circuit packaging. The integrated circuit packaging comprises a substrate, a chip and a decoupling capacitor. The chip is arranged on the substrate. The decoupling capacitor is arranged on the chip. The chip and the substrate are electrically connected. The decoupling capacitor is electrically connected with the chip. The decoupling capacitor is integrated in the integrated circuit packaging so that a decoupling circuit path of the chip is effectively shortened and a loop inductance is reduced; a power supply with low impedance can be provided for a high speed chip and an electromagnetic interference of the chip is reduced; requirements of a high density, high performance and low cost of the integrated circuit are satisfied; low technology difficulty is realized; and good economic and social benefits are possessed. The internal decoupling integrated circuit packaging can be widely used for various kinds of the integrated circuit packaging.

Description

A kind of integrated antenna package of inner decoupling
Technical field
The utility model relates to integrated antenna package field, relates in particular to a kind of integrated antenna package of inner decoupling.
Background technology
PCB: printed circuit board (PCB).
BGA:Ball Grid Array, soldered ball grid array, the encapsulation of general reference soldered ball grid array.
POP:Package On Package, laminate packaging, a kind of three-dimension packaging structure.
Integrated circuit is the core of electronic product, and the normal work of chip be unable to do without power source deoupling circuit, and the most frequently used decoupling circuit adds decoupling capacitor exactly on pcb board.But along with this decoupling circuit of raising of electronic product signal rate can not meet the demands, because the Path too long that this decoupling circuit electric current is flowed through from decoupling capacitor to chip internal, inductance on supply path presents high-impedance behavior in the time of high frequency, causes chip in the time of high speed operation, easily to produce the problem of electricity shortage.Can increase chip area and add decoupling capacitor at chip internal, cost is increased severely.
Utility model content
In order to solve the problems of the technologies described above, it can be chip decoupling and reduction chip electromagnetic interference better that the purpose of this utility model is to provide one, meets the integrated antenna package of integrated antenna package high density, high-performance, low cost requirement simultaneously.
The technical scheme that the utility model adopts is:
An integrated antenna package for inner decoupling, it comprises substrate, chip and decoupling capacitor, and described chip is arranged on substrate, and described decoupling capacitor is arranged on chip, and described chip is connected with electrical property of substrate, and described decoupling capacitor and chip are electrically connected.
As the first embodiment of the present utility model, described decoupling capacitor is directly mounted on chip surface.
As the second embodiment of the present utility model, it also comprises top substrate layer, and described decoupling capacitor is mounted in top substrate layer, and described top substrate layer is mounted on chip surface, and described decoupling capacitor is connected with described chip by gold thread.
As the third embodiment of the present utility model, described decoupling capacitor is directly mounted on chip surface, is provided with silicon through hole on described chip, and described decoupling capacitor is electrically connected by silicon through hole and chip.
Preferably, the lower surface of described substrate has multiple encapsulation solder joints.
Preferably, described chip is connected with electrical property of substrate by gold thread.
Preferably, described chip is connected with electrical property of substrate by multiple chip welding spots.
Preferably, whole encapsulation is sealed by capsulation material.
The beneficial effects of the utility model are:
The utility model passes through at the integrated decoupling capacitor of interior of IC package, effectively shorten the decoupling circuit path of chip, reduce loop inductance, can be the electromagnetic interference that high-speed chip provides low-impedance power supply and reduces chip, meet integrated circuit high density, high-performance, requirement cheaply, and it is low to realize technology difficulty, there is good economic and social benefit.The utility model can be widely used in various integrated antenna packages.
Brief description of the drawings
Below in conjunction with accompanying drawing, embodiment of the present utility model is described further:
Fig. 1 is the structural representation of the utility model the first embodiment;
Fig. 2 is the structural representation of the utility model the second embodiment;
Fig. 3 is the structural representation of the third embodiment of the utility model;
Fig. 4 is the frequency-impedance plot of the utility model and prior art contrast.
Embodiment
It should be noted that, in the situation that not conflicting, the feature in embodiment and embodiment in the application can combine mutually.
A kind of integrated antenna package of inner decoupling, it comprises substrate 1, chip 2 and decoupling capacitor 3, and described chip 2 is arranged on substrate 1, and described decoupling capacitor 3 is arranged on chip 2, described chip 2 is electrically connected with substrate 1, and described decoupling capacitor 3 is electrically connected with chip 2.Whole encapsulation can be BGA packing forms, POP packing forms or other encapsulated type.
As shown in Figure 1, as the first embodiment of the present utility model, described decoupling capacitor 3 is directly mounted on chip 2 surfaces.Described chip 2 is electrically connected by gold thread 5 and substrate 1.The lower surface of described substrate 1 has multiple encapsulation solder joints 4.Whole encapsulation is sealed by capsulation material 8.
As shown in Figure 2, as the second embodiment of the present utility model, it also comprises top substrate layer 7, and described decoupling capacitor 3 is mounted in top substrate layer 7, and described top substrate layer 7 is mounted on chip 2 surfaces, and described decoupling capacitor 3 is connected with described chip 2 by gold thread 5.Described chip 2 is electrically connected by gold thread 5 and substrate 1.The lower surface of described substrate 1 has multiple encapsulation solder joints 4.Whole encapsulation is sealed by capsulation material 8.
As shown in Figure 3, as the third embodiment of the present utility model, described decoupling capacitor 3 is directly mounted on chip 2 surfaces, on described chip 2, is provided with silicon through hole 9, and described decoupling capacitor 3 is electrically connected by silicon through hole 9 and chip 2.The positive pole of decoupling capacitor 3 is connected to the power end of chip 2 by silicon through hole 9, the negative pole of decoupling capacitor 3 is connected to the ground end of chip 2 by another silicon through hole 9.Described chip 2 is electrically connected with substrate 1 by multiple chip welding spots 6.The lower surface of described substrate 1 has multiple encapsulation solder joints 4.Whole encapsulation is sealed by capsulation material 8.
As shown in Figure 4, contrast is known without the frequency-impedance plot of inner decoupling encapsulation intrinsic impedance 10, electric capacity intrinsic impedance 12, the intrinsic impedance 11 of the second embodiment and the intrinsic impedance 13 of the first embodiment:
Decoupling capacitor 3 is mounted on base plate for packaging 1, can reduces the impedance of low-frequency range, but the decoupling effect of patch capacitor, and not performance completely, is mainly because the inductance being encapsulated on chip 2 paths shows due to high impedance in the time of high frequency; Decoupling capacitor 3 is mounted on to chip 2 surfaces, the impedance that can see chip 2 ends is the linear superposition of encapsulation intrinsic impedance and condensance substantially, the effect of decoupling capacitor 3 is greatly brought into play, and just a source impedance is all dragged down, and greatly improves the Power Integrity of whole encapsulation.
The utility model passes through at the integrated decoupling capacitor 3 of interior of IC package, effectively shorten the decoupling circuit path of chip 2, reduce loop inductance, can be the electromagnetic interference that high-speed chip 2 provides low-impedance power supply and reduces chip 2, meet integrated circuit high density, high-performance, requirement cheaply, and it is low to realize technology difficulty, there is good economic and social benefit.
More than that better enforcement of the present utility model is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to the utility model spirit, and the distortion that these are equal to or replacement are all included in the application's claim limited range.

Claims (8)

1. the integrated antenna package of an inner decoupling, it is characterized in that: it comprises substrate, chip and decoupling capacitor, described chip is arranged on substrate, and described decoupling capacitor is arranged on chip, described chip is connected with electrical property of substrate, and described decoupling capacitor and chip are electrically connected.
2. the integrated antenna package of a kind of inner decoupling according to claim 1, is characterized in that: described decoupling capacitor is directly mounted on chip surface.
3. the integrated antenna package of a kind of inner decoupling according to claim 1, it is characterized in that: it also comprises top substrate layer, described decoupling capacitor is mounted in top substrate layer, and described top substrate layer is mounted on chip surface, and described decoupling capacitor is connected with described chip by gold thread.
4. the integrated antenna package of a kind of inner decoupling according to claim 1, is characterized in that: described decoupling capacitor is directly mounted on chip surface, is provided with silicon through hole on described chip, and described decoupling capacitor is electrically connected by silicon through hole and chip.
5. according to the integrated antenna package of a kind of inner decoupling described in claim 1 to 4 any one, it is characterized in that: the lower surface of described substrate has multiple encapsulation solder joints.
6. according to the integrated antenna package of a kind of inner decoupling described in claim 5 any one, it is characterized in that: described chip is connected with electrical property of substrate by gold thread.
7. according to the integrated antenna package of a kind of inner decoupling described in claim 5 any one, it is characterized in that: described chip is connected with electrical property of substrate by multiple chip welding spots.
8. according to the integrated antenna package of a kind of inner decoupling described in claim 1,2,3,4,6 or 7, it is characterized in that: whole encapsulation is sealed by capsulation material.
CN201420050566.0U 2014-01-26 2014-01-26 Internal decoupling integrated circuit packaging Expired - Lifetime CN203733790U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420050566.0U CN203733790U (en) 2014-01-26 2014-01-26 Internal decoupling integrated circuit packaging

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Application Number Priority Date Filing Date Title
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105957841A (en) * 2015-03-09 2016-09-21 联发科技股份有限公司 Semiconductor package assembly
WO2018125256A1 (en) * 2016-12-31 2018-07-05 Intel Corporation Decoupling capacitor mounted on an integrated circuit die, and method of manufacturing the same
CN112447606A (en) * 2019-08-29 2021-03-05 天津大学青岛海洋技术研究院 Decoupling capacitor placement method applied to system-in-package

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105957841A (en) * 2015-03-09 2016-09-21 联发科技股份有限公司 Semiconductor package assembly
EP3067928A3 (en) * 2015-03-09 2016-11-30 MediaTek, Inc Semiconductor package assembly with passive device
US9818727B2 (en) 2015-03-09 2017-11-14 Mediatek Inc. Semiconductor package assembly with passive device
TWI642163B (en) * 2015-03-09 2018-11-21 聯發科技股份有限公司 Semiconductor package assembly
CN105957841B (en) * 2015-03-09 2019-02-01 联发科技股份有限公司 Semiconductor package
US10497678B2 (en) 2015-03-09 2019-12-03 Mediatek Inc. Semiconductor package assembly with passive device
WO2018125256A1 (en) * 2016-12-31 2018-07-05 Intel Corporation Decoupling capacitor mounted on an integrated circuit die, and method of manufacturing the same
US11562978B2 (en) 2016-12-31 2023-01-24 Intel Corporation Decoupling capacitor mounted on an integrated circuit die, and method of manufacturing the same
CN112447606A (en) * 2019-08-29 2021-03-05 天津大学青岛海洋技术研究院 Decoupling capacitor placement method applied to system-in-package

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Granted publication date: 20140723