CN210518987U

CN210518987U - PCB structure for optimizing nuclear power distribution network impedance of BGA packaged chip

Info

Publication number: CN210518987U
Application number: CN201920969581.8U
Authority: CN
Inventors: 姜杰; 肖勇超; 吴均
Original assignee: Edadoc Co ltd
Current assignee: Edadoc Co ltd
Priority date: 2019-06-26
Filing date: 2019-06-26
Publication date: 2020-05-12
Anticipated expiration: 2029-06-26

Abstract

The utility model discloses an optimize BGA encapsulation chip nuclear power distribution network impedance's PCB structure, including the PCB body, be provided with power via hole and ground via hole on the PCB body, its characterized in that, the power via hole with the diameter of ground via hole is 10-12.8mil, BGA encapsulation chip's on the PCB body pin with the power via hole with ground via hole connection's pin is connected and is walked the line width and be 16.5-21 mil. Compared with the prior art, the utility model discloses need not modify the configuration of electric capacity quantity, appearance value, only through the power via hole of adjustment BGA and the via hole aperture of ground via hole and the design links such as the line linewidth of walking of pin and via connection, can promote the power integrality of this power distribution network, when reducing design cost, greatly improved design efficiency, and BGA encapsulates the chip scale and is big more, and the pin quantity of nuclear power distribution network is more, and is more obvious to the optimization effect of PDN impedance.

Description

PCB structure for optimizing nuclear power distribution network impedance of BGA packaged chip

[ technical field ] A method for producing a semiconductor device

The utility model relates to an optimize PCB structure of BGA encapsulation chip nuclear power distribution network impedance.

[ background of the invention ]

A Printed Circuit Board (PCB), also called a PCB, is an important component of physical support and signal transmission of electronic products. With the increase of the integration level and clock frequency of a digital chip packaged by a BGA (Ball Grid Array), the influence of Power noise generated in a Power Distribution Network (PDN) on the circuit performance is increasingly manifested, and meanwhile, in order to meet the requirement of low Power consumption of a chip, a BGA chip core Power supply shows a trend of lower and higher voltage and higher current, and the challenge of Power Integrity (PI) design is further increased.

The typical design concept for Power Distribution Network (PDN) impedance is based on a target impedance method. The target impedance is defined as the ratio of the maximum noise voltage to the maximum transient current tolerated by the system, and is expressed by the following formula:

Z_target＝ΔV_max/ΔI_max；

wherein Z is_targetRepresenting target impedance, Δ V_maxDenotes the maximum noise requirement, Δ I_maxRepresenting the maximum transient current.

Controlling the PDN impedance to be smaller than the target impedance in the frequency band of interest_maxAnd the power supply noise requirement is met. At present, the common BGA chip core power PDN impedance optimization mode is to perform repeated simulation-adjustment iteration on the configuration (quantity and capacitance value) of decoupling capacitors, and has large workload and low efficiency.

[ Utility model ] content

In order to overcome the deficiencies of the prior art, the utility model provides an optimize PCB structure of BGA encapsulation chip nuclear power distribution network impedance.

The utility model discloses technical scheme as follows:

the utility model provides an optimize PCB structure of BGA encapsulation chip nuclear power distribution network impedance, includes the PCB body, be provided with power via hole and ground via hole on the PCB body, its characterized in that, the power via hole with the diameter of ground via hole is 10-12.8 mil.

Furthermore, the width of the connection and routing of the pins of the BGA package chip on the PCB body and the pins connected with the power supply via holes and the ground via holes is 16.5-21 mil.

Further, the pins, the power vias and the ground vias of the same network on the surface layer of the PCB body are connected to each other.

Further, the adjacent PIN centre spacing of the BGA package chip of PCB body is 1.0 mm.

Further, the diameters of the power supply through hole and the ground through hole are both 12 mil.

Furthermore, the widths of the pin connecting wires are all 20 mil.

According to above-mentioned structure the utility model discloses, its beneficial effect lies in, compares with traditional way, the utility model discloses need not modify the configuration of electric capacity quantity, appearance value, only through the power via hole of adjustment BGA and the via hole aperture of ground via hole and design links such as line width are walked to pin and via hole connection, can promote the power integrality of this power distribution network, when reducing design cost, greatly improved design efficiency. And the larger the BGA packaging chip scale is, the more the number of pins of the nuclear power distribution network is, and the more obvious the optimization effect on the PDN impedance is.

[ description of the drawings ]

Fig. 1 is a schematic top view of the surface layer of the PCB body according to the present invention.

Fig. 2 is a graph comparing the PDN impedance curve simulation of the present invention and the conventional design.

In the figure, 1, a PCB body; 2. a power supply via hole; 3. a ground via; 4. a pin; 5. the pin is connected with the wiring.

[ detailed description ] embodiments

In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positions based on the orientations or positions shown in the drawings, and are for convenience of description only and not to be construed as limiting the technical solution. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.

As shown in figure 1, a PCB structure for optimizing the nuclear power distribution network impedance of a BGA package chip comprises a PCB body 1, wherein a power supply via hole 2 and a ground via hole 3 are arranged on the PCB body 1, the diameters of the power supply via hole 2 and the ground via hole 3 are both 12 mils, the width of a pin 4 of the BGA package chip on the PCB body 1 and the width of a pin connecting line 5 connected with the power supply via hole 2 and the ground via hole 3 are both 20 mils, and the pin 4, the power supply via hole 2 and the ground via hole 3 on the surface layer of the PCB body 1 are connected with each other as much as possible.

In this embodiment, the distance between the centers of the adjacent PINs of the BGA package chips of the PCB body is 1.0 mm. Under traditional design, the diameter of power via hole and ground via hole is 8 mils, and the pin of BGA package chip on the PCB body is connected with the pin of power via hole and ground via hole and is walked the line width and be 15 mils. In the embodiment, the diameters of the power supply via hole and the ground via hole can be increased to 10-12.8mil, the diameters are increased by 25-60% compared with the traditional design, the loop inductance of the power supply via hole and the ground via hole can be reduced by increasing the aperture, and the PDN impedance is further reduced by reducing the inductive reactance; the width of the connection wire of the pins of the BGA package chips on the PCB body and the pins connected with the power supply through holes and the ground through holes can be increased to 16.5-21mil, the wire width is increased by 25-60% compared with the traditional design, the parasitic inductance of the wire can be reduced by increasing the line width, and the PDN impedance is further reduced by reducing the inductive reactance.

BGA packages with 1.0mm spacing between adjacent PINs are most common, but the present invention is equally applicable to other formats of BGA, such as 0.8BGA, 1.25BGA, etc. Compared with a BGA (ball grid array) with the thickness of 1.0mm, in the traditional design, the aperture and the line width of the via hole of the BGA package with the relatively small PIN center spacing can be correspondingly reduced, and the aperture and the line width of the via hole of the BGA package with the relatively large PIN spacing can be correspondingly increased. For BGA package with PIN center spacing not less than 1.0mm, the diameters of the power supply via hole and the ground via hole are increased by 25-60% compared with the traditional design, and the width of the PINs of the BGA package chip on the PCB body and the PIN connecting and routing width connected with the power supply via hole and the ground via hole are increased by 25-60% compared with the traditional design; and for BGA package with PIN center spacing smaller than 1.0mm, due to space limitation, the width of the PINs of the BGA package chip on the PCB body and the width of the PINs connected with the power supply via holes and the ground via holes are increased by 25-60% compared with the traditional design.

Referring to fig. 2, according to the design requirement of the core power supply of a BGA packaged chip, the concerned frequency band of the PCB board level PDN impedance is 100KHz to 10MHz (for the power supply of the BGA packaged chip, there is VRM filtering in the low frequency band, and there are decoupling capacitors in the package and on-chip capacitors in the chip for high frequency decoupling). Contrast traditional design with the utility model discloses a PDN impedance simulation curve can know, the utility model discloses a PDN impedance satisfies the frequency channel of target impedance wideer, has increased the frequency channel width about 2.5MHz than traditional design, has promoted 25% system allowance in other words.

It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are considered to be within the scope of the invention as defined by the following claims. The above exemplary description of the present invention is made in conjunction with the accompanying drawings, and it is obvious that the present invention is not limited by the above manner, and various improvements made by the method concept and technical solution of the present invention or by directly applying the concept and technical solution of the present invention to other occasions without improvement are all within the protection scope of the present invention.

Claims

1. The utility model provides an optimize PCB structure of BGA encapsulation chip nuclear power distribution network impedance, includes the PCB body, be provided with power via hole and ground via hole on the PCB body, its characterized in that, the power via hole with the diameter of ground via hole is 10-12.8 mil.

2. The PCB structure for optimizing the impedance of the nuclear power distribution network of the BGA package chip as claimed in claim 1, wherein the widths of the pin connection traces connecting the pins of the BGA package chip on the PCB body with the power vias and the ground vias are 16.5-21 mil.

3. The PCB structure for optimizing impedance of a BGA packaged chip core power distribution network of claim 2, wherein said pins, said power vias and said ground vias of the same network on a surface layer of said PCB body are interconnected.

4. The PCB structure for optimizing the impedance of the nuclear power distribution network of the BGA packaged chip as claimed in any one of claims 1 to 3, wherein the pitch between adjacent PIN centers of the BGA packaged chips of the PCB body is 1.0 mm.

5. The PCB structure for optimizing the impedance of a BGA packaged chip core power distribution network of claim 1, wherein said power vias and said ground vias are each 12mil in diameter.

6. The PCB structure for optimizing the impedance of a BGA packaged chip core power distribution network of claim 2, wherein said pin connection traces are all 20 mils wide.