CN217821607U

CN217821607U - PCB structure based on stack design optimization power distribution network impedance

Info

Publication number: CN217821607U
Application number: CN202221984138.6U
Authority: CN
Inventors: 姜杰; 吴均
Original assignee: Edadoc Co ltd
Current assignee: Edadoc Co ltd
Priority date: 2022-07-29
Filing date: 2022-07-29
Publication date: 2022-11-15
Anticipated expiration: 2032-07-29

Abstract

The utility model relates to a PCB structure based on range upon range of design optimization power distribution network impedance, including multilayer circuit board, multilayer circuit board's top layer is equipped with the BGA chip, multilayer circuit board's bottom is equipped with decoupling capacitance, the top layer with be equipped with first power-ground between multilayer circuit board's the intermediate position and face, first power-ground with interval between the top layer is less than first power-ground with interval between the intermediate position. The utility model discloses the first power-the horizontal plane that will be located the intermediate position is to distributing to being close to the top layer, can shorten the backward flow route of power to reduce power distribution network impedance, made it satisfy the requirement that is less than target impedance.

Description

PCB structure based on stack design optimization power distribution network impedance

Technical Field

The utility model relates to a circuit board design field, specific theory relates to a PCB structure based on range upon range of design optimization power distribution network impedance.

Background

With the increase of the integration level and clock frequency of the digital chip packaged by the BGA, the influence of Power supply noise generated in a Power Delivery Network (PDN) on the circuit performance is increasingly appearing; the power distribution network is composed of a power supply, a ground wire, a plane, decoupling capacitors and the like, so that the existing method for optimizing the impedance of the power distribution network is to repeatedly simulate and adjust and iterate the quantity and capacitance values of the decoupling capacitors to finally obtain a configuration scheme that the impedance of the power distribution network is smaller than the target impedance.

The principle of the above method is based on a target impedance method, the target impedance is defined as the ratio of the maximum noise voltage (Δ Vmax) to the maximum transient current (Δ Imax) tolerated by the system, and the target impedance is expressed by the following formula: ztarget = Δ Vmax/. Δ Imax. And controlling the impedance of the power supply distribution network to be smaller than the target impedance in the concerned frequency band, so that the delta Vmax can meet the requirement of power supply noise.

However, in order to meet the requirement of low power consumption of the chip, the BGA chip power supply tends to have a lower voltage and a higher current, which inevitably reduces the target impedance, which brings difficulty to the optimization of controlling the impedance of the power distribution network to be lower than the target impedance.

On the other hand, in actual work it was found that: at present, a power plane is generally distributed to a middle layer by a conventional stacking design, and no matter a BGA chip or a decoupling capacitor is used, a backflow path of a power supply is large, so that loop inductance is large, and PDN impedance is large, so that the impedance of a power distribution network is reduced by a reasonable stacking design, the requirement of being smaller than target impedance is met, and the power distribution network becomes a feasible breakthrough.

SUMMERY OF THE UTILITY MODEL

In order to solve under the current BGA chip development trend, the circuit board is in BGA chip one side, and the unsatisfied problem that is less than the target impedance of power distribution network impedance, the utility model provides a PCB structure based on range upon range of design optimization power distribution network impedance.

The utility model discloses technical scheme as follows:

the utility model provides a PCB structure based on range upon range of design optimization power distribution network impedance, includes multilayer circuit board, the top layer of multilayer circuit board is equipped with the BGA chip, the bottom of multilayer circuit board is equipped with decoupling capacitance, the top layer with be equipped with first power-ground between the intermediate position of multilayer circuit board and face, first power-ground with the interval between the top layer is less than first power-ground with the interval between the intermediate position.

According to above scheme the utility model discloses, its characterized in that, first power-ground plane is to including first power plane and first ground plane, first power plane with first ground plane all with the BGA chip is connected.

Further, the first power plane and the first ground plane are adjacent.

Preferably, the distance between the first power plane and the first ground plane is 4 mils.

Further, the first ground plane is adjacent to the top layer.

According to above-mentioned scheme the utility model discloses, its characterized in that, the bottom with be equipped with second power-ground plane pair between the intermediate position of multilayer circuit board, second power-ground plane pair with interval between the bottom is less than second power-ground plane pair with interval between the intermediate position.

Further, the second power-ground plane pair includes a second power plane and a second ground plane, both of which are connected to the decoupling capacitor.

Further, the second power plane is adjacent to the second ground plane.

Further, the second ground plane is adjacent to the bottom layer.

According to the above scheme the utility model discloses, its beneficial effect lies in:

the utility model discloses distribute "first power-ground plane pair" that will be located the intermediate position to being close to the top layer, can shorten the power backward flow route of BGA chip to reduce the return circuit inductance of BGA chip, and then reduced power distribution network impedance, make it satisfy the requirement that is less than the target impedance;

in the same way, the utility model discloses to be located "second power-ground of intermediate position is to" distribute to being close to the bottom, shorten decoupling capacitor's power return path, further reduced power distribution network impedance, the PDN impedance after the optimization satisfies the frequency channel of condition wideer, has increased 2 MHz's frequency channel than traditional design method, has promoted 20% system allowance.

Drawings

FIG. 1 is a schematic structural diagram of a preferred embodiment of the present invention;

fig. 2 is a signal simulation diagram of a preferred embodiment of the present invention;

fig. 3 is a signal simulation diagram of the prior art.

In the figure, 1, the top layer; 10. a BGA chip; 2. a bottom layer; 20. a decoupling capacitor; 3. a first power plane; 4. a first ground plane; 5. a second power plane; 6. a second ground plane.

Detailed Description

For better understanding of the objects, technical solutions and technical effects of the present invention, the present invention will be further explained with reference to the accompanying drawings and embodiments. It is to be noted that the following examples are only for explaining the present invention and are not intended to limit the present invention.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present, and when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or to implicitly indicate a number of technical features.

Example one

As shown in fig. 1, a PCB structure for optimizing power distribution network impedance based on a stacked design includes a multilayer circuit board, a top layer 1 of the multilayer circuit board is provided with a BGA chip 10, a bottom layer 2 of the multilayer circuit board is provided with a decoupling capacitor 20, a first power-ground plane pair is provided between the top layer 1 and an intermediate position of the multilayer circuit board, and a distance between the first power-ground plane pair and the top layer 1 is smaller than a distance between the first power-ground plane pair and the intermediate position. It can be seen that the scheme is different from the existing structure that the power plane is arranged on the middle layer, the scheme distributes the first power-plane pair to the position close to the top layer 1, and can shorten the power supply backflow path of the BGA chip 10, so that the loop inductance of the BGA chip 10 is reduced, the power distribution network impedance is further reduced, and the power distribution network impedance is smaller than the target impedance.

In this embodiment, the "first power-ground plane pair" includes a first power plane 3 and a first ground plane 4, both the first power plane 3 and the first ground plane 4 are connected to the BGA chip 10, and as a result, the first power plane 3, the first ground plane 4 and the BGA chip 10 form a loop, and in this scheme, the distance between the first power plane 3 and the corresponding first ground plane 4 is not changed, and the first power plane 3 and the corresponding first ground plane 4 are matched as a set of "power-ground plane pair" and are distributed to the top layer 1 near the circuit board.

In an alternative embodiment, the first power plane 3 and the first ground plane 4 are adjacent, which has a smaller return path and a smaller PDN impedance than the structure with other signal layers between the first power plane 3 and the first ground plane 4. In a specific embodiment the first power supply plane 3 and the first ground plane 4 are spaced apart by 4mil, i.e. the thickness of the insulating layer between the first power supply plane 3 and the first ground plane 4 is 4mil.

In an optional embodiment, the first ground plane 4 is adjacent to the top layer 1, and compared with a circuit board structure in which a signal layer is arranged between the first ground plane 4 and the top layer 1, the embodiment has a smaller loop inductance and a smaller PDN impedance; meanwhile, the present embodiment can also isolate interference signals between the top layer 1 and the first power plane 3 through the first ground plane 4.

Example two

The utility model provides a PCB structure based on range upon range of design optimization power distribution network impedance, includes multilayer circuit board, and multilayer circuit board's top layer 1 is equipped with BGA chip 10, and multilayer circuit board's bottom 2 is equipped with decoupling capacitor 20, and on the structural basis of embodiment one, further optimize PCB structure in decoupling capacitor 20 one side to solve the problem that decoupling capacitor 20's power return current route is bigger than normal, it is specific: a second power supply-ground plane pair is arranged between the bottom layer 2 and the middle position of the multilayer circuit board, and the distance between the second power supply-ground plane pair and the bottom layer 2 is smaller than the distance between the second power supply-ground plane pair and the middle position. Along with the embodiment, the embodiment distributes the power-ground plane corresponding to the decoupling capacitor 20 to the position close to the bottom layer 2, so that the power return path of the decoupling capacitor 20 can be shortened, the loop inductance of the decoupling capacitor 20 is reduced, and the power distribution network impedance is further reduced to be smaller than the target impedance.

In the present embodiment, the "second power-ground plane pair" includes the second power plane 5 and the second ground plane 6, and both the second power plane 5 and the second ground plane 6 are connected to the decoupling capacitor 20. The second power plane 5, the second ground plane 6 and the decoupling capacitor 20 form a loop together, the distance between the second power plane 5 and the corresponding second ground plane 6 is not changed in the scheme, and the second power plane 5 and the corresponding second ground plane 6 are matched to form a group of power-ground plane pairs and are distributed to the position close to the bottom layer 2 of the circuit board.

In a preferred embodiment, the second power plane 5 is adjacent to the second ground plane 6, and this structure enables a smaller loop path and a smaller loop inductance on the side of the decoupling capacitor 20, further reducing the PDN impedance; in addition, the second ground plane 6 is adjacent to the bottom layer 2, so that the second ground plane 6 substantially reduces the return path and the smaller loop inductance corresponding to the decoupling capacitor 20 while isolating the interference signal between the second power plane 5 and the bottom layer 2.

As shown in fig. 2 and 3, through adopting above-mentioned structure, the utility model discloses carry out simulation, concern the frequency channel and be 100KHz to 10MHz to compare simulation result with the simulation result that adopts traditional method, follow two simulation result contrastive analysis and know: the utility model discloses it is wideer to satisfy the frequency channel that the PDN impedance is less than the target impedance, has increased 2 MHz's frequency channel than traditional approach, has promoted 20% system allowance in other words.

All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above examples only represent some embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims

1. A PCB structure for optimizing power distribution network impedance based on a stacked design comprises a multilayer circuit board, wherein a BGA chip is arranged on the top layer of the multilayer circuit board, a decoupling capacitor is arranged on the bottom layer of the multilayer circuit board, and a first power-ground plane pair is arranged between the top layer and the middle position of the multilayer circuit board.

2. The PCB structure for optimizing power distribution network impedance based on a stacked design of claim 1, wherein the first power-ground plane pair comprises a first power plane and a first ground plane, both the first power plane and the first ground plane being connected to the BGA chip.

3. The PCB structure for optimizing power distribution network impedance based on stacked design of claim 2, wherein the first power plane and the first ground plane are adjacent.

4. The PCB structure for optimizing power distribution network impedance based on stacked design as claimed in claim 3, wherein the first power plane and the first ground plane are spaced apart by 4mil.

5. The PCB structure for optimizing power distribution network impedance based on a stacked design of claim 2, wherein the first ground plane is adjacent to the top layer.

6. The PCB structure for optimizing power distribution network impedance based on a stacked design as recited in claim 1, wherein a second power-ground plane pair is disposed between the bottom layer and an intermediate position of the multi-layered circuit board, and a distance between the second power-ground plane pair and the bottom layer is smaller than a distance between the second power-ground plane pair and the intermediate position.

7. The PCB structure for optimizing power distribution network impedance based on a stacked design of claim 6, wherein the second power-ground plane pair comprises a second power plane and a second ground plane, both of which are connected to the decoupling capacitor.

8. The PCB structure for optimizing power distribution network impedance based on a stacked design of claim 7, wherein the second power plane and the second ground plane are adjacent.

9. The PCB structure for optimizing power distribution network impedance based on a stacked design of claim 7, wherein the second ground plane is adjacent to the bottom layer.