CN102956622A - Inductor structure - Google Patents
Inductor structure Download PDFInfo
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- CN102956622A CN102956622A CN2012104968385A CN201210496838A CN102956622A CN 102956622 A CN102956622 A CN 102956622A CN 2012104968385 A CN2012104968385 A CN 2012104968385A CN 201210496838 A CN201210496838 A CN 201210496838A CN 102956622 A CN102956622 A CN 102956622A
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- bonding jumper
- chip inductor
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Abstract
The invention discloses an inductor structure, which comprises an on-chip inductor and a shielding layer located under the on-chip inductor, the shielding layer comprises at least one shielding unit, the shielding unit is orthogonal to the direction of eddy current generated by the on-chip inductor, and is composed of an MOM (Metal-Oxide-Metal) capacitor structure, the MOM capacitor structure comprises a group of right-angled first metal strips and a group of right-angled second metal strips, the group of first metal strips are parallel to one another and are spaced from one another to a certain degree, the group of second metal strips are parallel to one another and are spaced from one another to a certain degree, the group of first metal strips and the group of second metal strips are located on the same metal layer and formed into an inserting finger structure, the first metal strips are connected with a power supply, and the second metal strips are earthed. The inductor structure sufficiently utilizes the area of the bottom of the on-chip inductor to achieve the function of a voltage-regulating MOS (Metal Oxide Semiconductor) capacitor.
Description
Technical field
The present invention relates to integrated circuit fields, particularly a kind of inductance for circuit chip structure.
Background technology
Inductance is the important passive device in the radio frequency transceiver front end, and the radio-frequency front-end transceiver module need to be used mainly containing of integrated inductor: low noise amplifier, power amplifier, oscillator, up-conversion mixer etc.Inductance has all been played the part of important effect in these modules.
Take low noise amplifier as example, low noise amplifier is one of important module in the radio frequency transceiver, is mainly used in will being received from the communication system signal amplification of antenna, and the receiver circuit of being convenient to rear class is processed.Be positioned at the at first one-level that whole receiver is close to antenna just because of noise amplifier, its characteristic directly affects the quality that whole receiver receives signal.For low noise amplifier, the performance of inductance has directly determined gain, noise, impedance matching of low noise amplifier etc.
As a rule, the Q value is one of important indicator of an inductance performance, and the energy storage loss that higher Q value means inductance still less that is to say that the isolation between inductance and the substrate is better.In addition, to the assessment of an inductance except the traditional performance indexs such as inductance value, Q value, in radio system, also comprise inductance to the impact of other circuit, if inductance itself is better with the isolation of peripheral circuits, in inductance work, will not affect so the work of other circuit.
Because the area of integrated silicon inductor is usually larger, how when guaranteeing inductance performance, strengthen the isolation of inductance and substrate, inductance and other circuit, for the module that is applied to radio-frequency front-end, have great significance.
Figure 1 shows that the schematic diagram of induction structure in the prior art, its structure by the passive masking layer of substrate realizes the isolation of inductance and substrate.As a rule, for the integrated circuit (IC) chip of 8 layers of metal level, top-level metallic and time top-level metallic are commonly used to make integrated inductor 1, first layer metal then is used for making the passive separator 2 of sheltering that is positioned at inductance 1 below as shown in Figure 1, passive shelter separator 2 by many independences and itself be 90 the degree rectangular shaped the first layer metal lines consist of.The vortex flow perpendicular direction that these first layer metal lines and integrated inductor 1 produce cuts off the inductance galvanomagnetic effect to the impact of substrate thereby reach the passive separator 2 of sheltering.It should be noted that because the area of inductance usually large (such as 300 microns * 300 microns) is thereunder made the effect that passive masking layer no doubt can play electromagnetic isolation, but but effectively do not utilized the area of inductance below.
Summary of the invention
Main purpose of the present invention is to overcome the defective of prior art, takes full advantage of the area of induction areas below, makes screen have the effect of isolation and electric capacity of voltage regulation concurrently.
For reaching above-mentioned purpose, the invention provides a kind of induction structure, the screen that comprises on-chip inductor and be positioned at described on-chip inductor below, described screen comprises at least one screen unit, the vortex flow direction quadrature that described screen unit and described on-chip inductor produce, described screen unit is comprised of the MOM capacitance structure, and described MOM capacitance structure comprises square first bonding jumper of one group of certain intervals that is parallel to each other and has, and this end sealing of organizing the first bonding jumper links to each other; Square second bonding jumper of one group of certain intervals that is parallel to each other and has, this end sealing of organizing the second bonding jumper links to each other, this is organized the first bonding jumper and this and organizes the second bonding jumper and be positioned at layer metal level and form to insert and refer to structure, described the first bonding jumper connects power supply, described the second metal strips for grounding has dielectric medium between described the first bonding jumper and described the second bonding jumper.
Preferably, described MOM capacitance structure comprises that many groups are positioned at the first bonding jumper of different metal layer and the second bonding jumper that many groups are positioned at the different metal layer.
Preferably, between described first bonding jumper of different metal layer, by through-hole interconnection, between described second bonding jumper of different metal layer, pass through through-hole interconnection.
Preferably, described MOM capacitance structure comprises 4 group of first bonding jumper that lays respectively at 4 layers of metal level and 4 group of second bonding jumper that lays respectively at 4 layers of metal level, and described the first bonding jumper and described the second bonding jumper that are positioned at layer metal level form the slotting structure that refers to.
Preferably, the material of described dielectric medium is silicon dioxide.
Preferably, described on-chip inductor is the square spiral circle, and the number of described screen unit is 4, and described 4 screen units are with the Central Symmetry distribution of described on-chip inductor.
Preferably, has the interval between the described screen unit.
The invention has the advantages that, screen not only can play on-chip inductor and substrate in the induction structure, buffer action between on-chip inductor and other circuit, further the screen unit of screen is based on MOM capacitance structure composition, can also be connected between the supply voltage and ground of chip as large voltage stabilizing mos capacitance, play the pressure stabilization function of supply voltage, thereby taken full advantage of the larger area of on-chip inductor below.
Description of drawings
Fig. 1 is the schematic diagram of induction structure in the prior art.
Fig. 2 is the schematic diagram of MOM capacitance structure in the prior art.
Fig. 3 is the schematic diagram of embodiment of the invention induction structure.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Induction structure of the present invention comprises on-chip inductor and is positioned at the screen of on-chip inductor below.Wherein, on-chip inductor is made by top-level metallic and time top-level metallic, and screen comprises at least one screen unit.The passive arrangement mode of first layer metal of sheltering in the separator is similar in the arrangement mode of screen unit and the prior art, that is to say the vortex flow direction quadrature that produces with on-chip inductor, thereby can cut off the inductance galvanomagnetic effect to the impact of substrate.
Wherein, screen unit is comprised of the MOM capacitance structure.In modern integrated circuits technique, especially in 90nm and following technology node, MIM electric capacity commonly used is replaced by MOM electric capacity usually in original technique.For MOM electric capacity, as shown in Figure 2, (the electric capacity top crown is MOM Cap MetalA as two-layer pole plate about the electric capacity with layer metal in employing, the electric capacity bottom crown is MOM Cap Metal B), electric capacity adopts up and down silicon dioxide as dielectric material between the two-layer pole plate, solved the integration problem of high density capacitor and standard technology.Among the present invention, the MOM capacitance structure of screen unit also is to be formed by the manufacturing of standard integrated circuit technology, MOM capacitance structure that it should be noted that present embodiment comprises square first bonding jumper of one group of certain intervals that is parallel to each other and has, and this end sealing of organizing the first bonding jumper links to each other; Square second bonding jumper of one group of certain intervals that is parallel to each other and has, this end sealing of organizing the second bonding jumper links to each other, this is organized the first bonding jumper and this and organizes the second bonding jumper and be positioned at layer metal level and form to insert and refer to structure, the first bonding jumper connects power supply, the second metal strips for grounding, have dielectric medium between the first bonding jumper and the second bonding jumper, dielectric medium can be silicon dioxide.
Because the second metal strips for grounding, therefore many grounded metal lines with vortex flow direction quadrature have been equivalent to below on-chip inductor, form, thereby can be well at on-chip inductor magnetic field and substrate, and realize between on-chip inductor magnetic field and other circuit cutting off, so that substrate loss reduces, also reduced the signal cross-talk to other circuit devcies simultaneously.In addition, the first bonding jumper that is connected to whole chip power voltage is the upper strata pole plate of MOM electric capacity, the second bonding jumper that is connected to the ground of whole chip is lower floor's pole plate of MOM electric capacity, and the dielectric medium between the first bonding jumper and the second bonding jumper is the up and down intermetallic dielectric material of same layer between the two-layer pole plate of MOM electric capacity.Thereby this MOM electric capacity is connected between supply voltage and the ground, is equivalent to connect a large electric capacity between the supply voltage of chip and ground, has played the pressure stabilization function of supply voltage.It is worthy of note; traditional supply voltage voltage regulation way is generally and connects a large-scale mos capacitance between supply voltage and ground; in order to guarantee the enough large of mos capacitance value; usually need very large transistor area; and usually can independently occupy quite a few area of chip, cause the area cost of chip to increase.And induction structure of the present invention is to utilize the MOM capacitance structure to form the screen of on-chip inductor below, so takes full advantage of the larger area of below, on-chip inductor zone, need not additionally to increase chip area again large-scale mos capacitance is set, the cost of effectively saving.
Better, the MOM capacitance structure comprises that many groups are positioned at the first bonding jumper of different metal layer and the second bonding jumper that many groups are positioned at the different metal layer, can pass through through-hole interconnection between the first bonding jumper of different metal layer and between the second bonding jumper of different metal layer, thereby realize that the multiple layer metal parallel connection increases the up and down area of two-layer pole plate of MOM electric capacity.In one embodiment of this invention, the first bonding jumper of MOM capacitance structure and the second bonding jumper are arranged in 4 layers of metal level respectively, that is to say that the up and down two-layer pole plate of MOM electric capacity is made of the sidewall that four layers of metal are built up respectively.
Figure 3 shows that the schematic diagram of the induction structure of first embodiment of the invention.Please refer to Fig. 3, on-chip inductor 10 is the square spiral circle, is made by top-level metallic and time top-level metallic.Screen has 4 screen units, and the Central Symmetry distribution at on-chip inductor 10 forms " ten " font interval between 4 screen units.Each screen unit forms by MOM capacitance structure 20, therefore below on-chip inductor, have the MOM capacitance structure that the integrated circuit technology of 4 standards is made, be respectively upper left corner MOM capacitance structure, upper right corner MOM capacitance structure, lower left corner MOM capacitance structure and lower right corner MOM capacitance structure.Each MOM capacitance structure comprises square second bonding jumper 22 of 21, one groups of certain intervals that are parallel to each other and have of square the first bonding jumper of one group of certain intervals that is parallel to each other and has, and the dielectric medium between the first bonding jumper 21 and the second bonding jumper 22.Wherein the first bonding jumper 21 of each MOM capacitance structure 20 and the second bonding jumper 22 are all outwards dispersed arrangement with equidirectional, and the end sealing of a plurality of the first bonding jumpers 21 links to each other, and the end sealing of a plurality of the second bonding jumpers 22 links to each other; The first bonding jumper 21 and the second bonding jumper 22 are positioned at layer metal level and form to insert and refer to structure, and the first bonding jumper 21 meets power vd D, 22 ground connection GND of the second metal.Because the second bonding jumper 22 ground connection of MOM capacitance structure 20, its equivalence is the grounded metal line of square, therefore can shield well the magnetic interference of square spiral circle, the first metal wire 21 then is equivalent to connect a MOM electric capacity after connecing supply voltage between supply voltage and ground, play the pressure stabilization function of supply voltage, thereby take full advantage of the larger area of below, on-chip inductor zone, need not additionally to increase again chip area traditional large-scale mos capacitance is set.
To sum up, induction structure proposed by the invention, utilize the MOM capacitance structure to form the screen of on-chip inductor below, between inductance and substrate, play the buffer action of inductance and substrate, inductance and peripheral circuits, in addition, the MOM capacitance structure is as large voltage stabilizing mos capacitance, be connected between the supply voltage and ground of chip, played the pressure stabilization function of supply voltage.Therefore, compared to prior art, the present invention takes full advantage of the larger area of on-chip inductor below, has effectively reduced conventional power source voltage voltage stabilizing MOS transistor at the area that chip takies, and provides cost savings.
Although the present invention discloses as above with preferred embodiment; right described many embodiment only give an example for convenience of explanation; be not to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion so that claims are described.
Claims (7)
1. induction structure, the screen that comprises on-chip inductor and be positioned at described on-chip inductor below, described screen comprises at least one screen unit, the vortex flow direction quadrature that described screen unit and described on-chip inductor produce is characterized in that,
Described screen unit is comprised of the MOM capacitance structure, and described MOM capacitance structure comprises:
Square first bonding jumper of one group of certain intervals that is parallel to each other and has, this end sealing of organizing the first bonding jumper links to each other;
Square second bonding jumper of one group of certain intervals that is parallel to each other and has, this end sealing of organizing the second bonding jumper links to each other, this is organized the first bonding jumper and this and organizes the second bonding jumper and be positioned at layer metal level and form to insert and refer to structure, described the first bonding jumper connects power supply, described the second metal strips for grounding has dielectric medium between described the first bonding jumper and described the second bonding jumper.
2. induction structure according to claim 1 is characterized in that, described MOM capacitance structure comprises that many groups are positioned at the first bonding jumper of different metal layer and the second bonding jumper that many groups are positioned at the different metal layer.
3. induction structure according to claim 2 is characterized in that, by through-hole interconnection, passes through through-hole interconnection between described second bonding jumper of different metal layer between described first bonding jumper of different metal layer.
4. induction structure according to claim 3, it is characterized in that, described MOM capacitance structure comprises 4 group of first bonding jumper that lays respectively at 4 layers of metal level and 4 group of second bonding jumper that lays respectively at 4 layers of metal level, and described the first bonding jumper and described the second bonding jumper that are positioned at layer metal level form the slotting structure that refers to.
5. induction structure according to claim 1 is characterized in that, the material of described dielectric medium is silicon dioxide.
6. induction structure according to claim 1 is characterized in that, described on-chip inductor is the square spiral circle, and the number of described screen unit is 4, and described 4 screen units are with the Central Symmetry distribution of described on-chip inductor.
7. induction structure according to claim 6 is characterized in that, has the interval between the described screen unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210496838.5A CN102956622B (en) | 2012-11-29 | 2012-11-29 | A kind of induction structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210496838.5A CN102956622B (en) | 2012-11-29 | 2012-11-29 | A kind of induction structure |
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| CN102956622A true CN102956622A (en) | 2013-03-06 |
| CN102956622B CN102956622B (en) | 2017-03-15 |
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| CN201210496838.5A Active CN102956622B (en) | 2012-11-29 | 2012-11-29 | A kind of induction structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337494A (en) * | 2013-06-08 | 2013-10-02 | 上海集成电路研发中心有限公司 | Inductance structure |
| CN111128952A (en) * | 2018-10-30 | 2020-05-08 | 力晶科技股份有限公司 | Metal-oxide-metal capacitor structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010013626A1 (en) * | 2000-02-14 | 2001-08-16 | Hiroki Fujii | Semiconductor device |
| CN101131998A (en) * | 2006-08-22 | 2008-02-27 | 联华电子股份有限公司 | Conductor screening pattern and semiconductor structure with inductance element |
| US20110133308A1 (en) * | 2009-05-22 | 2011-06-09 | Chan Kuei-Ti | Semiconductor device with oxide define pattern |
| US8106479B1 (en) * | 2008-10-01 | 2012-01-31 | Qualcomm Atheros, Inc. | Patterned capacitor ground shield for inductor in an integrated circuit |
| CN102446898A (en) * | 2011-12-27 | 2012-05-09 | 杭州电子科技大学 | Integrated circuit on-chip inductor structure with multiple substrate shielding layers |
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2012
- 2012-11-29 CN CN201210496838.5A patent/CN102956622B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010013626A1 (en) * | 2000-02-14 | 2001-08-16 | Hiroki Fujii | Semiconductor device |
| CN101131998A (en) * | 2006-08-22 | 2008-02-27 | 联华电子股份有限公司 | Conductor screening pattern and semiconductor structure with inductance element |
| US8106479B1 (en) * | 2008-10-01 | 2012-01-31 | Qualcomm Atheros, Inc. | Patterned capacitor ground shield for inductor in an integrated circuit |
| US20110133308A1 (en) * | 2009-05-22 | 2011-06-09 | Chan Kuei-Ti | Semiconductor device with oxide define pattern |
| CN102446898A (en) * | 2011-12-27 | 2012-05-09 | 杭州电子科技大学 | Integrated circuit on-chip inductor structure with multiple substrate shielding layers |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337494A (en) * | 2013-06-08 | 2013-10-02 | 上海集成电路研发中心有限公司 | Inductance structure |
| CN111128952A (en) * | 2018-10-30 | 2020-05-08 | 力晶科技股份有限公司 | Metal-oxide-metal capacitor structure |
| CN111128952B (en) * | 2018-10-30 | 2021-12-17 | 力晶积成电子制造股份有限公司 | Metal-oxide-metal capacitor structure |
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| Publication number | Publication date |
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| CN102956622B (en) | 2017-03-15 |
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