CN203351579U - Heavy current field effect transistor - Google Patents
Heavy current field effect transistor Download PDFInfo
- Publication number
- CN203351579U CN203351579U CN2013204021900U CN201320402190U CN203351579U CN 203351579 U CN203351579 U CN 203351579U CN 2013204021900 U CN2013204021900 U CN 2013204021900U CN 201320402190 U CN201320402190 U CN 201320402190U CN 203351579 U CN203351579 U CN 203351579U
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- CN
- China
- Prior art keywords
- field effect
- heat sink
- effect transistor
- lead
- root
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model discloses a heavy current field effect transistor, including a heat sink, an insulating shell, a field effect transistor chip, a drain electrode pin, a grid electrode pin and a source electrode pin. The heat sink is embedded on the outer surface of the insulating shell and form an enclosed package cavity with the insulating shell. The heat sink and the drain electrode pin are connected as a whole. The root of the drain electrode pin, the root of the grid electrode pin and the root of the source electrode pin are fixed on the insulating shell and extend in to the package cavity. The field effect transistor chip is arranged at the center of the front surface of the heat sink. A drain electrode of the field effect transistor chip is directly attached to the heat sink, a grid electrode of the field effect transistor chip is connected with the grid electrode pin through a first gold thread, and a source electrode of the field effect transistor chip is connected with the source electrode pin through a second gold thread. The heavy current field effect transistor is good in heat radiation effect, high in working efficiency and long is service life, and can be widely applied to the semiconductor industry.
Description
Technical field
The utility model relates to a kind of semiconductor device, particularly relates to a kind of large electric current field effect transistor of good heat dissipation effect.
Background technology
At present field effect transistor commonly used is mainly by the epoxy encapsulation body and be encapsulated in the chip of epoxy encapsulation body inside and lead frame etc. forms.And existing large electric current field effect transistor generally adopts the TO-220 encapsulation, adopt the TO-220 encapsulation can load large-sized chip, but chip easily causes the field effect transistor temperature not stop to rise because large electric current produces high heat after energising, thereby cause the electrical quantity of field effect transistor to change, further cause the temperature of field effect transistor to raise, when temperature rises to a certain degree, field effect transistor will lose efficacy and can't recover.Therefore, current TO-220 encapsulation can't meet the radiating requirements of large electric current field effect transistor.
The utility model content
In order to solve above-mentioned technical problem, the purpose of this utility model is to provide a kind of large electric current field effect transistor of good heat dissipation effect.
The utility model solves the technical scheme that its technical problem adopts:
A kind of large electric current field effect transistor, comprise heat sink, insulation crust, field effect tube chip, drain lead, gate lead and source lead;
On the described heat sink outer surface that is embedded in insulation crust and form an airtight encapsulation cavity with insulation crust, described heat sink and drain lead are connected as a single entity, and the root of the root of described drain lead, the root of gate lead and source lead is fixed on insulation crust and stretches in the encapsulation cavity;
Described field effect tube chip is arranged on place in the middle of heat sink front, the drain electrode of described field effect tube chip directly be mounted on heat sink on, the grid of described field effect tube chip is connected with gate lead by the first gold thread, and the source electrode of described field effect tube chip is connected with source lead by the second gold thread.
Further, be filled with the heat conductive insulating colloid of root, the first gold thread, the second gold thread and field effect tube chip of root, the source lead of root for coating heat sink front, drain lead, gate lead in described encapsulation cavity.
Further, described field effect transistor also is provided with the location hole that runs through heat sink, encapsulates cavity and insulation crust.
Further, also be provided with the first location notch and the second location notch on described insulation crust, described the first location notch and the second location notch and location hole are on the same level line.
Further, the thickness of described insulation crust is 4 ~ 6mm, and the length of described insulation crust is 20 ~ 22mm, the width of described insulation crust is 15 ~ 18mm, described heat sink thickness is 0.8 ~ 1.2mm, and described heat sink length is 15 ~ 18mm, and described heat sink width is 12 ~ 15mm.
Further, the thickness of described drain lead, gate lead and source lead is 0.5mm, and the root width of described gate lead and the root width of source lead are 1.0mm, and the root width of described drain lead is 1.5mm.
Further, the diameter of described the first gold thread and the second gold thread is 1.2 μ m.
The beneficial effects of the utility model are: a kind of large electric current field effect transistor of the present utility model, on insulation crust, be embedded with heat sink, and heat sink integrated connection of the drain lead with field effect transistor, the drain electrode of field effect tube chip directly be mounted on heat sink on, source electrode and grid are connected to corresponding pin by gold thread respectively, radiating effect is better, has improved operating efficiency, has also extended the useful life of field effect transistor simultaneously.
The accompanying drawing explanation
Below in conjunction with drawings and Examples, the utility model is described in further detail.
Fig. 1 is the side schematic view of large electric current field effect transistor of the present utility model;
Fig. 2 is the front schematic view of large electric current field effect transistor of the present utility model;
Fig. 3 is the schematic rear view of large electric current field effect transistor of the present utility model.
Embodiment
With reference to Fig. 1, Fig. 2 and Fig. 3, the utility model provides a kind of large electric current field effect transistor, comprises heat sink 1, insulation crust 2, field effect tube chip 3, drain lead 4, gate lead 5 and source lead 6;
Described heat sink 1 is embedded on the outer surface of insulation crust 2 and with insulation crust 2 and forms an airtight encapsulation cavity, described heat sink 1 is connected as a single entity with drain lead 4, and the root of the root of described drain lead 4, gate lead 5 and the root of source lead 6 are fixed on insulation crust 2 and stretch in the encapsulation cavity;
Described field effect tube chip 3 is arranged on heat sink 1 middle place, front, the drain electrode of described field effect tube chip 3 directly is mounted on heat sink 1, the grid of described field effect tube chip 3 is connected with gate lead 5 by the first gold thread 7-1, and the source electrode of described field effect tube chip 3 is connected with source lead 6 by the second gold thread 7-2.
The bottom of field effect tube chip 3 is drain D, mounts on heat sink 1 by conducting resinl, or is mounted on heat sink 1 and is connected on drain lead 4 by eutectic weldering mode; The front of field effect tube chip 3 is grid G and source S, and grid G is by the first gold thread 7-1 and gate lead 5, and source S is connected with source lead 6 by the second gold thread 7-2.
Do not mark the encapsulation cavity in Fig. 1 to Fig. 3, the size of encapsulation cavity is mainly to be determined by the shell thickness of insulation crust 2, and shell thickness is less, encapsulates cavity larger, and shell thickness is larger, encapsulates cavity less.
Be further used as preferred embodiment, be filled with the heat conductive insulating colloid of root, the first gold thread 7-1, the second gold thread 7-2 and field effect tube chip 3 of root, the source lead 6 of root, the gate lead 5 of front for coating heat sink 1, drain lead 4 in described encapsulation cavity.Here, the heat conductive insulating colloid is selected the heat-conducting effect insulating cement better than resin.
Be further used as preferred embodiment, described field effect transistor also is provided with the location hole 8 that runs through heat sink 1, encapsulation cavity and insulation crust 2.
Be further used as preferred embodiment, also be provided with the first location notch 9-1 and the second location notch 9-2 on described insulation crust 2, described the first location notch 9-1 and the second location notch 9-2 and location hole 8 are on the same level line.
Be further used as preferred embodiment, the thickness of described insulation crust 2 is 4 ~ 6mm, the length of described insulation crust 2 is 20 ~ 22mm, the width of described insulation crust 2 is 15 ~ 18mm, described heat sink 1 thickness is 0.8 ~ 1.2mm, described heat sink 1 length is 15 ~ 18mm, and described heat sink 1 width is 12 ~ 15mm.
Be further used as preferred embodiment, the thickness of described drain lead 4, gate lead 5 and source lead 6 is 0.5mm, the root width of described gate lead 5 and the root width of source lead 5 are 1.0mm, and the root width of described drain lead 4 is 1.5mm.
Be further used as preferred embodiment, the diameter of described the first gold thread 7-1 and the second gold thread 7-2 is 1.2 μ m.
More than that better enforcement of the present utility model is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to the utility model spirit, and the modification that these are equal to or replacement all are included in the application's claim limited range.
Claims (7)
1. a large electric current field effect transistor, is characterized in that, comprises heat sink (1), insulation crust (2), field effect tube chip (3), drain lead (4), gate lead (5) and source lead (6);
Described heat sink (1) is embedded on the outer surface of insulation crust (2) and forms an airtight encapsulation cavity with insulation crust (2), described heat sink (1) is connected as a single entity with drain lead (4), and the root of the root of described drain lead (4), gate lead (5) and the root of source lead (6) are fixed on insulation crust (2) and go up and stretch in the encapsulation cavity;
Described field effect tube chip (3) is arranged on the middle place, front of heat sink (1), the drain electrode of described field effect tube chip (3) directly is mounted on heat sink (1), the grid of described field effect tube chip (3) is connected with gate lead (5) by the first gold thread (7-1), and the source electrode of described field effect tube chip (3) is connected with source lead (6) by the second gold thread (7-2).
2. a kind of large electric current field effect transistor according to claim 1, it is characterized in that, be filled with the heat conductive insulating colloid of root, the first gold thread (7-1), the second gold thread (7-2) and field effect tube chip (3) of root, the source lead (6) of root, the gate lead (5) of front, the drain lead (4) of heat sink for coating (1) in described encapsulation cavity.
3. a kind of large electric current field effect transistor according to claim 1, is characterized in that, described field effect transistor also is provided with the location hole (8) that runs through heat sink (1), encapsulation cavity and insulation crust (2).
4. a kind of large electric current field effect transistor according to claim 3, it is characterized in that, also be provided with the first location notch (9-1) and the second location notch (9-2) on described insulation crust (2), described the first location notch (9-1) and the second location notch (9-2) and location hole (8) are on the same level line.
5. a kind of large electric current field effect transistor according to claim 1, it is characterized in that, the thickness of described insulation crust (2) is 4 ~ 6mm, the length of described insulation crust (2) is 20 ~ 22mm, the width of described insulation crust (2) is 15 ~ 18mm, the thickness of described heat sink (1) is 0.8 ~ 1.2mm, and the length of described heat sink (1) is 15 ~ 18mm, and the width of described heat sink (1) is 12 ~ 15mm.
6. a kind of large electric current field effect transistor according to claim 5, it is characterized in that, the thickness of described drain lead (4), gate lead (5) and source lead (6) is 0.5mm, the root width of the root width of described gate lead (5) and source lead (5) is 1.0mm, and the root width of described drain lead (4) is 1.5mm.
7. a kind of large electric current field effect transistor according to claim 1, is characterized in that, the diameter of described the first gold thread (7-1) and the second gold thread (7-2) is 1.2 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013204021900U CN203351579U (en) | 2013-07-05 | 2013-07-05 | Heavy current field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013204021900U CN203351579U (en) | 2013-07-05 | 2013-07-05 | Heavy current field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203351579U true CN203351579U (en) | 2013-12-18 |
Family
ID=49751444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013204021900U Expired - Fee Related CN203351579U (en) | 2013-07-05 | 2013-07-05 | Heavy current field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203351579U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105252712A (en) * | 2015-10-26 | 2016-01-20 | 张家港凯思半导体有限公司 | Direct insertion type discrete device, manufacturing method and forming die |
-
2013
- 2013-07-05 CN CN2013204021900U patent/CN203351579U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105252712A (en) * | 2015-10-26 | 2016-01-20 | 张家港凯思半导体有限公司 | Direct insertion type discrete device, manufacturing method and forming die |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131218 Termination date: 20200705 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |