CN201845754U - 碳纳米管团簇作为芯片凸点的倒装芯片封装结构 - Google Patents

碳纳米管团簇作为芯片凸点的倒装芯片封装结构 Download PDF

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CN201845754U
CN201845754U CN 201020262499 CN201020262499U CN201845754U CN 201845754 U CN201845754 U CN 201845754U CN 201020262499 CN201020262499 CN 201020262499 CN 201020262499 U CN201020262499 U CN 201020262499U CN 201845754 U CN201845754 U CN 201845754U
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chip
carbon nano
nano tube
salient point
salient points
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郭洪岩
赖志明
陈锦辉
张黎
陈栋
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Jiangyin Changdian Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本实用新型涉及一种碳纳米管团簇作为芯片凸点的倒装芯片封装结构，所述封装结构包括基板(301)和芯片(201)，芯片(201)表面的芯片端子(202)上连接有凸点，芯片(201)通过其表面的凸点倒装于基板(301)正面，基板(301)背面的焊盘(302)上设置有焊球(305)，其特征在于所述凸点采用碳纳米管团簇(103)。本实用新型倒装芯片封装结构能减小芯片与凸点间热应力，缓解芯片与基板间热应力以及克服锡基焊球凸点的形变累计损伤。

Description

碳纳米管团簇作为芯片凸点的倒装芯片封装结构
（一）技术领域
本实用新型涉及一种具有凸点结构的倒装芯片封装结构。属半导体技术领域。
(二)背景技术
随着半导体技术的发展，芯片的特征尺寸不断缩小，集成度不断提高，其端子数目不断增加，端子间的节距也不断缩小。当端子间的节距缩小到70um以下、端子数目多于1000以上时，传统的引线键和的封装方式已经不再适用。对于这种多端子数和端子的节距小的芯片的封装目前大部分采用倒装芯片的封装方式来实现。
目前倒装芯片所采用的通常是铜柱凸点或者锡基焊料凸点。然而，由于铜/焊料与半导体材料(通常为硅或者砷化镓)热膨胀系数相差比较大，在芯片服役过程中由于温度变化而产生的热应力通常会集中在凸点与芯片结合处的边角部位，从而造成凸点断裂失效。铜柱凸点由于其刚性大，变形困难，很难缓解芯片与基板之间由于热适配造成的热应力，从而造成芯片的断裂失效。虽然锡基焊料凸点可以通过蠕变塑性变形在一定程度上缓解芯片与基板热失配造成的应力，但是这种变形会对锡基焊料凸点造成不可逆转的损伤累积，最终导致锡基焊料凸点的断裂失效。因此必须寻找一种新的凸点材料及封装方法来解决目前倒装芯片封装中存在的上述问题。
(三)发明内容
本实用新型的目的在于克服上述不足，提供一种能减小芯片与凸点间热应力、缓解芯片与基板间热应力以及克服焊球凸点的形变累计损伤的碳纳米管团簇作为芯片凸点的倒装芯片封装结构。
本实用新型的目的是这样实现的：一种碳纳米管团簇作为芯片凸点的倒装芯片封装结构，包括基板和芯片，芯片表面的芯片端子上连接有凸点，芯片通过其表面的凸点倒装于基板正面，基板背面的焊盘上设置有焊球，其特征在于所述凸点采用碳纳米管团簇。
本实用新型的有益效果是：
1、由于本实用新型采用的碳纳米管团簇具有与半导体材料硅相近的热膨胀系数，因此减小了芯片与凸点间由于热失配而产生的热应力，增加了封装结构的可靠性。
2、由于碳纳米管团簇凸点比铜柱凸点刚性低易发生弹性变形，因此可以通过碳纳米管团簇凸点的弹性变形有效的缓解芯片与基板间由于热失配导致的热应力。
3、由于碳纳米管团簇凸点屈服强度高不会发生塑性变形，因此本实用新型克服了焊球凸点的塑性形变累计损伤的缺点，提高了凸点本身的可靠性。
(四)附图说明
图1A～图1C为本实用新型形成碳纳米管团簇阵列的流程示意图。
图2A～图2D为本实用新型在芯片表面形成碳纳米管团簇凸点的流程示意图。
图3A～图3E为本实用新型将具有碳纳米管团簇凸点的芯片倒装到基板上并形成球栅封装结构的流程示意图。
附图标记：
衬底101、掩膜102、碳纳米管团簇103；
芯片201、芯片端子202、第一导电胶或导电膜203；
基板301、焊盘302、第二导电胶或导电膜303、底填料304、焊球305。
(五)具体实施方式
参见图3E，本实用新型碳纳米管团簇作为芯片凸点的倒装芯片封装结构，包括基板301和芯片201，芯片201表面的芯片端子202上连接有凸点，芯片201通过其表面的凸点倒装于基板301正面，基板301背面的焊盘302上设置有焊球305，所述凸点采用碳纳米管团簇103。
本实用新型封装结构的制作方法主要包含以下三个步骤：
步骤一、在衬底上生长碳纳米管团簇阵列
参见图1A～图1C，图1A～图1C为本实用新型形成碳纳米管团簇阵列的流程示意图。如图1A所示，首先在衬底101上通过光刻或其他等效的方式形成掩膜102，掩膜要根据芯片上芯片端子202的分布来设计。衬底101可以是硅或者陶瓷等材料。然后在形成掩膜的衬底上生长碳纳米管团簇阵列103，如图1B所示。碳纳米管团簇阵列103生长结束后将掩膜移除。至此便得到了与芯片端子分布相同的碳纳米管团簇阵列。如图1C所示。一般情况下碳纳米管团簇直径可以在几微米到几百微米，高度也可以达到100微米以上。
步骤二、碳纳米管团簇阵列转移到芯片表面
参见图2A～图2D，图2A～图2D为本实用新型在芯片表面形成碳纳米管团簇凸点的流程示意图。如图2B所示，首先在芯片201表面涂布一层第一导电胶或导电膜203。将步骤一得到的碳纳米管团簇与芯片上对应的芯片端子202对准后(如图1C所示)粘连到芯片表面。粘连结束后将用于碳纳米管团簇生长的衬底去除，如图2D所示。最终在芯片表面制备了碳纳米管团簇凸点。
步骤三、将具有或碳纳米管团簇凸点的芯片倒装到基板上
参见图3A～图3E，图3A～图3E为本实用新型将具有碳纳米管团簇凸点的芯片倒装到基板上并形成球栅(BGA)封装结构的流程示意图。如图3B所示，首先在基板301上涂布一层第二导电胶或导电膜303。用于该结构的基板301可以是(但不局限于)FR-4、陶瓷和玻璃等。然后将步骤二制备的具有碳纳米管团簇凸点的芯片倒装到基板301上，如图3C所示。倒装结束后，用底填料304填充所述凸点的间隙，以此来提高封装结构的可靠性。如图3D所示。最后在基板301背面的焊盘302上放置焊球305并回流，最终得到如图3E所示的倒装芯片封装结构。

Claims (1)

1.一种碳纳米管团簇作为芯片凸点的倒装芯片封装结构，包括基板(301)和芯片(201)，芯片(201)表面的芯片端子(202)上连接有凸点，芯片(201)通过其表面的凸点倒装于基板(301)正面，基板(301)背面的焊盘(302)上设置有焊球(305)，其特征在于所述凸点采用碳纳米管团簇(103)。
CN 201020262499 2010-07-19 2010-07-19 碳纳米管团簇作为芯片凸点的倒装芯片封装结构 Expired - Lifetime CN201845754U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227121A (zh) * 2013-04-16 2013-07-31 上海大学 通过碳纳米管凸点实现玻璃覆晶封装的方法
CN106158828A (zh) * 2015-04-16 2016-11-23 清华大学 片间互连结构、片间互连结构的制造方法及封装结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227121A (zh) * 2013-04-16 2013-07-31 上海大学 通过碳纳米管凸点实现玻璃覆晶封装的方法
CN106158828A (zh) * 2015-04-16 2016-11-23 清华大学 片间互连结构、片间互连结构的制造方法及封装结构

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Granted publication date: 20110525