CN201584408U - Power module - Google Patents

Power module Download PDF

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Publication number
CN201584408U
CN201584408U CN2009202843478U CN200920284347U CN201584408U CN 201584408 U CN201584408 U CN 201584408U CN 2009202843478 U CN2009202843478 U CN 2009202843478U CN 200920284347 U CN200920284347 U CN 200920284347U CN 201584408 U CN201584408 U CN 201584408U
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CN
China
Prior art keywords
copper layer
ceramic
layer
power
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2009202843478U
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Chinese (zh)
Inventor
庄伟东
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NANJING YINMAO MICROELECTRONIC MANUFACTURING CO LTD
Original Assignee
NANJING YINMAO MICROELECTRONIC MANUFACTURING CO LTD
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Priority to CN2009202843478U priority Critical patent/CN201584408U/en
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Publication of CN201584408U publication Critical patent/CN201584408U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

The utility model relates to a power module, and aims to provide a power module with low stray inductance. The technical scheme is as follows: the power module comprises a ceramic copper coated substrate, a power chip, a signal terminal and a power terminal; the ceramic copper coated substrate is sequentially provided with a first front-side copper layer, a first ceramic layer and a first back side copper layer from up to down; the first front-side copper layer comprises a line structure of the module and a positive bus; a laminated ceramic copper coated substrate is arranged above the first front-side copper layer which serves as the positive bus; the laminated ceramic copper coated substrate sequentially comprises a second back side copper layer, a second ceramic layer and a second front-side copper layer from down to up; and the second front-side copper layer serves as the negative bus of the module.

Description

A kind of power model
Technical field
The utility model relates to the power electronic device field, is specifically related to a kind of power model.
Background technology
The stray inductance of power model inside is to the performance of module, and even the reliability service of power system has material impact.In the design, under the prerequisite that satisfies conditions such as voltage, electric current, module heat dissipating, the stray inductance of inside modules must be effectively controlled.High stray inductance is not only at IGBT, and MOSFET constant power device two ends produce overvoltage, and can cause electromagnetic interference in inside modules, and influence is controlled the switch of module, even burns power model.
Overvoltage:
v overshoot = L stray × di dt
Lstray=inside modules stray inductance, di/dt=current changing rate, A/us
Voltage between module I GBT collector electrode-emitter:
v CE＝v overshoot+v DC-link
VDC-link=module bus voltage
For example: Lstray=100nH, the current changing rate di/dt=2000A/us during module shuts down, so, overshoot voltage Vovershoot=200V
IGBT module to withstand voltage 600V, when bus voltage 300V, if the stray inductance that system wiring causes also is 100nH, the overshoot voltage at power device two ends can reach 700V during shutoff, far surpassed the withstand voltage of IGBT, caused that probably device damages because of overvoltage.
Be to improve the heat radiation of power device, and provide enough withstand voltage, the current power module adopts ceramic copper-clad base plate substantially.Ceramic material generally adopts high-purity alpha-alumina.For further improving the heat-sinking capability of substrate, high power module also can adopt the aluminium nitride copper-clad base plate.The structure of ceramic copper-clad base plate is seen Fig. 1, and its front 1 and the back side 2 are the copper layer, and the centre is a ceramic layer 3.The thickness of copper layer is usually between 0.1 millimeter 0.5 millimeter, and the thickness of ceramic layer is usually between 0.25 millimeter to 0.64 millimeter, its typical performance is as follows: purity＞96%, thermal coefficient of expansion is 6.5ppm/K, thermal conductivity＞20W/mK, dielectric constant is 8.1, and is withstand voltage＞25kV/mm, specific insulation＞10 14m.Back side copper layer 2 is connected with the power model base plate by brazing mode usually, is the main approach of heat radiation.Front copper layer etches different figures, as shown in Figure 1 according to the line construction of module.Power chip is connected to front copper layer 1 by modes such as soldering, sintering.Front copper layer 1 composition module internal circuit, front copper layer 1 also comprise positive bus 4 and negative bus 5, because front copper layer 1 is a planar structure, positive bus 4 can only be arranged in parallel with negative bus 5, causes stray inductance (Lstray) higher.
Summary of the invention
The purpose of this utility model is to overcome the defective of prior art, provides a kind of stray inductance low power model.
The technical scheme that realizes the utility model purpose is: a kind of power model, comprise ceramic copper-clad base plate, power chip, signal terminal and power terminal, described ceramic copper-clad base plate is provided with the first front copper layer from top to bottom successively, first ceramic layer and first back side copper layer, the first front copper layer comprises the line construction and the positive bus of module, above as the first front copper layer of described positive bus, be provided with the multi-layered ceramic copper-clad base plate, the multi-layered ceramic copper-clad base plate comprises second back side copper layer from bottom to up successively, second ceramic layer and the second front copper layer, the second front copper layer is as the negative bus of module.
Be provided with two ceramic copper-clad base plates of ceramic copper-clad base plate and multi-layered ceramic copper-clad base plate in the technique scheme, the upper and lower surface of two ceramic copper-clad base plates all is covered with the copper layer.The copper layer of described second ceramic layer and its upper and lower surface constitutes the multi-layered ceramic copper-clad base plate, promptly is provided with the multi-layered ceramic copper-clad base plate on the copper layer of front, as the negative bus of power model inside.Power chip is connected to front copper layer by modes such as soldering, sintering, and positive bus is connected with power chip by supersonic bonding or soldering with negative bus.
As further improvement of the utility model, described first back side copper layer can be connected with the first ceramic layer front copper layer by brazing mode, and second back side copper layer of multi-layered ceramic copper-clad base plate is by soldering and power model base plate, and promptly ceramic copper-clad base plate connects.
The utility model adopts the multi-layered ceramic copper-clad base plate, negative bus is superimposed upon on the positive bus, and utilizes second ceramic layer to insulate, thereby reach the purpose that reduces stray inductance.
Description of drawings
Fig. 1 is the ceramic copper-clad base plate structural representation of the utility model background technology
Fig. 2 is the utility model embodiment 1 ceramic copper-clad base plate structural representation
Fig. 3 is the utility model embodiment 1 power model structural representation
Embodiment
Be described further below in conjunction with embodiment.
Embodiment 1
Shown in Fig. 2 and 3, a kind of power model 10, comprise ceramic copper-clad base plate 20, power chip 6, positive signal terminal 8, negative signal terminal 9 and power terminal 13, ceramic copper-clad base plate 20 is provided with front copper layer 1 from top to bottom successively, first ceramic layer 2 and first back side copper layer 3, the first front copper layer 1 comprises the line construction and the positive bus 4 of module, above as the front copper layer of positive bus 4, be provided with multi-layered ceramic copper-clad base plate 30, multi-layered ceramic copper-clad base plate 30 comprises ceramic layer 7, second back side copper layer below second ceramic layer 7, with the second top front copper layer of second ceramic layer 7, the second front copper layer is as the negative bus 5 of power model 10.Power chip 6 is connected to front copper layer 1 by modes such as soldering, sintering.Negative bus 5 is connected with power chip 6 by supersonic bonding 12.Positive bus 4 is connected with positive signal terminal 8, negative signal terminal 9 respectively by supersonic bonding 12 with negative bus 5.Negative bus 5 also is connected with power chip 6 by soldering 11 among Fig. 3.

Claims (5)

1. power model, comprise ceramic copper-clad base plate, power chip, signal terminal and power terminal, described ceramic copper-clad base plate is provided with the first front copper layer from top to bottom successively, first ceramic layer and first back side copper layer, the first front copper layer comprises the line construction and the positive bus of module, it is characterized in that, above as the first front copper layer of described positive bus, be provided with the multi-layered ceramic copper-clad base plate, the multi-layered ceramic copper-clad base plate comprises second back side copper layer from bottom to up successively, be provided with second ceramic layer above second back side copper layer, be covered with the second front copper layer on second ceramic layer, the second front copper layer is as the negative bus of module.
2. power model according to claim 1 is characterized in that, described second back side copper layer is connected with the first front copper layer by brazing mode.
3. power model according to claim 1 is characterized in that, positive bus is connected with power chip by supersonic bonding with negative bus.
4. power model according to claim 1 is characterized in that, positive bus is connected with power chip by soldering with negative bus.
5. power model according to claim 1 is characterized in that, positive bus is connected with signal terminal by supersonic bonding with negative bus.
CN2009202843478U 2009-12-08 2009-12-08 Power module Expired - Lifetime CN201584408U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009202843478U CN201584408U (en) 2009-12-08 2009-12-08 Power module

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Application Number Priority Date Filing Date Title
CN2009202843478U CN201584408U (en) 2009-12-08 2009-12-08 Power module

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CN201584408U true CN201584408U (en) 2010-09-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738099A (en) * 2012-06-05 2012-10-17 嘉兴斯达微电子有限公司 Novel high-reliability power module
CN112928089A (en) * 2021-01-29 2021-06-08 西安理工大学 Structure for reducing displacement current of high-voltage SiC module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738099A (en) * 2012-06-05 2012-10-17 嘉兴斯达微电子有限公司 Novel high-reliability power module
CN112928089A (en) * 2021-01-29 2021-06-08 西安理工大学 Structure for reducing displacement current of high-voltage SiC module

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Granted publication date: 20100915

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