CN104465605A - Semiconductor chip packaging structure - Google Patents
Semiconductor chip packaging structure Download PDFInfo
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- CN104465605A CN104465605A CN201410708696.3A CN201410708696A CN104465605A CN 104465605 A CN104465605 A CN 104465605A CN 201410708696 A CN201410708696 A CN 201410708696A CN 104465605 A CN104465605 A CN 104465605A
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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Abstract
The invention provides a semiconductor chip packaging structure. The semiconductor chip packaging structure comprises a bottom plate, at least one chip pair and electric conduction pieces, wherein a plurality of independent electric conduction areas are arranged on the bottom plate, the chip pairs are arranged on the bottom plate and electrically connected with the bottom plate, the electric conduction pieces are arranged on the chip pairs and used in cooperation with the electric conduction areas for making a first chip and a second chip in each chip pair connected in series. The semiconductor chip packaging structure is compact and simple in structure, the double-face heat dissipation can be conducted through the electric conduction pieces and the bottom plate, the service life of devices is prolonged, and the reliability of the devices is improved.
Description
Technical field
The present invention relates to chip encapsulation technology field.Relate in particular to a kind of semiconductor chip package.
Background technology
The power electronics semiconductor device of discrete encapsulation is widely used in numerous occasions such as Switching Power Supply, inverter and motor driver.But discrete encapsulating structure not only increases the overall dimensions of device, also add the distance of chip chamber, therefore the line of the power electronics semiconductor device of discrete encapsulation is connected usually through the prefabricated conducting wire of pcb board, but this will the three dimensions that takies of increasing circuit, is unfavorable for the miniaturization of power-supply system.
Along with " energy-saving and emission-reduction " are brought up to fundamental state policy height by country, Energy Efficiency Standard improves constantly, and the development trend of power device is: high-breakdown-voltage, low on-resistance, big current, elevated operating temperature, low switching losses and high switching speed.Power device based on third generation semi-conducting material is developed, and comprises chip material, encapsulation and integration technique and encapsulation critical material etc. and causes the extensive concern comprising academia and industrial quarters.As everyone knows, based on the structural design of third generation semiconductor die package and the acting in conjunction of various crucial encapsulating material by the combination property of remarkable boost device.But the current chip based on third generation semiconductor adopts the deriving technology of ripe wire bonding (wire bonding) technology encapsulation or similar wire bonding to realize mostly both at home and abroad.It is complicated mainly to there is encapsulating structure level in such technology, and interface resistance is large and be unfavorable for heat radiation, electrode contact area little and contact resistance causes greatly that device loss is high, device mainly relies on single channel to dispel the heat to make the defects such as low and poor reliability device lifetime.
Summary of the invention
For this reason, technical problem to be solved by this invention is semiconductor chip package of the prior art, there is level complexity, interface resistance is large and be unfavorable for heat radiation, electrode contact area little and contact resistance causes greatly that device loss is high, device mainly relies on single channel to dispel the heat to make the defects such as low and poor reliability device lifetime, thus provide a kind of compact conformation simple, can the semiconductor chip package of two-side radiation.
For solving the problems of the technologies described above, technical scheme of the present invention is as follows:
The invention provides a kind of semiconductor chip package, comprising:
Base plate, it has multiple independently conductive region;
At least one chip pair, to be arranged on described base plate and to be electrically connected with described base plate;
Conducting strip, is arranged on described chip to upper, with described conductive region acting in conjunction, the first chip of described chip centering and the second chip-in series is connected.
Semiconductor chip package of the present invention, the outer surface of described conducting strip is fin shape.
Semiconductor chip package of the present invention, described conducting strip is etched with insulation tank, and described conducting strip is divided into control end contact zone and join domain;
Described control end contact zone is electrically connected with the control end of described first chip, and described join domain is electrically connected with the output of described first chip and the input of described second chip.
Semiconductor chip package of the present invention, described conductive region comprises:
First conductive region, is electrically connected with described control end contact zone;
Second conductive region, is electrically connected with the input of described first chip;
3rd conductive region, is electrically connected with the control end of described second chip;
4th conductive region, is electrically connected with the output of described second chip;
5th conductive region, is electrically connected with described join domain.
Semiconductor chip package of the present invention, the conductive metal layer of described base plate is etched with many bar insulations groove, and described conductive metal layer is divided into multiple independently conductive region.
Semiconductor chip package of the present invention, also comprises:
First diode chip for backlight unit, be arranged on described second conductive region, the negative pole of described first diode chip for backlight unit is electrically connected with the input of described first chip by described second conductive region, and the positive pole of described first diode chip for backlight unit is electrically connected with the output of described first chip by described join domain;
Second diode chip for backlight unit, be arranged on described 4th conductive region, the positive pole of described second diode chip for backlight unit is electrically connected with the output of described second chip by described 4th conductive region, and the negative pole of described second diode chip for backlight unit is electrically connected with the input of described second chip by described join domain.
Semiconductor chip package of the present invention, described first chip and described second chip are controllable semiconductor chip.
Semiconductor chip package of the present invention, described base plate comprises and covers copper ceramic wafer, aluminium base with insulating barrier.
Semiconductor chip package of the present invention, described conducting strip is flexible copper thin slice.
Technique scheme of the present invention has the following advantages compared to existing technology:
The invention provides a kind of semiconductor chip package, comprise base plate, it has multiple independently conductive region, at least one chip pair, to be arranged on base plate and to be electrically connected with base plate, conducting strip, is arranged on chip to upper, with conductive region acting in conjunction, the first chip of chip centering and the second chip-in series is connected.Semiconductor chip package of the present invention, compact conformation is simple, can carry out two-side radiation, improve useful life and the reliability of device by conducting strip and base plate.
Accompanying drawing explanation
In order to make content of the present invention be more likely to be clearly understood, below according to a particular embodiment of the invention and by reference to the accompanying drawings, the present invention is further detailed explanation, wherein
The schematic diagram of semiconductor chip package when Fig. 1 is chip exterior non-parallel diode;
The explosive view of semiconductor chip package when Fig. 2 is chip exterior non-parallel diode;
The schematic diagram of semiconductor chip package when Fig. 3 is chip exterior parallel diode;
The explosive view of semiconductor chip package when Fig. 4 is chip exterior parallel diode;
Fig. 5 is the circuit topology figure of semiconductor chip package.
In figure, Reference numeral is expressed as: 1-base plate, 2-chip pair, 3-conducting strip, 4-first diode chip for backlight unit, 5-second diode chip for backlight unit, 11-first conductive region, 12-second conductive region, 13-the 3rd conductive region, 14-the 4th conductive region, 15-the 5th conductive region, 21-first chip, 22-second chip, 31-control end contact zone, 32-join domain, the control end of 211-first chip, the output of 212-first chip, the input of 213-first chip, the input of 221-second chip, the control end of 222-second chip, the output of 223-second chip.
Embodiment
Present embodiments provide a kind of semiconductor chip package, as shown in Figure 1 and Figure 2, comprising:
Base plate 1, it has multiple independently conductive region;
At least one chip, to 2, to be arranged on described base plate 1 and to be electrically connected with described base plate 1;
Conducting strip 3, is arranged on described chip on 2, with described conductive region acting in conjunction, described chip is connected in series to the first chip 21 in 2 and the second chip 22.
Particularly, according to design requirement, base plate 1 can arrange multiple chip to 2, each chip realizes the series connection of the first chip 21 and the second chip 22 by the conducting strip 3 of its correspondence and the acting in conjunction of conductive region to 2.
Preferably, the outer surface of described conducting strip 3 can be fin shape.
Particularly, fin shape includes but not limited to the shapes such as needle-like, column, sheet or aliform, can strengthen the heat dispersion of conducting strip 3 further.
Preferably, described conducting strip 3 can be etched with insulation tank, described conducting strip 3 is divided into control end contact zone 31 and join domain 32;
Described control end contact zone 31 is electrically connected with the control end 211 of described first chip 21, and described join domain 32 is electrically connected with the output 212 of described first chip 21 and the input 221 of described second chip 22.
Particularly, by control end contact zone 31 to control end 211 input control signal of the first chip 21, unlatching or the closedown of the first chip 21 can be controlled; The electrical connection of the output 212 of the first chip 21 and the input 221 of the second chip 22 is achieved by join domain 32, after making electric current flow out to join domain 32 from the output 212 of the first chip 21, the input of the second chip 22 can be flowed into by join domain 32.
Preferably, described conductive region can comprise:
First conductive region 11, is electrically connected with described control end contact zone 31;
Second conductive region 12, is electrically connected with the input 213 of described first chip 21;
3rd conductive region 13, is electrically connected with the control end 222 of described second chip 22;
4th conductive region 14, is electrically connected with the output 223 of described second chip 22;
5th conductive region 15, is electrically connected with described join domain 32.
Particularly, the first conductive region 11 is because be electrically connected with control end contact zone 31, and can pick out end as the control end 211 of the first chip 21, the control signal introducing the first chip 21 from the outside controls it and opens or close; Second conductive region 12, because be electrically connected with the input 213 of the first chip 21, can pick out end as the input 213 of the first chip 21, introduce electric current; 3rd conductive region 13 is because be electrically connected with the control end 222 of the second chip 22, and can pick out end as the control end 222 of the second chip 22, the control signal introducing the second chip 22 from the outside controls it and opens or close; 4th conductive region 14, because be electrically connected with the output 223 of the second chip 22, can pick out end as the output 223 of the second chip 22, the electric current flowed out be drawn from the second chip 22; 5th conductive region 15, because be electrically connected with join domain 32, can pick out end as the input 221 of the output 212 of the first chip 21 and the second chip 22.
Particularly, electric current introduces the input 213 of the first chip 21 from the second conductive region 12, output 212 through the first chip 21 flows into join domain 32, arrive after the 5th conductive region 15 through join domain 32 and return join domain 32, the input 221 of the second chip 22 is flowed into through join domain 32, output 223 through the second chip 22 flows into the 4th conductive region 14, draws through the 4th conductive region 14.
Preferably, the conductive metal layer of described base plate 1 can be etched with many bar insulations groove, described conductive metal layer is divided into multiple independently conductive region.Because insulation tank keeps insulation each other between conductive region, become multiple independently conductive region.
Preferably, described first chip 21 and described second chip 22 are controllable semiconductor chip.
Particularly, controllable semiconductor chip comprises metal-oxide-semiconductor chip, igbt chip, thyristor chip, triode chip etc.Described first chip 21 and described second chip 22 can be same controllable semiconductor chip, also can be different kind controllable semiconductor chips.For triode chip and metal-oxide-semiconductor chip, when the first chip 21 and/or the second chip 22 are triode chip, the base stage of chip is control end, and the collector electrode of chip is input, and the emitter of chip is output; When the first chip 21 and/or the second chip 22 are metal-oxide-semiconductor chip, the grid of chip is control end, and the source electrode of chip is input, and the drain electrode of chip is output.
Fig. 5 is the circuit topology figure of above-mentioned semiconductor chip package, composition graphs 1, Fig. 2 can see, electric current flows into from the second conductive region 12, the input 213 (collector electrode D) of the first chip 21 is flowed into through the second conductive region 12, output 212 (emitter S) through the first chip 21 exports join domain 32 to, after to turn back back join domain 32 through the 5th conductive region 15, the input 221 (collector electrode D) of the second chip 22 is flowed into through join domain 32, output 223 (emitter S) through the second chip 22 flows out to the 4th conductive region 14, through the 4th conductive region 14, electric current is drawn, achieve the series connection of the first chip 21 and the second chip 22.
Preferably, described semiconductor chip package, can also comprise:
First diode chip for backlight unit 4, be arranged on described second conductive region 12, the negative pole of described first diode chip for backlight unit 4 is electrically connected by the input 213 of described second conductive region 12 with described first chip 21, and the positive pole of described first diode chip for backlight unit 4 is electrically connected by the output 212 of described join domain 32 with described first chip 21;
Second diode chip for backlight unit 5, be arranged on described 4th conductive region 14, the positive pole of described second diode chip for backlight unit 5 is electrically connected by the output 223 of described 4th conductive region 14 with described second chip 22, and the negative pole of described second diode chip for backlight unit 5 is electrically connected by the input 221 of described join domain 32 with described second chip 22.
Particularly, if when there is no integrated diode in chip, external diode chip for backlight unit can be protected by chip, if in chip during integrated diode, external high-performance diode chip for backlight unit raising chip can be protected or reduce the switching loss of diode.
As shown in Figure 5, composition graphs 3 and Fig. 4, can see, the positive pole of the first diode chip for backlight unit 4 is electrically connected with the output 212 (emitter S) of the first chip 21 by join domain 32, and the negative pole of the first diode chip for backlight unit 4 is electrically connected with the input 213 (collector electrode D) of described first chip 21 by described second conductive region 12; The positive pole of the second diode chip for backlight unit 5 is electrically connected with the output 223 (emitter S) of described second chip 22 by described 4th conductive region 14, and the negative pole of described second diode chip for backlight unit 5 is electrically connected with the input 221 (collector electrode D) of described second chip 22 by described join domain 32.
Preferably, described base plate 1 can comprise and covers copper ceramic wafer, aluminium base etc. with insulating barrier, and semiconductor chip package can be made to have good thermal diffusivity and conductivity.Can certainly replace ceramic layer with other insulating barrier, the conductive metal layer of base plate 1 can be the metal level such as layers of copper, aluminium lamination.
Preferably, described conducting strip 3 can be flexible copper thin slice.Therefore, conducting strip 3 has good stickiness and conductivity.Certain conducting strip 3 also can be the sheet metal of other flexibility, such as flexible aluminum slice.
Semiconductor chip package described in the present embodiment, compact conformation is simple, can carry out two-side radiation, improve useful life and the reliability of device by conducting strip and base plate.
Obviously, above-described embodiment is only for clearly example being described, and the restriction not to execution mode.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all execution modes.And thus the apparent change of extending out or variation be still among the protection range of the invention.
Claims (9)
1. a semiconductor chip package, is characterized in that, comprising:
Base plate (1), it has multiple independently conductive region;
At least one chip, to (2), is arranged on described base plate (1) and goes up and be electrically connected with described base plate (1);
Conducting strip (3), is arranged on described chip on (2), with described conductive region acting in conjunction, described chip is connected in series to the first chip (21) in (2) and the second chip (22).
2. semiconductor chip package according to claim 1, is characterized in that, the outer surface of described conducting strip (3) is fin shape.
3. semiconductor chip package according to claim 1, is characterized in that:
(3) are etched with insulation tank to described conducting strip, described conducting strip (3) are divided into control end contact zone (31) and join domain (32);
Described control end contact zone (31) is electrically connected with the control end (211) of described first chip (21), and described join domain (32) is electrically connected with the output (212) of described first chip (21) and the input (221) of described second chip (22).
4. semiconductor chip package according to claim 3, is characterized in that, described conductive region comprises:
First conductive region (11), is electrically connected with described control end contact zone (31);
Second conductive region (12), is electrically connected with the input (213) of described first chip (21);
3rd conductive region (13), is electrically connected with the control end (222) of described second chip (22);
4th conductive region (14), is electrically connected with the output (223) of described second chip (22);
5th conductive region (15), is electrically connected with described join domain (32).
5. semiconductor chip package according to claim 1, is characterized in that, the conductive metal layer of described base plate (1) is etched with many bar insulations groove, and described conductive metal layer is divided into multiple independently conductive region.
6. semiconductor chip package according to claim 4, is characterized in that, also comprises:
First diode chip for backlight unit (4), be arranged on described second conductive region (12), the negative pole of described first diode chip for backlight unit (4) is electrically connected with the input (213) of described first chip (21) by described second conductive region (12), and the positive pole of described first diode chip for backlight unit (4) is electrically connected with the output (212) of described first chip (21) by described join domain (32);
Second diode chip for backlight unit (5), be arranged on described 4th conductive region (14), the positive pole of described second diode chip for backlight unit (5) is electrically connected with the output (223) of described second chip (22) by described 4th conductive region (14), and the negative pole of described second diode chip for backlight unit (5) is electrically connected with the input (221) of described second chip (22) by described join domain (32).
7. semiconductor chip package according to claim 1, is characterized in that, described first chip (21) and described second chip (22) are controllable semiconductor chip.
8. semiconductor chip package according to claim 1, is characterized in that, described base plate (1) comprises and covers copper ceramic wafer, aluminium base with insulating barrier.
9. semiconductor chip package according to claim 1, is characterized in that, described conducting strip (3) is flexible copper thin slice.
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| CN201410708696.3A CN104465605A (en) | 2014-11-27 | 2014-11-27 | Semiconductor chip packaging structure |
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| CN201410708696.3A CN104465605A (en) | 2014-11-27 | 2014-11-27 | Semiconductor chip packaging structure |
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